ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV64IMACFD_RV64MInstr.cpp
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1 
8 #include "RV64IMACFDArch.h"
9 #include "RV64IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // MULW ------------------------------------------------------------------------
16 static InstructionDefinition mulw_rd_rs1_rs2 (
17  ISA32_RV64IMACFD,
18  "mulw",
19  (uint32_t) 0x200003b,
20  (uint32_t) 0xfe00707f,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 etiss_uint8 rd = 0;
30 static BitArrayRange R_rd_0(11, 7);
31 rd += R_rd_0.read(ba) << 0;
32 etiss_uint8 rs1 = 0;
33 static BitArrayRange R_rs1_0(19, 15);
34 rs1 += R_rs1_0.read(ba) << 0;
35 etiss_uint8 rs2 = 0;
36 static BitArrayRange R_rs2_0(24, 20);
37 rs2 += R_rs2_0.read(ba) << 0;
38 
39 // -----------------------------------------------------------------------------
40 
41  {
42  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
43 
44  cp.code() = std::string("//MULW\n");
45 
46 // -----------------------------------------------------------------------------
47 cp.code() += "etiss_coverage_count(1, 209);\n";
48 { // block
49 cp.code() += "etiss_coverage_count(1, 1169);\n";
50 cp.code() += "{ // block\n";
51 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
52 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
53 cp.code() += "} // block\n";
54 } // block
55 { // block
56 cp.code() += "etiss_coverage_count(1, 7771);\n";
57 cp.code() += "{ // block\n";
58 cp.code() += "etiss_coverage_count(1, 7737);\n";
59 if ((rd % 32ULL) != 0LL) { // conditional
60 cp.code() += "etiss_coverage_count(5, 7743, 7740, 7738, 7741, 7742);\n";
61 { // block
62 cp.code() += "etiss_coverage_count(1, 7770);\n";
63 cp.code() += "{ // block\n";
64 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) * (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]))));\n";
65 cp.code() += "etiss_coverage_count(16, 7769, 7748, 7747, 7745, 7768, 7766, 7763, 7755, 7753, 7752, 7750, 7762, 7760, 7759, 7757, 7764);\n";
66 cp.code() += "} // block\n";
67 } // block
68 } // conditional
69 cp.code() += "} // block\n";
70 } // block
71 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
72 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
73 // -----------------------------------------------------------------------------
74  cp.getAffectedRegisters().add("instructionPointer", 32);
75  }
76 
77  return true;
78  },
79  0,
80  [] (BitArray & ba, Instruction & instr)
81  {
82 // -----------------------------------------------------------------------------
83 etiss_uint8 rd = 0;
84 static BitArrayRange R_rd_0(11, 7);
85 rd += R_rd_0.read(ba) << 0;
86 etiss_uint8 rs1 = 0;
87 static BitArrayRange R_rs1_0(19, 15);
88 rs1 += R_rs1_0.read(ba) << 0;
89 etiss_uint8 rs2 = 0;
90 static BitArrayRange R_rs2_0(24, 20);
91 rs2 += R_rs2_0.read(ba) << 0;
92 
93 // -----------------------------------------------------------------------------
94 
95  std::stringstream ss;
96 // -----------------------------------------------------------------------------
97 ss << "mulw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
98 // -----------------------------------------------------------------------------
99  return ss.str();
100  }
101 );
102 
103 // DIVW ------------------------------------------------------------------------
104 static InstructionDefinition divw_rd_rs1_rs2 (
105  ISA32_RV64IMACFD,
106  "divw",
107  (uint32_t) 0x200403b,
108  (uint32_t) 0xfe00707f,
109  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
110  {
111 
112 // -----------------------------------------------------------------------------
113 
114 // -----------------------------------------------------------------------------
115 
116 // -----------------------------------------------------------------------------
117 etiss_uint8 rd = 0;
118 static BitArrayRange R_rd_0(11, 7);
119 rd += R_rd_0.read(ba) << 0;
120 etiss_uint8 rs1 = 0;
121 static BitArrayRange R_rs1_0(19, 15);
122 rs1 += R_rs1_0.read(ba) << 0;
123 etiss_uint8 rs2 = 0;
124 static BitArrayRange R_rs2_0(24, 20);
125 rs2 += R_rs2_0.read(ba) << 0;
126 
127 // -----------------------------------------------------------------------------
128 
129  {
130  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
131 
132  cp.code() = std::string("//DIVW\n");
133 
134 // -----------------------------------------------------------------------------
135 cp.code() += "etiss_coverage_count(1, 210);\n";
136 { // block
137 cp.code() += "etiss_coverage_count(1, 1169);\n";
138 cp.code() += "{ // block\n";
139 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
140 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
141 cp.code() += "} // block\n";
142 } // block
143 { // block
144 cp.code() += "etiss_coverage_count(1, 7859);\n";
145 cp.code() += "{ // block\n";
146 cp.code() += "etiss_coverage_count(1, 7772);\n";
147 if ((rd % 32ULL) != 0LL) { // conditional
148 cp.code() += "etiss_coverage_count(5, 7778, 7775, 7773, 7776, 7777);\n";
149 { // block
150 cp.code() += "etiss_coverage_count(1, 7858);\n";
151 cp.code() += "{ // block\n";
152 cp.code() += "etiss_coverage_count(1, 7779);\n";
153 cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0LL) { // conditional\n";
154 cp.code() += "etiss_coverage_count(5, 7786, 7784, 7783, 7781, 7785);\n";
155 { // block
156 cp.code() += "etiss_coverage_count(1, 7849);\n";
157 cp.code() += "{ // block\n";
158 etiss_int32 MMIN = -2147483648LL;
159 cp.code() += "etiss_coverage_count(1, 7793);\n";
160 cp.code() += "etiss_coverage_count(1, 7794);\n";
161 cp.code() += "if ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) == " + std::to_string(MMIN) + "LL && (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) == -1LL) { // conditional\n";
162 cp.code() += "etiss_coverage_count(12, 7814, 7803, 7801, 7799, 7798, 7796, 7802, 7813, 7810, 7808, 7807, 7805);\n";
163 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -2147483648LL;\n";
164 cp.code() += "etiss_coverage_count(4, 7824, 7819, 7818, 7816);\n";
165 cp.code() += "} // conditional\n";
166 cp.code() += "else { // conditional\n";
167 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) / (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])));\n";
168 cp.code() += "etiss_coverage_count(15, 7848, 7829, 7828, 7826, 7847, 7844, 7836, 7834, 7833, 7831, 7843, 7841, 7840, 7838, 7845);\n";
169 cp.code() += "} // conditional\n";
170 cp.code() += "} // block\n";
171 } // block
172 cp.code() += "} // conditional\n";
173 cp.code() += "else { // conditional\n";
174 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -1LL;\n";
175 cp.code() += "etiss_coverage_count(4, 7857, 7854, 7853, 7851);\n";
176 cp.code() += "} // conditional\n";
177 cp.code() += "} // block\n";
178 } // block
179 } // conditional
180 cp.code() += "} // block\n";
181 } // block
182 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
183 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
184 // -----------------------------------------------------------------------------
185  cp.getAffectedRegisters().add("instructionPointer", 32);
186  }
187 
188  return true;
189  },
190  0,
191  [] (BitArray & ba, Instruction & instr)
192  {
193 // -----------------------------------------------------------------------------
194 etiss_uint8 rd = 0;
195 static BitArrayRange R_rd_0(11, 7);
196 rd += R_rd_0.read(ba) << 0;
197 etiss_uint8 rs1 = 0;
198 static BitArrayRange R_rs1_0(19, 15);
199 rs1 += R_rs1_0.read(ba) << 0;
200 etiss_uint8 rs2 = 0;
201 static BitArrayRange R_rs2_0(24, 20);
202 rs2 += R_rs2_0.read(ba) << 0;
203 
204 // -----------------------------------------------------------------------------
205 
206  std::stringstream ss;
207 // -----------------------------------------------------------------------------
208 ss << "divw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
209 // -----------------------------------------------------------------------------
210  return ss.str();
211  }
212 );
213 
214 // DIVUW -----------------------------------------------------------------------
215 static InstructionDefinition divuw_rd_rs1_rs2 (
216  ISA32_RV64IMACFD,
217  "divuw",
218  (uint32_t) 0x200503b,
219  (uint32_t) 0xfe00707f,
220  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
221  {
222 
223 // -----------------------------------------------------------------------------
224 
225 // -----------------------------------------------------------------------------
226 
227 // -----------------------------------------------------------------------------
228 etiss_uint8 rd = 0;
229 static BitArrayRange R_rd_0(11, 7);
230 rd += R_rd_0.read(ba) << 0;
231 etiss_uint8 rs1 = 0;
232 static BitArrayRange R_rs1_0(19, 15);
233 rs1 += R_rs1_0.read(ba) << 0;
234 etiss_uint8 rs2 = 0;
235 static BitArrayRange R_rs2_0(24, 20);
236 rs2 += R_rs2_0.read(ba) << 0;
237 
238 // -----------------------------------------------------------------------------
239 
240  {
241  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
242 
243  cp.code() = std::string("//DIVUW\n");
244 
245 // -----------------------------------------------------------------------------
246 cp.code() += "etiss_coverage_count(1, 211);\n";
247 { // block
248 cp.code() += "etiss_coverage_count(1, 1169);\n";
249 cp.code() += "{ // block\n";
250 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
251 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
252 cp.code() += "} // block\n";
253 } // block
254 { // block
255 cp.code() += "etiss_coverage_count(1, 7911);\n";
256 cp.code() += "{ // block\n";
257 cp.code() += "etiss_coverage_count(1, 7860);\n";
258 if ((rd % 32ULL) != 0LL) { // conditional
259 cp.code() += "etiss_coverage_count(5, 7866, 7863, 7861, 7864, 7865);\n";
260 { // block
261 cp.code() += "etiss_coverage_count(1, 7910);\n";
262 cp.code() += "{ // block\n";
263 cp.code() += "etiss_coverage_count(1, 7867);\n";
264 cp.code() += "if ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) != 0LL) { // conditional\n";
265 cp.code() += "etiss_coverage_count(6, 7876, 7874, 7872, 7871, 7869, 7875);\n";
266 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) / (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]))));\n";
267 cp.code() += "etiss_coverage_count(16, 7901, 7881, 7880, 7878, 7900, 7898, 7896, 7888, 7886, 7885, 7883, 7895, 7893, 7892, 7890, 7897);\n";
268 cp.code() += "} // conditional\n";
269 cp.code() += "else { // conditional\n";
270 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -1LL;\n";
271 cp.code() += "etiss_coverage_count(4, 7909, 7906, 7905, 7903);\n";
272 cp.code() += "} // conditional\n";
273 cp.code() += "} // block\n";
274 } // block
275 } // conditional
276 cp.code() += "} // block\n";
277 } // block
278 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
279 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
280 // -----------------------------------------------------------------------------
281  cp.getAffectedRegisters().add("instructionPointer", 32);
282  }
283 
284  return true;
285  },
286  0,
287  [] (BitArray & ba, Instruction & instr)
288  {
289 // -----------------------------------------------------------------------------
290 etiss_uint8 rd = 0;
291 static BitArrayRange R_rd_0(11, 7);
292 rd += R_rd_0.read(ba) << 0;
293 etiss_uint8 rs1 = 0;
294 static BitArrayRange R_rs1_0(19, 15);
295 rs1 += R_rs1_0.read(ba) << 0;
296 etiss_uint8 rs2 = 0;
297 static BitArrayRange R_rs2_0(24, 20);
298 rs2 += R_rs2_0.read(ba) << 0;
299 
300 // -----------------------------------------------------------------------------
301 
302  std::stringstream ss;
303 // -----------------------------------------------------------------------------
304 ss << "divuw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
305 // -----------------------------------------------------------------------------
306  return ss.str();
307  }
308 );
309 
310 // REMW ------------------------------------------------------------------------
311 static InstructionDefinition remw_rd_rs1_rs2 (
312  ISA32_RV64IMACFD,
313  "remw",
314  (uint32_t) 0x200603b,
315  (uint32_t) 0xfe00707f,
316  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
317  {
318 
319 // -----------------------------------------------------------------------------
320 
321 // -----------------------------------------------------------------------------
322 
323 // -----------------------------------------------------------------------------
324 etiss_uint8 rd = 0;
325 static BitArrayRange R_rd_0(11, 7);
326 rd += R_rd_0.read(ba) << 0;
327 etiss_uint8 rs1 = 0;
328 static BitArrayRange R_rs1_0(19, 15);
329 rs1 += R_rs1_0.read(ba) << 0;
330 etiss_uint8 rs2 = 0;
331 static BitArrayRange R_rs2_0(24, 20);
332 rs2 += R_rs2_0.read(ba) << 0;
333 
334 // -----------------------------------------------------------------------------
335 
336  {
337  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
338 
339  cp.code() = std::string("//REMW\n");
340 
341 // -----------------------------------------------------------------------------
342 cp.code() += "etiss_coverage_count(1, 212);\n";
343 { // block
344 cp.code() += "etiss_coverage_count(1, 1169);\n";
345 cp.code() += "{ // block\n";
346 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
347 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
348 cp.code() += "} // block\n";
349 } // block
350 { // block
351 cp.code() += "etiss_coverage_count(1, 8004);\n";
352 cp.code() += "{ // block\n";
353 cp.code() += "etiss_coverage_count(1, 7912);\n";
354 if ((rd % 32ULL) != 0LL) { // conditional
355 cp.code() += "etiss_coverage_count(5, 7918, 7915, 7913, 7916, 7917);\n";
356 { // block
357 cp.code() += "etiss_coverage_count(1, 8003);\n";
358 cp.code() += "{ // block\n";
359 cp.code() += "etiss_coverage_count(1, 7919);\n";
360 cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0LL) { // conditional\n";
361 cp.code() += "etiss_coverage_count(5, 7926, 7924, 7923, 7921, 7925);\n";
362 { // block
363 cp.code() += "etiss_coverage_count(1, 7986);\n";
364 cp.code() += "{ // block\n";
365 etiss_int32 MMIN = -2147483648LL;
366 cp.code() += "etiss_coverage_count(1, 7933);\n";
367 cp.code() += "etiss_coverage_count(1, 7934);\n";
368 cp.code() += "if ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) == " + std::to_string(MMIN) + "LL && (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) == -1LL) { // conditional\n";
369 cp.code() += "etiss_coverage_count(12, 7954, 7943, 7941, 7939, 7938, 7936, 7942, 7953, 7950, 7948, 7947, 7945);\n";
370 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = 0LL;\n";
371 cp.code() += "etiss_coverage_count(5, 7961, 7959, 7958, 7956, 7960);\n";
372 cp.code() += "} // conditional\n";
373 cp.code() += "else { // conditional\n";
374 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) % (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])));\n";
375 cp.code() += "etiss_coverage_count(15, 7985, 7966, 7965, 7963, 7984, 7981, 7973, 7971, 7970, 7968, 7980, 7978, 7977, 7975, 7982);\n";
376 cp.code() += "} // conditional\n";
377 cp.code() += "} // block\n";
378 } // block
379 cp.code() += "} // conditional\n";
380 cp.code() += "else { // conditional\n";
381 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])));\n";
382 cp.code() += "etiss_coverage_count(10, 8002, 7991, 7990, 7988, 8001, 7998, 7996, 7995, 7993, 7999);\n";
383 cp.code() += "} // conditional\n";
384 cp.code() += "} // block\n";
385 } // block
386 } // conditional
387 cp.code() += "} // block\n";
388 } // block
389 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
390 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
391 // -----------------------------------------------------------------------------
392  cp.getAffectedRegisters().add("instructionPointer", 32);
393  }
394 
395  return true;
396  },
397  0,
398  [] (BitArray & ba, Instruction & instr)
399  {
400 // -----------------------------------------------------------------------------
401 etiss_uint8 rd = 0;
402 static BitArrayRange R_rd_0(11, 7);
403 rd += R_rd_0.read(ba) << 0;
404 etiss_uint8 rs1 = 0;
405 static BitArrayRange R_rs1_0(19, 15);
406 rs1 += R_rs1_0.read(ba) << 0;
407 etiss_uint8 rs2 = 0;
408 static BitArrayRange R_rs2_0(24, 20);
409 rs2 += R_rs2_0.read(ba) << 0;
410 
411 // -----------------------------------------------------------------------------
412 
413  std::stringstream ss;
414 // -----------------------------------------------------------------------------
415 ss << "remw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
416 // -----------------------------------------------------------------------------
417  return ss.str();
418  }
419 );
420 
421 // REMUW -----------------------------------------------------------------------
422 static InstructionDefinition remuw_rd_rs1_rs2 (
423  ISA32_RV64IMACFD,
424  "remuw",
425  (uint32_t) 0x200703b,
426  (uint32_t) 0xfe00707f,
427  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
428  {
429 
430 // -----------------------------------------------------------------------------
431 
432 // -----------------------------------------------------------------------------
433 
434 // -----------------------------------------------------------------------------
435 etiss_uint8 rd = 0;
436 static BitArrayRange R_rd_0(11, 7);
437 rd += R_rd_0.read(ba) << 0;
438 etiss_uint8 rs1 = 0;
439 static BitArrayRange R_rs1_0(19, 15);
440 rs1 += R_rs1_0.read(ba) << 0;
441 etiss_uint8 rs2 = 0;
442 static BitArrayRange R_rs2_0(24, 20);
443 rs2 += R_rs2_0.read(ba) << 0;
444 
445 // -----------------------------------------------------------------------------
446 
447  {
448  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
449 
450  cp.code() = std::string("//REMUW\n");
451 
452 // -----------------------------------------------------------------------------
453 cp.code() += "etiss_coverage_count(1, 213);\n";
454 { // block
455 cp.code() += "etiss_coverage_count(1, 1169);\n";
456 cp.code() += "{ // block\n";
457 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
458 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
459 cp.code() += "} // block\n";
460 } // block
461 { // block
462 cp.code() += "etiss_coverage_count(1, 8064);\n";
463 cp.code() += "{ // block\n";
464 cp.code() += "etiss_coverage_count(1, 8005);\n";
465 if ((rd % 32ULL) != 0LL) { // conditional
466 cp.code() += "etiss_coverage_count(5, 8011, 8008, 8006, 8009, 8010);\n";
467 { // block
468 cp.code() += "etiss_coverage_count(1, 8063);\n";
469 cp.code() += "{ // block\n";
470 cp.code() += "etiss_coverage_count(1, 8012);\n";
471 cp.code() += "if ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) != 0LL) { // conditional\n";
472 cp.code() += "etiss_coverage_count(6, 8021, 8019, 8017, 8016, 8014, 8020);\n";
473 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) % (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]))));\n";
474 cp.code() += "etiss_coverage_count(16, 8046, 8026, 8025, 8023, 8045, 8043, 8041, 8033, 8031, 8030, 8028, 8040, 8038, 8037, 8035, 8042);\n";
475 cp.code() += "} // conditional\n";
476 cp.code() += "else { // conditional\n";
477 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])));\n";
478 cp.code() += "etiss_coverage_count(10, 8062, 8051, 8050, 8048, 8061, 8058, 8056, 8055, 8053, 8059);\n";
479 cp.code() += "} // conditional\n";
480 cp.code() += "} // block\n";
481 } // block
482 } // conditional
483 cp.code() += "} // block\n";
484 } // block
485 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
486 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
487 // -----------------------------------------------------------------------------
488  cp.getAffectedRegisters().add("instructionPointer", 32);
489  }
490 
491  return true;
492  },
493  0,
494  [] (BitArray & ba, Instruction & instr)
495  {
496 // -----------------------------------------------------------------------------
497 etiss_uint8 rd = 0;
498 static BitArrayRange R_rd_0(11, 7);
499 rd += R_rd_0.read(ba) << 0;
500 etiss_uint8 rs1 = 0;
501 static BitArrayRange R_rs1_0(19, 15);
502 rs1 += R_rs1_0.read(ba) << 0;
503 etiss_uint8 rs2 = 0;
504 static BitArrayRange R_rs2_0(24, 20);
505 rs2 += R_rs2_0.read(ba) << 0;
506 
507 // -----------------------------------------------------------------------------
508 
509  std::stringstream ss;
510 // -----------------------------------------------------------------------------
511 ss << "remuw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
512 // -----------------------------------------------------------------------------
513  return ss.str();
514  }
515 );
ISA32_RV64IMACFD
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
mulw_rd_rs1_rs2
static InstructionDefinition mulw_rd_rs1_rs2(ISA32_RV64IMACFD, "mulw",(uint32_t) 0x200003b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MULW\n");cp.code()+="etiss_coverage_count(1, 209);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7771);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 7737);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 7743, 7740, 7738, 7741, 7742);\n";{ cp.code()+="etiss_coverage_count(1, 7770);\n";cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)((etiss_int32)(((etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) * (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]))));\n";cp.code()+="etiss_coverage_count(16, 7769, 7748, 7747, 7745, 7768, 7766, 7763, 7755, 7753, 7752, 7750, 7762, 7760, 7759, 7757, 7764);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "mulw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
divw_rd_rs1_rs2
static InstructionDefinition divw_rd_rs1_rs2(ISA32_RV64IMACFD, "divw",(uint32_t) 0x200403b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//DIVW\n");cp.code()+="etiss_coverage_count(1, 210);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7859);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 7772);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 7778, 7775, 7773, 7776, 7777);\n";{ cp.code()+="etiss_coverage_count(1, 7858);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 7779);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 7786, 7784, 7783, 7781, 7785);\n";{ cp.code()+="etiss_coverage_count(1, 7849);\n";cp.code()+="{ // block\n";etiss_int32 MMIN=-2147483648LL;cp.code()+="etiss_coverage_count(1, 7793);\n";cp.code()+="etiss_coverage_count(1, 7794);\n";cp.code()+="if ((etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) == "+std::to_string(MMIN)+"LL && (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) == -1LL) { // conditional\n";cp.code()+="etiss_coverage_count(12, 7814, 7803, 7801, 7799, 7798, 7796, 7802, 7813, 7810, 7808, 7807, 7805);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = -2147483648LL;\n";cp.code()+="etiss_coverage_count(4, 7824, 7819, 7818, 7816);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) / (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])));\n";cp.code()+="etiss_coverage_count(15, 7848, 7829, 7828, 7826, 7847, 7844, 7836, 7834, 7833, 7831, 7843, 7841, 7840, 7838, 7845);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = -1LL;\n";cp.code()+="etiss_coverage_count(4, 7857, 7854, 7853, 7851);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "divw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
divuw_rd_rs1_rs2
static InstructionDefinition divuw_rd_rs1_rs2(ISA32_RV64IMACFD, "divuw",(uint32_t) 0x200503b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//DIVUW\n");cp.code()+="etiss_coverage_count(1, 211);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7911);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 7860);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 7866, 7863, 7861, 7864, 7865);\n";{ cp.code()+="etiss_coverage_count(1, 7910);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 7867);\n";cp.code()+="if ((etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(6, 7876, 7874, 7872, 7871, 7869, 7875);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)((etiss_int32)(((etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) / (etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]))));\n";cp.code()+="etiss_coverage_count(16, 7901, 7881, 7880, 7878, 7900, 7898, 7896, 7888, 7886, 7885, 7883, 7895, 7893, 7892, 7890, 7897);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = -1LL;\n";cp.code()+="etiss_coverage_count(4, 7909, 7906, 7905, 7903);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "divuw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
remuw_rd_rs1_rs2
static InstructionDefinition remuw_rd_rs1_rs2(ISA32_RV64IMACFD, "remuw",(uint32_t) 0x200703b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//REMUW\n");cp.code()+="etiss_coverage_count(1, 213);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8064);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 8005);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8011, 8008, 8006, 8009, 8010);\n";{ cp.code()+="etiss_coverage_count(1, 8063);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 8012);\n";cp.code()+="if ((etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(6, 8021, 8019, 8017, 8016, 8014, 8020);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)((etiss_int32)(((etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) % (etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]))));\n";cp.code()+="etiss_coverage_count(16, 8046, 8026, 8025, 8023, 8045, 8043, 8041, 8033, 8031, 8030, 8028, 8040, 8038, 8037, 8035, 8042);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL])));\n";cp.code()+="etiss_coverage_count(10, 8062, 8051, 8050, 8048, 8061, 8058, 8056, 8055, 8053, 8059);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "remuw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
remw_rd_rs1_rs2
static InstructionDefinition remw_rd_rs1_rs2(ISA32_RV64IMACFD, "remw",(uint32_t) 0x200603b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//REMW\n");cp.code()+="etiss_coverage_count(1, 212);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8004);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 7912);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 7918, 7915, 7913, 7916, 7917);\n";{ cp.code()+="etiss_coverage_count(1, 8003);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 7919);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 7926, 7924, 7923, 7921, 7925);\n";{ cp.code()+="etiss_coverage_count(1, 7986);\n";cp.code()+="{ // block\n";etiss_int32 MMIN=-2147483648LL;cp.code()+="etiss_coverage_count(1, 7933);\n";cp.code()+="etiss_coverage_count(1, 7934);\n";cp.code()+="if ((etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) == "+std::to_string(MMIN)+"LL && (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) == -1LL) { // conditional\n";cp.code()+="etiss_coverage_count(12, 7954, 7943, 7941, 7939, 7938, 7936, 7942, 7953, 7950, 7948, 7947, 7945);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = 0LL;\n";cp.code()+="etiss_coverage_count(5, 7961, 7959, 7958, 7956, 7960);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) % (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])));\n";cp.code()+="etiss_coverage_count(15, 7985, 7966, 7965, 7963, 7984, 7981, 7973, 7971, 7970, 7968, 7980, 7978, 7977, 7975, 7982);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL])));\n";cp.code()+="etiss_coverage_count(10, 8002, 7991, 7990, 7988, 8001, 7998, 7996, 7995, 7993, 7999);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "remw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
uint32_t
static __inline__ uint32_t
Definition: arm_cde.h:25
etiss_uint8
uint8_t etiss_uint8
Definition: types.h:87
etiss_int32
int32_t etiss_int32
Definition: types.h:92
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:386
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition: Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition: Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
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