ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV64IMACFD_RV64MInstr.cpp
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1 
8 #include "RV64IMACFDArch.h"
9 #include "RV64IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // MULW ------------------------------------------------------------------------
16 static InstructionDefinition mulw_rd_rs1_rs2 (
17  ISA32_RV64IMACFD,
18  "mulw",
19  (uint32_t) 0x200003b,
20  (uint32_t) 0xfe00707f,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 etiss_uint8 rd = 0;
30 static BitArrayRange R_rd_0(11, 7);
31 rd += R_rd_0.read(ba) << 0;
32 etiss_uint8 rs1 = 0;
33 static BitArrayRange R_rs1_0(19, 15);
34 rs1 += R_rs1_0.read(ba) << 0;
35 etiss_uint8 rs2 = 0;
36 static BitArrayRange R_rs2_0(24, 20);
37 rs2 += R_rs2_0.read(ba) << 0;
38 
39 // -----------------------------------------------------------------------------
40 
41  {
42  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
43 
44  cp.code() = std::string("//MULW\n");
45 
46 // -----------------------------------------------------------------------------
47 { // block
48 cp.code() += "{ // block\n";
49 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
50 cp.code() += "} // block\n";
51 } // block
52 { // block
53 cp.code() += "{ // block\n";
54 if ((rd % 32ULL) != 0LL) { // conditional
55 { // block
56 cp.code() += "{ // block\n";
57 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) * (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]))));\n";
58 cp.code() += "} // block\n";
59 } // block
60 } // conditional
61 cp.code() += "} // block\n";
62 } // block
63 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
64 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
65 // -----------------------------------------------------------------------------
66  cp.getAffectedRegisters().add("instructionPointer", 32);
67  }
68 
69  return true;
70  },
71  0,
72  [] (BitArray & ba, Instruction & instr)
73  {
74 // -----------------------------------------------------------------------------
75 etiss_uint8 rd = 0;
76 static BitArrayRange R_rd_0(11, 7);
77 rd += R_rd_0.read(ba) << 0;
78 etiss_uint8 rs1 = 0;
79 static BitArrayRange R_rs1_0(19, 15);
80 rs1 += R_rs1_0.read(ba) << 0;
81 etiss_uint8 rs2 = 0;
82 static BitArrayRange R_rs2_0(24, 20);
83 rs2 += R_rs2_0.read(ba) << 0;
84 
85 // -----------------------------------------------------------------------------
86 
87  std::stringstream ss;
88 // -----------------------------------------------------------------------------
89 ss << "mulw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
90 // -----------------------------------------------------------------------------
91  return ss.str();
92  }
93 );
94 
95 // DIVW ------------------------------------------------------------------------
96 static InstructionDefinition divw_rd_rs1_rs2 (
97  ISA32_RV64IMACFD,
98  "divw",
99  (uint32_t) 0x200403b,
100  (uint32_t) 0xfe00707f,
101  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
102  {
103 
104 // -----------------------------------------------------------------------------
105 
106 // -----------------------------------------------------------------------------
107 
108 // -----------------------------------------------------------------------------
109 etiss_uint8 rd = 0;
110 static BitArrayRange R_rd_0(11, 7);
111 rd += R_rd_0.read(ba) << 0;
112 etiss_uint8 rs1 = 0;
113 static BitArrayRange R_rs1_0(19, 15);
114 rs1 += R_rs1_0.read(ba) << 0;
115 etiss_uint8 rs2 = 0;
116 static BitArrayRange R_rs2_0(24, 20);
117 rs2 += R_rs2_0.read(ba) << 0;
118 
119 // -----------------------------------------------------------------------------
120 
121  {
122  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
123 
124  cp.code() = std::string("//DIVW\n");
125 
126 // -----------------------------------------------------------------------------
127 { // block
128 cp.code() += "{ // block\n";
129 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
130 cp.code() += "} // block\n";
131 } // block
132 { // block
133 cp.code() += "{ // block\n";
134 if ((rd % 32ULL) != 0LL) { // conditional
135 { // block
136 cp.code() += "{ // block\n";
137 cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0LL) { // conditional\n";
138 { // block
139 cp.code() += "{ // block\n";
140 etiss_int32 MMIN = -2147483648LL;
141 cp.code() += "if ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) == " + std::to_string(MMIN) + "LL && (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) == -1LL) { // conditional\n";
142 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -2147483648LL;\n";
143 cp.code() += "} // conditional\n";
144 cp.code() += "else { // conditional\n";
145 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) / (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])));\n";
146 cp.code() += "} // conditional\n";
147 cp.code() += "} // block\n";
148 } // block
149 cp.code() += "} // conditional\n";
150 cp.code() += "else { // conditional\n";
151 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -1LL;\n";
152 cp.code() += "} // conditional\n";
153 cp.code() += "} // block\n";
154 } // block
155 } // conditional
156 cp.code() += "} // block\n";
157 } // block
158 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
159 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
160 // -----------------------------------------------------------------------------
161  cp.getAffectedRegisters().add("instructionPointer", 32);
162  }
163 
164  return true;
165  },
166  0,
167  [] (BitArray & ba, Instruction & instr)
168  {
169 // -----------------------------------------------------------------------------
170 etiss_uint8 rd = 0;
171 static BitArrayRange R_rd_0(11, 7);
172 rd += R_rd_0.read(ba) << 0;
173 etiss_uint8 rs1 = 0;
174 static BitArrayRange R_rs1_0(19, 15);
175 rs1 += R_rs1_0.read(ba) << 0;
176 etiss_uint8 rs2 = 0;
177 static BitArrayRange R_rs2_0(24, 20);
178 rs2 += R_rs2_0.read(ba) << 0;
179 
180 // -----------------------------------------------------------------------------
181 
182  std::stringstream ss;
183 // -----------------------------------------------------------------------------
184 ss << "divw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
185 // -----------------------------------------------------------------------------
186  return ss.str();
187  }
188 );
189 
190 // DIVUW -----------------------------------------------------------------------
191 static InstructionDefinition divuw_rd_rs1_rs2 (
192  ISA32_RV64IMACFD,
193  "divuw",
194  (uint32_t) 0x200503b,
195  (uint32_t) 0xfe00707f,
196  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
197  {
198 
199 // -----------------------------------------------------------------------------
200 
201 // -----------------------------------------------------------------------------
202 
203 // -----------------------------------------------------------------------------
204 etiss_uint8 rd = 0;
205 static BitArrayRange R_rd_0(11, 7);
206 rd += R_rd_0.read(ba) << 0;
207 etiss_uint8 rs1 = 0;
208 static BitArrayRange R_rs1_0(19, 15);
209 rs1 += R_rs1_0.read(ba) << 0;
210 etiss_uint8 rs2 = 0;
211 static BitArrayRange R_rs2_0(24, 20);
212 rs2 += R_rs2_0.read(ba) << 0;
213 
214 // -----------------------------------------------------------------------------
215 
216  {
217  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
218 
219  cp.code() = std::string("//DIVUW\n");
220 
221 // -----------------------------------------------------------------------------
222 { // block
223 cp.code() += "{ // block\n";
224 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
225 cp.code() += "} // block\n";
226 } // block
227 { // block
228 cp.code() += "{ // block\n";
229 if ((rd % 32ULL) != 0LL) { // conditional
230 { // block
231 cp.code() += "{ // block\n";
232 cp.code() += "if ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) != 0LL) { // conditional\n";
233 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) / (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]))));\n";
234 cp.code() += "} // conditional\n";
235 cp.code() += "else { // conditional\n";
236 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -1LL;\n";
237 cp.code() += "} // conditional\n";
238 cp.code() += "} // block\n";
239 } // block
240 } // conditional
241 cp.code() += "} // block\n";
242 } // block
243 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
244 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
245 // -----------------------------------------------------------------------------
246  cp.getAffectedRegisters().add("instructionPointer", 32);
247  }
248 
249  return true;
250  },
251  0,
252  [] (BitArray & ba, Instruction & instr)
253  {
254 // -----------------------------------------------------------------------------
255 etiss_uint8 rd = 0;
256 static BitArrayRange R_rd_0(11, 7);
257 rd += R_rd_0.read(ba) << 0;
258 etiss_uint8 rs1 = 0;
259 static BitArrayRange R_rs1_0(19, 15);
260 rs1 += R_rs1_0.read(ba) << 0;
261 etiss_uint8 rs2 = 0;
262 static BitArrayRange R_rs2_0(24, 20);
263 rs2 += R_rs2_0.read(ba) << 0;
264 
265 // -----------------------------------------------------------------------------
266 
267  std::stringstream ss;
268 // -----------------------------------------------------------------------------
269 ss << "divuw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
270 // -----------------------------------------------------------------------------
271  return ss.str();
272  }
273 );
274 
275 // REMW ------------------------------------------------------------------------
276 static InstructionDefinition remw_rd_rs1_rs2 (
277  ISA32_RV64IMACFD,
278  "remw",
279  (uint32_t) 0x200603b,
280  (uint32_t) 0xfe00707f,
281  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
282  {
283 
284 // -----------------------------------------------------------------------------
285 
286 // -----------------------------------------------------------------------------
287 
288 // -----------------------------------------------------------------------------
289 etiss_uint8 rd = 0;
290 static BitArrayRange R_rd_0(11, 7);
291 rd += R_rd_0.read(ba) << 0;
292 etiss_uint8 rs1 = 0;
293 static BitArrayRange R_rs1_0(19, 15);
294 rs1 += R_rs1_0.read(ba) << 0;
295 etiss_uint8 rs2 = 0;
296 static BitArrayRange R_rs2_0(24, 20);
297 rs2 += R_rs2_0.read(ba) << 0;
298 
299 // -----------------------------------------------------------------------------
300 
301  {
302  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
303 
304  cp.code() = std::string("//REMW\n");
305 
306 // -----------------------------------------------------------------------------
307 { // block
308 cp.code() += "{ // block\n";
309 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
310 cp.code() += "} // block\n";
311 } // block
312 { // block
313 cp.code() += "{ // block\n";
314 if ((rd % 32ULL) != 0LL) { // conditional
315 { // block
316 cp.code() += "{ // block\n";
317 cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0LL) { // conditional\n";
318 { // block
319 cp.code() += "{ // block\n";
320 etiss_int32 MMIN = -2147483648LL;
321 cp.code() += "if ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) == " + std::to_string(MMIN) + "LL && (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) == -1LL) { // conditional\n";
322 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = 0LL;\n";
323 cp.code() += "} // conditional\n";
324 cp.code() += "else { // conditional\n";
325 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) % (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])));\n";
326 cp.code() += "} // conditional\n";
327 cp.code() += "} // block\n";
328 } // block
329 cp.code() += "} // conditional\n";
330 cp.code() += "else { // conditional\n";
331 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])));\n";
332 cp.code() += "} // conditional\n";
333 cp.code() += "} // block\n";
334 } // block
335 } // conditional
336 cp.code() += "} // block\n";
337 } // block
338 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
339 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
340 // -----------------------------------------------------------------------------
341  cp.getAffectedRegisters().add("instructionPointer", 32);
342  }
343 
344  return true;
345  },
346  0,
347  [] (BitArray & ba, Instruction & instr)
348  {
349 // -----------------------------------------------------------------------------
350 etiss_uint8 rd = 0;
351 static BitArrayRange R_rd_0(11, 7);
352 rd += R_rd_0.read(ba) << 0;
353 etiss_uint8 rs1 = 0;
354 static BitArrayRange R_rs1_0(19, 15);
355 rs1 += R_rs1_0.read(ba) << 0;
356 etiss_uint8 rs2 = 0;
357 static BitArrayRange R_rs2_0(24, 20);
358 rs2 += R_rs2_0.read(ba) << 0;
359 
360 // -----------------------------------------------------------------------------
361 
362  std::stringstream ss;
363 // -----------------------------------------------------------------------------
364 ss << "remw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
365 // -----------------------------------------------------------------------------
366  return ss.str();
367  }
368 );
369 
370 // REMUW -----------------------------------------------------------------------
371 static InstructionDefinition remuw_rd_rs1_rs2 (
372  ISA32_RV64IMACFD,
373  "remuw",
374  (uint32_t) 0x200703b,
375  (uint32_t) 0xfe00707f,
376  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
377  {
378 
379 // -----------------------------------------------------------------------------
380 
381 // -----------------------------------------------------------------------------
382 
383 // -----------------------------------------------------------------------------
384 etiss_uint8 rd = 0;
385 static BitArrayRange R_rd_0(11, 7);
386 rd += R_rd_0.read(ba) << 0;
387 etiss_uint8 rs1 = 0;
388 static BitArrayRange R_rs1_0(19, 15);
389 rs1 += R_rs1_0.read(ba) << 0;
390 etiss_uint8 rs2 = 0;
391 static BitArrayRange R_rs2_0(24, 20);
392 rs2 += R_rs2_0.read(ba) << 0;
393 
394 // -----------------------------------------------------------------------------
395 
396  {
397  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
398 
399  cp.code() = std::string("//REMUW\n");
400 
401 // -----------------------------------------------------------------------------
402 { // block
403 cp.code() += "{ // block\n";
404 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
405 cp.code() += "} // block\n";
406 } // block
407 { // block
408 cp.code() += "{ // block\n";
409 if ((rd % 32ULL) != 0LL) { // conditional
410 { // block
411 cp.code() += "{ // block\n";
412 cp.code() += "if ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) != 0LL) { // conditional\n";
413 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) % (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]))));\n";
414 cp.code() += "} // conditional\n";
415 cp.code() += "else { // conditional\n";
416 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])));\n";
417 cp.code() += "} // conditional\n";
418 cp.code() += "} // block\n";
419 } // block
420 } // conditional
421 cp.code() += "} // block\n";
422 } // block
423 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
424 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
425 // -----------------------------------------------------------------------------
426  cp.getAffectedRegisters().add("instructionPointer", 32);
427  }
428 
429  return true;
430  },
431  0,
432  [] (BitArray & ba, Instruction & instr)
433  {
434 // -----------------------------------------------------------------------------
435 etiss_uint8 rd = 0;
436 static BitArrayRange R_rd_0(11, 7);
437 rd += R_rd_0.read(ba) << 0;
438 etiss_uint8 rs1 = 0;
439 static BitArrayRange R_rs1_0(19, 15);
440 rs1 += R_rs1_0.read(ba) << 0;
441 etiss_uint8 rs2 = 0;
442 static BitArrayRange R_rs2_0(24, 20);
443 rs2 += R_rs2_0.read(ba) << 0;
444 
445 // -----------------------------------------------------------------------------
446 
447  std::stringstream ss;
448 // -----------------------------------------------------------------------------
449 ss << "remuw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
450 // -----------------------------------------------------------------------------
451  return ss.str();
452  }
453 );
ISA32_RV64IMACFD
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
divw_rd_rs1_rs2
static InstructionDefinition divw_rd_rs1_rs2(ISA32_RV64IMACFD, "divw",(uint32_t) 0x200403b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//DIVW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if((rd % 32ULL) !=0LL) { { cp.code()+="{ // block\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";{ cp.code()+="{ // block\n";etiss_int32 MMIN=-2147483648LL;cp.code()+="if ((etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) == "+std::to_string(MMIN)+"LL && (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) == -1LL) { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = -2147483648LL;\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) / (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])));\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = -1LL;\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "divw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
remuw_rd_rs1_rs2
static InstructionDefinition remuw_rd_rs1_rs2(ISA32_RV64IMACFD, "remuw",(uint32_t) 0x200703b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//REMUW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if((rd % 32ULL) !=0LL) { { cp.code()+="{ // block\n";cp.code()+="if ((etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) != 0LL) { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)((etiss_int32)(((etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) % (etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]))));\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL])));\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "remuw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
remw_rd_rs1_rs2
static InstructionDefinition remw_rd_rs1_rs2(ISA32_RV64IMACFD, "remw",(uint32_t) 0x200603b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//REMW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if((rd % 32ULL) !=0LL) { { cp.code()+="{ // block\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";{ cp.code()+="{ // block\n";etiss_int32 MMIN=-2147483648LL;cp.code()+="if ((etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) == "+std::to_string(MMIN)+"LL && (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) == -1LL) { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = 0LL;\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) % (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])));\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL])));\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "remw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
divuw_rd_rs1_rs2
static InstructionDefinition divuw_rd_rs1_rs2(ISA32_RV64IMACFD, "divuw",(uint32_t) 0x200503b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//DIVUW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if((rd % 32ULL) !=0LL) { { cp.code()+="{ // block\n";cp.code()+="if ((etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) != 0LL) { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)((etiss_int32)(((etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) / (etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]))));\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = -1LL;\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "divuw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
mulw_rd_rs1_rs2
static InstructionDefinition mulw_rd_rs1_rs2(ISA32_RV64IMACFD, "mulw",(uint32_t) 0x200003b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MULW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if((rd % 32ULL) !=0LL) { { cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)((etiss_int32)(((etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) * (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]))));\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "mulw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
uint32_t
static __inline__ uint32_t
Definition: arm_cde.h:25
etiss_uint8
uint8_t etiss_uint8
Definition: types.h:87
etiss_int32
int32_t etiss_int32
Definition: types.h:92
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:386
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition: Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition: Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
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