ETISS 0.11.2
ExtendableTranslatingInstructionSetSimulator(version0.11.2)
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RV64IMACFD_RV64MInstr.cpp
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1// clang-format off
9#include "RV64IMACFDArch.h"
10#include "RV64IMACFDFuncs.h"
11
12using namespace etiss;
13using namespace etiss::instr;
14
15// MULW ------------------------------------------------------------------------
16static InstructionDefinition mulw_rd_rs1_rs2 (
17 ISA32_RV64IMACFD,
18 "mulw",
19 (uint32_t) 0x200003b,
20 (uint32_t) 0xfe00707f,
21 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22 {
23
24// -----------------------------------------------------------------------------
25
26// -----------------------------------------------------------------------------
27
28// -----------------------------------------------------------------------------
29// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
30etiss_uint8 rd = 0;
31static BitArrayRange R_rd_0(11, 7);
32rd += R_rd_0.read(ba) << 0;
33etiss_uint8 rs1 = 0;
34static BitArrayRange R_rs1_0(19, 15);
35rs1 += R_rs1_0.read(ba) << 0;
36etiss_uint8 rs2 = 0;
37static BitArrayRange R_rs2_0(24, 20);
38rs2 += R_rs2_0.read(ba) << 0;
39
40// NOLINTEND(clang-diagnostic-unused-but-set-variable)
41// -----------------------------------------------------------------------------
42
43 {
44 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
45
46 cp.code() = std::string("//MULW\n");
47
48// -----------------------------------------------------------------------------
49cp.code() += "etiss_coverage_count(1, 209);\n";
50{ // block
51cp.code() += "etiss_coverage_count(1, 1169);\n";
52cp.code() += "{ // block\n";
53cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
54cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
55cp.code() += "} // block\n";
56} // block
57{ // block
58cp.code() += "etiss_coverage_count(1, 7771);\n";
59cp.code() += "{ // block\n";
60cp.code() += "etiss_coverage_count(1, 7737);\n";
61if ((rd % 32ULL) != 0LL) { // conditional
62cp.code() += "etiss_coverage_count(5, 7743, 7740, 7738, 7741, 7742);\n";
63{ // block
64cp.code() += "etiss_coverage_count(1, 7770);\n";
65cp.code() += "{ // block\n";
66cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) * (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]))));\n";
67cp.code() += "etiss_coverage_count(16, 7769, 7748, 7747, 7745, 7768, 7766, 7763, 7755, 7753, 7752, 7750, 7762, 7760, 7759, 7757, 7764);\n";
68cp.code() += "} // block\n";
69} // block
70} // conditional
71cp.code() += "} // block\n";
72} // block
73cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
74cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
75// -----------------------------------------------------------------------------
76 cp.getAffectedRegisters().add("instructionPointer", 32);
77 }
78
79 return true;
80 },
81 0,
82 [] (BitArray & ba, Instruction & instr)
83 {
84// -----------------------------------------------------------------------------
85etiss_uint8 rd = 0;
86static BitArrayRange R_rd_0(11, 7);
87rd += R_rd_0.read(ba) << 0;
88etiss_uint8 rs1 = 0;
89static BitArrayRange R_rs1_0(19, 15);
90rs1 += R_rs1_0.read(ba) << 0;
91etiss_uint8 rs2 = 0;
92static BitArrayRange R_rs2_0(24, 20);
93rs2 += R_rs2_0.read(ba) << 0;
94
95// -----------------------------------------------------------------------------
96
97 std::stringstream ss;
98// -----------------------------------------------------------------------------
99ss << "mulw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
100// -----------------------------------------------------------------------------
101 return ss.str();
102 }
103);
104
105// DIVW ------------------------------------------------------------------------
106static InstructionDefinition divw_rd_rs1_rs2 (
107 ISA32_RV64IMACFD,
108 "divw",
109 (uint32_t) 0x200403b,
110 (uint32_t) 0xfe00707f,
111 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
112 {
113
114// -----------------------------------------------------------------------------
115
116// -----------------------------------------------------------------------------
117
118// -----------------------------------------------------------------------------
119// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
120etiss_uint8 rd = 0;
121static BitArrayRange R_rd_0(11, 7);
122rd += R_rd_0.read(ba) << 0;
123etiss_uint8 rs1 = 0;
124static BitArrayRange R_rs1_0(19, 15);
125rs1 += R_rs1_0.read(ba) << 0;
126etiss_uint8 rs2 = 0;
127static BitArrayRange R_rs2_0(24, 20);
128rs2 += R_rs2_0.read(ba) << 0;
129
130// NOLINTEND(clang-diagnostic-unused-but-set-variable)
131// -----------------------------------------------------------------------------
132
133 {
134 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
135
136 cp.code() = std::string("//DIVW\n");
137
138// -----------------------------------------------------------------------------
139cp.code() += "etiss_coverage_count(1, 210);\n";
140{ // block
141cp.code() += "etiss_coverage_count(1, 1169);\n";
142cp.code() += "{ // block\n";
143cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
144cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
145cp.code() += "} // block\n";
146} // block
147{ // block
148cp.code() += "etiss_coverage_count(1, 7859);\n";
149cp.code() += "{ // block\n";
150cp.code() += "etiss_coverage_count(1, 7772);\n";
151if ((rd % 32ULL) != 0LL) { // conditional
152cp.code() += "etiss_coverage_count(5, 7778, 7775, 7773, 7776, 7777);\n";
153{ // block
154cp.code() += "etiss_coverage_count(1, 7858);\n";
155cp.code() += "{ // block\n";
156cp.code() += "etiss_coverage_count(1, 7779);\n";
157cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0LL) { // conditional\n";
158cp.code() += "etiss_coverage_count(5, 7786, 7784, 7783, 7781, 7785);\n";
159{ // block
160cp.code() += "etiss_coverage_count(1, 7849);\n";
161cp.code() += "{ // block\n";
162etiss_int32 MMIN = -2147483648LL;
163cp.code() += "etiss_coverage_count(1, 7793);\n";
164cp.code() += "etiss_coverage_count(1, 7794);\n";
165cp.code() += "if ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) == " + std::to_string(MMIN) + "LL && (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) == -1LL) { // conditional\n";
166cp.code() += "etiss_coverage_count(12, 7814, 7803, 7801, 7799, 7798, 7796, 7802, 7813, 7810, 7808, 7807, 7805);\n";
167cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -2147483648LL;\n";
168cp.code() += "etiss_coverage_count(4, 7824, 7819, 7818, 7816);\n";
169cp.code() += "} // conditional\n";
170cp.code() += "else { // conditional\n";
171cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) / (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])));\n";
172cp.code() += "etiss_coverage_count(15, 7848, 7829, 7828, 7826, 7847, 7844, 7836, 7834, 7833, 7831, 7843, 7841, 7840, 7838, 7845);\n";
173cp.code() += "} // conditional\n";
174cp.code() += "} // block\n";
175} // block
176cp.code() += "} // conditional\n";
177cp.code() += "else { // conditional\n";
178cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -1LL;\n";
179cp.code() += "etiss_coverage_count(4, 7857, 7854, 7853, 7851);\n";
180cp.code() += "} // conditional\n";
181cp.code() += "} // block\n";
182} // block
183} // conditional
184cp.code() += "} // block\n";
185} // block
186cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
187cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
188// -----------------------------------------------------------------------------
189 cp.getAffectedRegisters().add("instructionPointer", 32);
190 }
191
192 return true;
193 },
194 0,
195 [] (BitArray & ba, Instruction & instr)
196 {
197// -----------------------------------------------------------------------------
198etiss_uint8 rd = 0;
199static BitArrayRange R_rd_0(11, 7);
200rd += R_rd_0.read(ba) << 0;
201etiss_uint8 rs1 = 0;
202static BitArrayRange R_rs1_0(19, 15);
203rs1 += R_rs1_0.read(ba) << 0;
204etiss_uint8 rs2 = 0;
205static BitArrayRange R_rs2_0(24, 20);
206rs2 += R_rs2_0.read(ba) << 0;
207
208// -----------------------------------------------------------------------------
209
210 std::stringstream ss;
211// -----------------------------------------------------------------------------
212ss << "divw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
213// -----------------------------------------------------------------------------
214 return ss.str();
215 }
216);
217
218// DIVUW -----------------------------------------------------------------------
219static InstructionDefinition divuw_rd_rs1_rs2 (
220 ISA32_RV64IMACFD,
221 "divuw",
222 (uint32_t) 0x200503b,
223 (uint32_t) 0xfe00707f,
224 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
225 {
226
227// -----------------------------------------------------------------------------
228
229// -----------------------------------------------------------------------------
230
231// -----------------------------------------------------------------------------
232// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
233etiss_uint8 rd = 0;
234static BitArrayRange R_rd_0(11, 7);
235rd += R_rd_0.read(ba) << 0;
236etiss_uint8 rs1 = 0;
237static BitArrayRange R_rs1_0(19, 15);
238rs1 += R_rs1_0.read(ba) << 0;
239etiss_uint8 rs2 = 0;
240static BitArrayRange R_rs2_0(24, 20);
241rs2 += R_rs2_0.read(ba) << 0;
242
243// NOLINTEND(clang-diagnostic-unused-but-set-variable)
244// -----------------------------------------------------------------------------
245
246 {
247 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
248
249 cp.code() = std::string("//DIVUW\n");
250
251// -----------------------------------------------------------------------------
252cp.code() += "etiss_coverage_count(1, 211);\n";
253{ // block
254cp.code() += "etiss_coverage_count(1, 1169);\n";
255cp.code() += "{ // block\n";
256cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
257cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
258cp.code() += "} // block\n";
259} // block
260{ // block
261cp.code() += "etiss_coverage_count(1, 7911);\n";
262cp.code() += "{ // block\n";
263cp.code() += "etiss_coverage_count(1, 7860);\n";
264if ((rd % 32ULL) != 0LL) { // conditional
265cp.code() += "etiss_coverage_count(5, 7866, 7863, 7861, 7864, 7865);\n";
266{ // block
267cp.code() += "etiss_coverage_count(1, 7910);\n";
268cp.code() += "{ // block\n";
269cp.code() += "etiss_coverage_count(1, 7867);\n";
270cp.code() += "if ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) != 0LL) { // conditional\n";
271cp.code() += "etiss_coverage_count(6, 7876, 7874, 7872, 7871, 7869, 7875);\n";
272cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) / (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]))));\n";
273cp.code() += "etiss_coverage_count(16, 7901, 7881, 7880, 7878, 7900, 7898, 7896, 7888, 7886, 7885, 7883, 7895, 7893, 7892, 7890, 7897);\n";
274cp.code() += "} // conditional\n";
275cp.code() += "else { // conditional\n";
276cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -1LL;\n";
277cp.code() += "etiss_coverage_count(4, 7909, 7906, 7905, 7903);\n";
278cp.code() += "} // conditional\n";
279cp.code() += "} // block\n";
280} // block
281} // conditional
282cp.code() += "} // block\n";
283} // block
284cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
285cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
286// -----------------------------------------------------------------------------
287 cp.getAffectedRegisters().add("instructionPointer", 32);
288 }
289
290 return true;
291 },
292 0,
293 [] (BitArray & ba, Instruction & instr)
294 {
295// -----------------------------------------------------------------------------
296etiss_uint8 rd = 0;
297static BitArrayRange R_rd_0(11, 7);
298rd += R_rd_0.read(ba) << 0;
299etiss_uint8 rs1 = 0;
300static BitArrayRange R_rs1_0(19, 15);
301rs1 += R_rs1_0.read(ba) << 0;
302etiss_uint8 rs2 = 0;
303static BitArrayRange R_rs2_0(24, 20);
304rs2 += R_rs2_0.read(ba) << 0;
305
306// -----------------------------------------------------------------------------
307
308 std::stringstream ss;
309// -----------------------------------------------------------------------------
310ss << "divuw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
311// -----------------------------------------------------------------------------
312 return ss.str();
313 }
314);
315
316// REMW ------------------------------------------------------------------------
317static InstructionDefinition remw_rd_rs1_rs2 (
318 ISA32_RV64IMACFD,
319 "remw",
320 (uint32_t) 0x200603b,
321 (uint32_t) 0xfe00707f,
322 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
323 {
324
325// -----------------------------------------------------------------------------
326
327// -----------------------------------------------------------------------------
328
329// -----------------------------------------------------------------------------
330// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
331etiss_uint8 rd = 0;
332static BitArrayRange R_rd_0(11, 7);
333rd += R_rd_0.read(ba) << 0;
334etiss_uint8 rs1 = 0;
335static BitArrayRange R_rs1_0(19, 15);
336rs1 += R_rs1_0.read(ba) << 0;
337etiss_uint8 rs2 = 0;
338static BitArrayRange R_rs2_0(24, 20);
339rs2 += R_rs2_0.read(ba) << 0;
340
341// NOLINTEND(clang-diagnostic-unused-but-set-variable)
342// -----------------------------------------------------------------------------
343
344 {
345 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
346
347 cp.code() = std::string("//REMW\n");
348
349// -----------------------------------------------------------------------------
350cp.code() += "etiss_coverage_count(1, 212);\n";
351{ // block
352cp.code() += "etiss_coverage_count(1, 1169);\n";
353cp.code() += "{ // block\n";
354cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
355cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
356cp.code() += "} // block\n";
357} // block
358{ // block
359cp.code() += "etiss_coverage_count(1, 8004);\n";
360cp.code() += "{ // block\n";
361cp.code() += "etiss_coverage_count(1, 7912);\n";
362if ((rd % 32ULL) != 0LL) { // conditional
363cp.code() += "etiss_coverage_count(5, 7918, 7915, 7913, 7916, 7917);\n";
364{ // block
365cp.code() += "etiss_coverage_count(1, 8003);\n";
366cp.code() += "{ // block\n";
367cp.code() += "etiss_coverage_count(1, 7919);\n";
368cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0LL) { // conditional\n";
369cp.code() += "etiss_coverage_count(5, 7926, 7924, 7923, 7921, 7925);\n";
370{ // block
371cp.code() += "etiss_coverage_count(1, 7986);\n";
372cp.code() += "{ // block\n";
373etiss_int32 MMIN = -2147483648LL;
374cp.code() += "etiss_coverage_count(1, 7933);\n";
375cp.code() += "etiss_coverage_count(1, 7934);\n";
376cp.code() += "if ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) == " + std::to_string(MMIN) + "LL && (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) == -1LL) { // conditional\n";
377cp.code() += "etiss_coverage_count(12, 7954, 7943, 7941, 7939, 7938, 7936, 7942, 7953, 7950, 7948, 7947, 7945);\n";
378cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = 0LL;\n";
379cp.code() += "etiss_coverage_count(5, 7961, 7959, 7958, 7956, 7960);\n";
380cp.code() += "} // conditional\n";
381cp.code() += "else { // conditional\n";
382cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) % (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])));\n";
383cp.code() += "etiss_coverage_count(15, 7985, 7966, 7965, 7963, 7984, 7981, 7973, 7971, 7970, 7968, 7980, 7978, 7977, 7975, 7982);\n";
384cp.code() += "} // conditional\n";
385cp.code() += "} // block\n";
386} // block
387cp.code() += "} // conditional\n";
388cp.code() += "else { // conditional\n";
389cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])));\n";
390cp.code() += "etiss_coverage_count(10, 8002, 7991, 7990, 7988, 8001, 7998, 7996, 7995, 7993, 7999);\n";
391cp.code() += "} // conditional\n";
392cp.code() += "} // block\n";
393} // block
394} // conditional
395cp.code() += "} // block\n";
396} // block
397cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
398cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
399// -----------------------------------------------------------------------------
400 cp.getAffectedRegisters().add("instructionPointer", 32);
401 }
402
403 return true;
404 },
405 0,
406 [] (BitArray & ba, Instruction & instr)
407 {
408// -----------------------------------------------------------------------------
409etiss_uint8 rd = 0;
410static BitArrayRange R_rd_0(11, 7);
411rd += R_rd_0.read(ba) << 0;
412etiss_uint8 rs1 = 0;
413static BitArrayRange R_rs1_0(19, 15);
414rs1 += R_rs1_0.read(ba) << 0;
415etiss_uint8 rs2 = 0;
416static BitArrayRange R_rs2_0(24, 20);
417rs2 += R_rs2_0.read(ba) << 0;
418
419// -----------------------------------------------------------------------------
420
421 std::stringstream ss;
422// -----------------------------------------------------------------------------
423ss << "remw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
424// -----------------------------------------------------------------------------
425 return ss.str();
426 }
427);
428
429// REMUW -----------------------------------------------------------------------
430static InstructionDefinition remuw_rd_rs1_rs2 (
431 ISA32_RV64IMACFD,
432 "remuw",
433 (uint32_t) 0x200703b,
434 (uint32_t) 0xfe00707f,
435 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
436 {
437
438// -----------------------------------------------------------------------------
439
440// -----------------------------------------------------------------------------
441
442// -----------------------------------------------------------------------------
443// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
444etiss_uint8 rd = 0;
445static BitArrayRange R_rd_0(11, 7);
446rd += R_rd_0.read(ba) << 0;
447etiss_uint8 rs1 = 0;
448static BitArrayRange R_rs1_0(19, 15);
449rs1 += R_rs1_0.read(ba) << 0;
450etiss_uint8 rs2 = 0;
451static BitArrayRange R_rs2_0(24, 20);
452rs2 += R_rs2_0.read(ba) << 0;
453
454// NOLINTEND(clang-diagnostic-unused-but-set-variable)
455// -----------------------------------------------------------------------------
456
457 {
458 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
459
460 cp.code() = std::string("//REMUW\n");
461
462// -----------------------------------------------------------------------------
463cp.code() += "etiss_coverage_count(1, 213);\n";
464{ // block
465cp.code() += "etiss_coverage_count(1, 1169);\n";
466cp.code() += "{ // block\n";
467cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
468cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
469cp.code() += "} // block\n";
470} // block
471{ // block
472cp.code() += "etiss_coverage_count(1, 8064);\n";
473cp.code() += "{ // block\n";
474cp.code() += "etiss_coverage_count(1, 8005);\n";
475if ((rd % 32ULL) != 0LL) { // conditional
476cp.code() += "etiss_coverage_count(5, 8011, 8008, 8006, 8009, 8010);\n";
477{ // block
478cp.code() += "etiss_coverage_count(1, 8063);\n";
479cp.code() += "{ // block\n";
480cp.code() += "etiss_coverage_count(1, 8012);\n";
481cp.code() += "if ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) != 0LL) { // conditional\n";
482cp.code() += "etiss_coverage_count(6, 8021, 8019, 8017, 8016, 8014, 8020);\n";
483cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) % (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]))));\n";
484cp.code() += "etiss_coverage_count(16, 8046, 8026, 8025, 8023, 8045, 8043, 8041, 8033, 8031, 8030, 8028, 8040, 8038, 8037, 8035, 8042);\n";
485cp.code() += "} // conditional\n";
486cp.code() += "else { // conditional\n";
487cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])));\n";
488cp.code() += "etiss_coverage_count(10, 8062, 8051, 8050, 8048, 8061, 8058, 8056, 8055, 8053, 8059);\n";
489cp.code() += "} // conditional\n";
490cp.code() += "} // block\n";
491} // block
492} // conditional
493cp.code() += "} // block\n";
494} // block
495cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
496cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
497// -----------------------------------------------------------------------------
498 cp.getAffectedRegisters().add("instructionPointer", 32);
499 }
500
501 return true;
502 },
503 0,
504 [] (BitArray & ba, Instruction & instr)
505 {
506// -----------------------------------------------------------------------------
507etiss_uint8 rd = 0;
508static BitArrayRange R_rd_0(11, 7);
509rd += R_rd_0.read(ba) << 0;
510etiss_uint8 rs1 = 0;
511static BitArrayRange R_rs1_0(19, 15);
512rs1 += R_rs1_0.read(ba) << 0;
513etiss_uint8 rs2 = 0;
514static BitArrayRange R_rs2_0(24, 20);
515rs2 += R_rs2_0.read(ba) << 0;
516
517// -----------------------------------------------------------------------------
518
519 std::stringstream ss;
520// -----------------------------------------------------------------------------
521ss << "remuw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
522// -----------------------------------------------------------------------------
523 return ss.str();
524 }
525);
526// clang-format on
ISA32_RV64IMACFD
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
mulw_rd_rs1_rs2
static InstructionDefinition mulw_rd_rs1_rs2(ISA32_RV64IMACFD, "mulw",(uint32_t) 0x200003b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MULW\n");cp.code()+="etiss_coverage_count(1, 209);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7771);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 7737);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 7743, 7740, 7738, 7741, 7742);\n";{ cp.code()+="etiss_coverage_count(1, 7770);\n";cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)((etiss_int32)(((etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) * (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]))));\n";cp.code()+="etiss_coverage_count(16, 7769, 7748, 7747, 7745, 7768, 7766, 7763, 7755, 7753, 7752, 7750, 7762, 7760, 7759, 7757, 7764);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "mulw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
divw_rd_rs1_rs2
static InstructionDefinition divw_rd_rs1_rs2(ISA32_RV64IMACFD, "divw",(uint32_t) 0x200403b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//DIVW\n");cp.code()+="etiss_coverage_count(1, 210);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7859);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 7772);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 7778, 7775, 7773, 7776, 7777);\n";{ cp.code()+="etiss_coverage_count(1, 7858);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 7779);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 7786, 7784, 7783, 7781, 7785);\n";{ cp.code()+="etiss_coverage_count(1, 7849);\n";cp.code()+="{ // block\n";etiss_int32 MMIN=-2147483648LL;cp.code()+="etiss_coverage_count(1, 7793);\n";cp.code()+="etiss_coverage_count(1, 7794);\n";cp.code()+="if ((etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) == "+std::to_string(MMIN)+"LL && (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) == -1LL) { // conditional\n";cp.code()+="etiss_coverage_count(12, 7814, 7803, 7801, 7799, 7798, 7796, 7802, 7813, 7810, 7808, 7807, 7805);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = -2147483648LL;\n";cp.code()+="etiss_coverage_count(4, 7824, 7819, 7818, 7816);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) / (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])));\n";cp.code()+="etiss_coverage_count(15, 7848, 7829, 7828, 7826, 7847, 7844, 7836, 7834, 7833, 7831, 7843, 7841, 7840, 7838, 7845);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = -1LL;\n";cp.code()+="etiss_coverage_count(4, 7857, 7854, 7853, 7851);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "divw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
divuw_rd_rs1_rs2
static InstructionDefinition divuw_rd_rs1_rs2(ISA32_RV64IMACFD, "divuw",(uint32_t) 0x200503b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//DIVUW\n");cp.code()+="etiss_coverage_count(1, 211);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7911);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 7860);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 7866, 7863, 7861, 7864, 7865);\n";{ cp.code()+="etiss_coverage_count(1, 7910);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 7867);\n";cp.code()+="if ((etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(6, 7876, 7874, 7872, 7871, 7869, 7875);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)((etiss_int32)(((etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) / (etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]))));\n";cp.code()+="etiss_coverage_count(16, 7901, 7881, 7880, 7878, 7900, 7898, 7896, 7888, 7886, 7885, 7883, 7895, 7893, 7892, 7890, 7897);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = -1LL;\n";cp.code()+="etiss_coverage_count(4, 7909, 7906, 7905, 7903);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "divuw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
remuw_rd_rs1_rs2
static InstructionDefinition remuw_rd_rs1_rs2(ISA32_RV64IMACFD, "remuw",(uint32_t) 0x200703b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//REMUW\n");cp.code()+="etiss_coverage_count(1, 213);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8064);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 8005);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8011, 8008, 8006, 8009, 8010);\n";{ cp.code()+="etiss_coverage_count(1, 8063);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 8012);\n";cp.code()+="if ((etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(6, 8021, 8019, 8017, 8016, 8014, 8020);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)((etiss_int32)(((etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) % (etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]))));\n";cp.code()+="etiss_coverage_count(16, 8046, 8026, 8025, 8023, 8045, 8043, 8041, 8033, 8031, 8030, 8028, 8040, 8038, 8037, 8035, 8042);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL])));\n";cp.code()+="etiss_coverage_count(10, 8062, 8051, 8050, 8048, 8061, 8058, 8056, 8055, 8053, 8059);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "remuw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
remw_rd_rs1_rs2
static InstructionDefinition remw_rd_rs1_rs2(ISA32_RV64IMACFD, "remw",(uint32_t) 0x200603b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//REMW\n");cp.code()+="etiss_coverage_count(1, 212);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8004);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 7912);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 7918, 7915, 7913, 7916, 7917);\n";{ cp.code()+="etiss_coverage_count(1, 8003);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 7919);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 7926, 7924, 7923, 7921, 7925);\n";{ cp.code()+="etiss_coverage_count(1, 7986);\n";cp.code()+="{ // block\n";etiss_int32 MMIN=-2147483648LL;cp.code()+="etiss_coverage_count(1, 7933);\n";cp.code()+="etiss_coverage_count(1, 7934);\n";cp.code()+="if ((etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) == "+std::to_string(MMIN)+"LL && (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) == -1LL) { // conditional\n";cp.code()+="etiss_coverage_count(12, 7954, 7943, 7941, 7939, 7938, 7936, 7942, 7953, 7950, 7948, 7947, 7945);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = 0LL;\n";cp.code()+="etiss_coverage_count(5, 7961, 7959, 7958, 7956, 7960);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) % (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])));\n";cp.code()+="etiss_coverage_count(15, 7985, 7966, 7965, 7963, 7984, 7981, 7973, 7971, 7970, 7968, 7980, 7978, 7977, 7975, 7982);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(((etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL])));\n";cp.code()+="etiss_coverage_count(10, 8002, 7991, 7990, 7988, 8001, 7998, 7996, 7995, 7993, 7999);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "remw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
etiss_uint8
uint8_t etiss_uint8
Definition types.h:49
etiss_int32
int32_t etiss_int32
Definition types.h:54
etiss::CodePart
Contains a small code snipped.
Definition CodePart.h:348
etiss::CodePart::code
std::string & code()
Definition CodePart.h:378
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition CodePart.h:376
etiss::CodeSet
A set of CodeParts.
Definition CodePart.h:399
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition CodePart.h:412
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition CodePart.h:184
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition Instruction.h:162
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition Instruction.cpp:171
etiss::instr::BitArray
stores a bit vector
Definition Instruction.h:114
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition Instruction.h:290
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition Instruction.h:319
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition Instruction.h:346
etiss
forwards: include/jit/*
Definition Benchmark.h:17
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