ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV64IMACFD_RV64IInstr.cpp
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1 
8 #include "RV64IMACFDArch.h"
9 #include "RV64IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // LWU -------------------------------------------------------------------------
16 static InstructionDefinition lwu_rd_rs1_imm (
17  ISA32_RV64IMACFD,
18  "lwu",
19  (uint32_t) 0x006003,
20  (uint32_t) 0x00707f,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 etiss_uint8 rd = 0;
30 static BitArrayRange R_rd_0(11, 7);
31 rd += R_rd_0.read(ba) << 0;
32 etiss_uint8 rs1 = 0;
33 static BitArrayRange R_rs1_0(19, 15);
34 rs1 += R_rs1_0.read(ba) << 0;
35 etiss_uint16 imm = 0;
36 static BitArrayRange R_imm_0(31, 20);
37 imm += R_imm_0.read(ba) << 0;
38 
39 // -----------------------------------------------------------------------------
40 
41  {
42  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
43 
44  cp.code() = std::string("//LWU\n");
45 
46 // -----------------------------------------------------------------------------
47 { // block
48 cp.code() += "{ // block\n";
49 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
50 cp.code() += "} // block\n";
51 } // block
52 { // block
53 cp.code() += "{ // block\n";
54 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
55 cp.code() += "etiss_uint32 mem_val_0;\n";
56 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
57 cp.code() += "if (cpu->exception) { // conditional\n";
58 { // procedure
59 cp.code() += "{ // procedure\n";
60 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
61 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
62 cp.code() += "} // procedure\n";
63 } // procedure
64 cp.code() += "} // conditional\n";
65 cp.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
66 if ((rd % 32ULL) != 0LL) { // conditional
67 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
68 } // conditional
69 cp.code() += "} // block\n";
70 } // block
71 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
72 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
73 // -----------------------------------------------------------------------------
74  cp.getAffectedRegisters().add("instructionPointer", 32);
75  }
76  {
77  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
78 
79  cp.code() = std::string("//LWU\n");
80 
81 // -----------------------------------------------------------------------------
82 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
83 // -----------------------------------------------------------------------------
84  }
85 
86  return true;
87  },
88  0,
89  [] (BitArray & ba, Instruction & instr)
90  {
91 // -----------------------------------------------------------------------------
92 etiss_uint8 rd = 0;
93 static BitArrayRange R_rd_0(11, 7);
94 rd += R_rd_0.read(ba) << 0;
95 etiss_uint8 rs1 = 0;
96 static BitArrayRange R_rs1_0(19, 15);
97 rs1 += R_rs1_0.read(ba) << 0;
98 etiss_uint16 imm = 0;
99 static BitArrayRange R_imm_0(31, 20);
100 imm += R_imm_0.read(ba) << 0;
101 
102 // -----------------------------------------------------------------------------
103 
104  std::stringstream ss;
105 // -----------------------------------------------------------------------------
106 ss << "lwu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
107 // -----------------------------------------------------------------------------
108  return ss.str();
109  }
110 );
111 
112 // LD --------------------------------------------------------------------------
113 static InstructionDefinition ld_rd_rs1_imm (
114  ISA32_RV64IMACFD,
115  "ld",
116  (uint32_t) 0x003003,
117  (uint32_t) 0x00707f,
118  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
119  {
120 
121 // -----------------------------------------------------------------------------
122 
123 // -----------------------------------------------------------------------------
124 
125 // -----------------------------------------------------------------------------
126 etiss_uint8 rd = 0;
127 static BitArrayRange R_rd_0(11, 7);
128 rd += R_rd_0.read(ba) << 0;
129 etiss_uint8 rs1 = 0;
130 static BitArrayRange R_rs1_0(19, 15);
131 rs1 += R_rs1_0.read(ba) << 0;
132 etiss_uint16 imm = 0;
133 static BitArrayRange R_imm_0(31, 20);
134 imm += R_imm_0.read(ba) << 0;
135 
136 // -----------------------------------------------------------------------------
137 
138  {
139  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
140 
141  cp.code() = std::string("//LD\n");
142 
143 // -----------------------------------------------------------------------------
144 { // block
145 cp.code() += "{ // block\n";
146 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
147 cp.code() += "} // block\n";
148 } // block
149 { // block
150 cp.code() += "{ // block\n";
151 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
152 cp.code() += "etiss_uint64 mem_val_0;\n";
153 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
154 cp.code() += "if (cpu->exception) { // conditional\n";
155 { // procedure
156 cp.code() += "{ // procedure\n";
157 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
158 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
159 cp.code() += "} // procedure\n";
160 } // procedure
161 cp.code() += "} // conditional\n";
162 cp.code() += "etiss_int64 res = (etiss_int64)(mem_val_0);\n";
163 if ((rd % 32ULL) != 0LL) { // conditional
164 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
165 } // conditional
166 cp.code() += "} // block\n";
167 } // block
168 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
169 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
170 // -----------------------------------------------------------------------------
171  cp.getAffectedRegisters().add("instructionPointer", 32);
172  }
173  {
174  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
175 
176  cp.code() = std::string("//LD\n");
177 
178 // -----------------------------------------------------------------------------
179 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
180 // -----------------------------------------------------------------------------
181  }
182 
183  return true;
184  },
185  0,
186  [] (BitArray & ba, Instruction & instr)
187  {
188 // -----------------------------------------------------------------------------
189 etiss_uint8 rd = 0;
190 static BitArrayRange R_rd_0(11, 7);
191 rd += R_rd_0.read(ba) << 0;
192 etiss_uint8 rs1 = 0;
193 static BitArrayRange R_rs1_0(19, 15);
194 rs1 += R_rs1_0.read(ba) << 0;
195 etiss_uint16 imm = 0;
196 static BitArrayRange R_imm_0(31, 20);
197 imm += R_imm_0.read(ba) << 0;
198 
199 // -----------------------------------------------------------------------------
200 
201  std::stringstream ss;
202 // -----------------------------------------------------------------------------
203 ss << "ld" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
204 // -----------------------------------------------------------------------------
205  return ss.str();
206  }
207 );
208 
209 // SD --------------------------------------------------------------------------
210 static InstructionDefinition sd_imm_rs1_rs2 (
211  ISA32_RV64IMACFD,
212  "sd",
213  (uint32_t) 0x003023,
214  (uint32_t) 0x00707f,
215  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
216  {
217 
218 // -----------------------------------------------------------------------------
219 
220 // -----------------------------------------------------------------------------
221 
222 // -----------------------------------------------------------------------------
223 etiss_uint16 imm = 0;
224 static BitArrayRange R_imm_0(11, 7);
225 imm += R_imm_0.read(ba) << 0;
226 etiss_uint8 rs1 = 0;
227 static BitArrayRange R_rs1_0(19, 15);
228 rs1 += R_rs1_0.read(ba) << 0;
229 etiss_uint8 rs2 = 0;
230 static BitArrayRange R_rs2_0(24, 20);
231 rs2 += R_rs2_0.read(ba) << 0;
232 static BitArrayRange R_imm_5(31, 25);
233 imm += R_imm_5.read(ba) << 5;
234 
235 // -----------------------------------------------------------------------------
236 
237  {
238  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
239 
240  cp.code() = std::string("//SD\n");
241 
242 // -----------------------------------------------------------------------------
243 { // block
244 cp.code() += "{ // block\n";
245 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
246 cp.code() += "} // block\n";
247 } // block
248 { // block
249 cp.code() += "{ // block\n";
250 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
251 cp.code() += "etiss_uint64 mem_val_0;\n";
252 cp.code() += "mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
253 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
254 cp.code() += "if (cpu->exception) { // conditional\n";
255 { // procedure
256 cp.code() += "{ // procedure\n";
257 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
258 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
259 cp.code() += "} // procedure\n";
260 } // procedure
261 cp.code() += "} // conditional\n";
262 cp.code() += "} // block\n";
263 } // block
264 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
265 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
266 // -----------------------------------------------------------------------------
267  cp.getAffectedRegisters().add("instructionPointer", 32);
268  }
269  {
270  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
271 
272  cp.code() = std::string("//SD\n");
273 
274 // -----------------------------------------------------------------------------
275 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
276 // -----------------------------------------------------------------------------
277  }
278 
279  return true;
280  },
281  0,
282  [] (BitArray & ba, Instruction & instr)
283  {
284 // -----------------------------------------------------------------------------
285 etiss_uint16 imm = 0;
286 static BitArrayRange R_imm_0(11, 7);
287 imm += R_imm_0.read(ba) << 0;
288 etiss_uint8 rs1 = 0;
289 static BitArrayRange R_rs1_0(19, 15);
290 rs1 += R_rs1_0.read(ba) << 0;
291 etiss_uint8 rs2 = 0;
292 static BitArrayRange R_rs2_0(24, 20);
293 rs2 += R_rs2_0.read(ba) << 0;
294 static BitArrayRange R_imm_5(31, 25);
295 imm += R_imm_5.read(ba) << 5;
296 
297 // -----------------------------------------------------------------------------
298 
299  std::stringstream ss;
300 // -----------------------------------------------------------------------------
301 ss << "sd" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
302 // -----------------------------------------------------------------------------
303  return ss.str();
304  }
305 );
306 
307 // SLLI ------------------------------------------------------------------------
308 static InstructionDefinition slli_rd_rs1_shamt (
309  ISA32_RV64IMACFD,
310  "slli",
311  (uint32_t) 0x001013,
312  (uint32_t) 0xfc00707f,
313  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
314  {
315 
316 // -----------------------------------------------------------------------------
317 
318 // -----------------------------------------------------------------------------
319 
320 // -----------------------------------------------------------------------------
321 etiss_uint8 rd = 0;
322 static BitArrayRange R_rd_0(11, 7);
323 rd += R_rd_0.read(ba) << 0;
324 etiss_uint8 rs1 = 0;
325 static BitArrayRange R_rs1_0(19, 15);
326 rs1 += R_rs1_0.read(ba) << 0;
327 etiss_uint8 shamt = 0;
328 static BitArrayRange R_shamt_0(25, 20);
329 shamt += R_shamt_0.read(ba) << 0;
330 
331 // -----------------------------------------------------------------------------
332 
333  {
334  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
335 
336  cp.code() = std::string("//SLLI\n");
337 
338 // -----------------------------------------------------------------------------
339 { // block
340 cp.code() += "{ // block\n";
341 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
342 cp.code() += "} // block\n";
343 } // block
344 if ((rd % 32ULL) != 0LL) { // conditional
345 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << " + std::to_string(shamt) + "ULL;\n";
346 } // conditional
347 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
348 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
349 // -----------------------------------------------------------------------------
350  cp.getAffectedRegisters().add("instructionPointer", 32);
351  }
352 
353  return true;
354  },
355  0,
356  [] (BitArray & ba, Instruction & instr)
357  {
358 // -----------------------------------------------------------------------------
359 etiss_uint8 rd = 0;
360 static BitArrayRange R_rd_0(11, 7);
361 rd += R_rd_0.read(ba) << 0;
362 etiss_uint8 rs1 = 0;
363 static BitArrayRange R_rs1_0(19, 15);
364 rs1 += R_rs1_0.read(ba) << 0;
365 etiss_uint8 shamt = 0;
366 static BitArrayRange R_shamt_0(25, 20);
367 shamt += R_shamt_0.read(ba) << 0;
368 
369 // -----------------------------------------------------------------------------
370 
371  std::stringstream ss;
372 // -----------------------------------------------------------------------------
373 ss << "slli" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
374 // -----------------------------------------------------------------------------
375  return ss.str();
376  }
377 );
378 
379 // SRLI ------------------------------------------------------------------------
380 static InstructionDefinition srli_rd_rs1_shamt (
381  ISA32_RV64IMACFD,
382  "srli",
383  (uint32_t) 0x005013,
384  (uint32_t) 0xfc00707f,
385  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
386  {
387 
388 // -----------------------------------------------------------------------------
389 
390 // -----------------------------------------------------------------------------
391 
392 // -----------------------------------------------------------------------------
393 etiss_uint8 rd = 0;
394 static BitArrayRange R_rd_0(11, 7);
395 rd += R_rd_0.read(ba) << 0;
396 etiss_uint8 rs1 = 0;
397 static BitArrayRange R_rs1_0(19, 15);
398 rs1 += R_rs1_0.read(ba) << 0;
399 etiss_uint8 shamt = 0;
400 static BitArrayRange R_shamt_0(25, 20);
401 shamt += R_shamt_0.read(ba) << 0;
402 
403 // -----------------------------------------------------------------------------
404 
405  {
406  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
407 
408  cp.code() = std::string("//SRLI\n");
409 
410 // -----------------------------------------------------------------------------
411 { // block
412 cp.code() += "{ // block\n";
413 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
414 cp.code() += "} // block\n";
415 } // block
416 if ((rd % 32ULL) != 0LL) { // conditional
417 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >> " + std::to_string(shamt) + "ULL;\n";
418 } // conditional
419 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
420 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
421 // -----------------------------------------------------------------------------
422  cp.getAffectedRegisters().add("instructionPointer", 32);
423  }
424 
425  return true;
426  },
427  0,
428  [] (BitArray & ba, Instruction & instr)
429  {
430 // -----------------------------------------------------------------------------
431 etiss_uint8 rd = 0;
432 static BitArrayRange R_rd_0(11, 7);
433 rd += R_rd_0.read(ba) << 0;
434 etiss_uint8 rs1 = 0;
435 static BitArrayRange R_rs1_0(19, 15);
436 rs1 += R_rs1_0.read(ba) << 0;
437 etiss_uint8 shamt = 0;
438 static BitArrayRange R_shamt_0(25, 20);
439 shamt += R_shamt_0.read(ba) << 0;
440 
441 // -----------------------------------------------------------------------------
442 
443  std::stringstream ss;
444 // -----------------------------------------------------------------------------
445 ss << "srli" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
446 // -----------------------------------------------------------------------------
447  return ss.str();
448  }
449 );
450 
451 // SRAI ------------------------------------------------------------------------
452 static InstructionDefinition srai_rd_rs1_shamt (
453  ISA32_RV64IMACFD,
454  "srai",
455  (uint32_t) 0x40005013,
456  (uint32_t) 0xfc00707f,
457  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
458  {
459 
460 // -----------------------------------------------------------------------------
461 
462 // -----------------------------------------------------------------------------
463 
464 // -----------------------------------------------------------------------------
465 etiss_uint8 rd = 0;
466 static BitArrayRange R_rd_0(11, 7);
467 rd += R_rd_0.read(ba) << 0;
468 etiss_uint8 rs1 = 0;
469 static BitArrayRange R_rs1_0(19, 15);
470 rs1 += R_rs1_0.read(ba) << 0;
471 etiss_uint8 shamt = 0;
472 static BitArrayRange R_shamt_0(25, 20);
473 shamt += R_shamt_0.read(ba) << 0;
474 
475 // -----------------------------------------------------------------------------
476 
477  {
478  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
479 
480  cp.code() = std::string("//SRAI\n");
481 
482 // -----------------------------------------------------------------------------
483 { // block
484 cp.code() += "{ // block\n";
485 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
486 cp.code() += "} // block\n";
487 } // block
488 if ((rd % 32ULL) != 0LL) { // conditional
489 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) >> " + std::to_string(shamt) + "ULL;\n";
490 } // conditional
491 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
492 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
493 // -----------------------------------------------------------------------------
494  cp.getAffectedRegisters().add("instructionPointer", 32);
495  }
496 
497  return true;
498  },
499  0,
500  [] (BitArray & ba, Instruction & instr)
501  {
502 // -----------------------------------------------------------------------------
503 etiss_uint8 rd = 0;
504 static BitArrayRange R_rd_0(11, 7);
505 rd += R_rd_0.read(ba) << 0;
506 etiss_uint8 rs1 = 0;
507 static BitArrayRange R_rs1_0(19, 15);
508 rs1 += R_rs1_0.read(ba) << 0;
509 etiss_uint8 shamt = 0;
510 static BitArrayRange R_shamt_0(25, 20);
511 shamt += R_shamt_0.read(ba) << 0;
512 
513 // -----------------------------------------------------------------------------
514 
515  std::stringstream ss;
516 // -----------------------------------------------------------------------------
517 ss << "srai" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
518 // -----------------------------------------------------------------------------
519  return ss.str();
520  }
521 );
522 
523 // ADDIW -----------------------------------------------------------------------
524 static InstructionDefinition addiw_rd_rs1_imm (
525  ISA32_RV64IMACFD,
526  "addiw",
527  (uint32_t) 0x00001b,
528  (uint32_t) 0x00707f,
529  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
530  {
531 
532 // -----------------------------------------------------------------------------
533 
534 // -----------------------------------------------------------------------------
535 
536 // -----------------------------------------------------------------------------
537 etiss_uint8 rd = 0;
538 static BitArrayRange R_rd_0(11, 7);
539 rd += R_rd_0.read(ba) << 0;
540 etiss_uint8 rs1 = 0;
541 static BitArrayRange R_rs1_0(19, 15);
542 rs1 += R_rs1_0.read(ba) << 0;
543 etiss_uint16 imm = 0;
544 static BitArrayRange R_imm_0(31, 20);
545 imm += R_imm_0.read(ba) << 0;
546 
547 // -----------------------------------------------------------------------------
548 
549  {
550  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
551 
552  cp.code() = std::string("//ADDIW\n");
553 
554 // -----------------------------------------------------------------------------
555 { // block
556 cp.code() += "{ // block\n";
557 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
558 cp.code() += "} // block\n";
559 } // block
560 { // block
561 cp.code() += "{ // block\n";
562 if ((rd % 32ULL) != 0LL) { // conditional
563 { // block
564 cp.code() += "{ // block\n";
565 cp.code() += "etiss_int32 res = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
566 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res);\n";
567 cp.code() += "} // block\n";
568 } // block
569 } // conditional
570 cp.code() += "} // block\n";
571 } // block
572 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
573 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
574 // -----------------------------------------------------------------------------
575  cp.getAffectedRegisters().add("instructionPointer", 32);
576  }
577 
578  return true;
579  },
580  0,
581  [] (BitArray & ba, Instruction & instr)
582  {
583 // -----------------------------------------------------------------------------
584 etiss_uint8 rd = 0;
585 static BitArrayRange R_rd_0(11, 7);
586 rd += R_rd_0.read(ba) << 0;
587 etiss_uint8 rs1 = 0;
588 static BitArrayRange R_rs1_0(19, 15);
589 rs1 += R_rs1_0.read(ba) << 0;
590 etiss_uint16 imm = 0;
591 static BitArrayRange R_imm_0(31, 20);
592 imm += R_imm_0.read(ba) << 0;
593 
594 // -----------------------------------------------------------------------------
595 
596  std::stringstream ss;
597 // -----------------------------------------------------------------------------
598 ss << "addiw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
599 // -----------------------------------------------------------------------------
600  return ss.str();
601  }
602 );
603 
604 // SLLIW -----------------------------------------------------------------------
605 static InstructionDefinition slliw_rd_rs1_shamt (
606  ISA32_RV64IMACFD,
607  "slliw",
608  (uint32_t) 0x00101b,
609  (uint32_t) 0xfe00707f,
610  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
611  {
612 
613 // -----------------------------------------------------------------------------
614 
615 // -----------------------------------------------------------------------------
616 
617 // -----------------------------------------------------------------------------
618 etiss_uint8 rd = 0;
619 static BitArrayRange R_rd_0(11, 7);
620 rd += R_rd_0.read(ba) << 0;
621 etiss_uint8 rs1 = 0;
622 static BitArrayRange R_rs1_0(19, 15);
623 rs1 += R_rs1_0.read(ba) << 0;
624 etiss_uint8 shamt = 0;
625 static BitArrayRange R_shamt_0(24, 20);
626 shamt += R_shamt_0.read(ba) << 0;
627 
628 // -----------------------------------------------------------------------------
629 
630  {
631  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
632 
633  cp.code() = std::string("//SLLIW\n");
634 
635 // -----------------------------------------------------------------------------
636 { // block
637 cp.code() += "{ // block\n";
638 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
639 cp.code() += "} // block\n";
640 } // block
641 { // block
642 cp.code() += "{ // block\n";
643 if ((rd % 32ULL) != 0LL) { // conditional
644 { // block
645 cp.code() += "{ // block\n";
646 cp.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) << " + std::to_string(shamt) + "ULL;\n";
647 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(sh_val));\n";
648 cp.code() += "} // block\n";
649 } // block
650 } // conditional
651 cp.code() += "} // block\n";
652 } // block
653 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
654 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
655 // -----------------------------------------------------------------------------
656  cp.getAffectedRegisters().add("instructionPointer", 32);
657  }
658 
659  return true;
660  },
661  0,
662  [] (BitArray & ba, Instruction & instr)
663  {
664 // -----------------------------------------------------------------------------
665 etiss_uint8 rd = 0;
666 static BitArrayRange R_rd_0(11, 7);
667 rd += R_rd_0.read(ba) << 0;
668 etiss_uint8 rs1 = 0;
669 static BitArrayRange R_rs1_0(19, 15);
670 rs1 += R_rs1_0.read(ba) << 0;
671 etiss_uint8 shamt = 0;
672 static BitArrayRange R_shamt_0(24, 20);
673 shamt += R_shamt_0.read(ba) << 0;
674 
675 // -----------------------------------------------------------------------------
676 
677  std::stringstream ss;
678 // -----------------------------------------------------------------------------
679 ss << "slliw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
680 // -----------------------------------------------------------------------------
681  return ss.str();
682  }
683 );
684 
685 // SRLIW -----------------------------------------------------------------------
686 static InstructionDefinition srliw_rd_rs1_shamt (
687  ISA32_RV64IMACFD,
688  "srliw",
689  (uint32_t) 0x00501b,
690  (uint32_t) 0xfe00707f,
691  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
692  {
693 
694 // -----------------------------------------------------------------------------
695 
696 // -----------------------------------------------------------------------------
697 
698 // -----------------------------------------------------------------------------
699 etiss_uint8 rd = 0;
700 static BitArrayRange R_rd_0(11, 7);
701 rd += R_rd_0.read(ba) << 0;
702 etiss_uint8 rs1 = 0;
703 static BitArrayRange R_rs1_0(19, 15);
704 rs1 += R_rs1_0.read(ba) << 0;
705 etiss_uint8 shamt = 0;
706 static BitArrayRange R_shamt_0(24, 20);
707 shamt += R_shamt_0.read(ba) << 0;
708 
709 // -----------------------------------------------------------------------------
710 
711  {
712  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
713 
714  cp.code() = std::string("//SRLIW\n");
715 
716 // -----------------------------------------------------------------------------
717 { // block
718 cp.code() += "{ // block\n";
719 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
720 cp.code() += "} // block\n";
721 } // block
722 { // block
723 cp.code() += "{ // block\n";
724 if ((rd % 32ULL) != 0LL) { // conditional
725 { // block
726 cp.code() += "{ // block\n";
727 cp.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) >> " + std::to_string(shamt) + "ULL;\n";
728 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(sh_val));\n";
729 cp.code() += "} // block\n";
730 } // block
731 } // conditional
732 cp.code() += "} // block\n";
733 } // block
734 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
735 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
736 // -----------------------------------------------------------------------------
737  cp.getAffectedRegisters().add("instructionPointer", 32);
738  }
739 
740  return true;
741  },
742  0,
743  [] (BitArray & ba, Instruction & instr)
744  {
745 // -----------------------------------------------------------------------------
746 etiss_uint8 rd = 0;
747 static BitArrayRange R_rd_0(11, 7);
748 rd += R_rd_0.read(ba) << 0;
749 etiss_uint8 rs1 = 0;
750 static BitArrayRange R_rs1_0(19, 15);
751 rs1 += R_rs1_0.read(ba) << 0;
752 etiss_uint8 shamt = 0;
753 static BitArrayRange R_shamt_0(24, 20);
754 shamt += R_shamt_0.read(ba) << 0;
755 
756 // -----------------------------------------------------------------------------
757 
758  std::stringstream ss;
759 // -----------------------------------------------------------------------------
760 ss << "srliw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
761 // -----------------------------------------------------------------------------
762  return ss.str();
763  }
764 );
765 
766 // SRAIW -----------------------------------------------------------------------
767 static InstructionDefinition sraiw_rd_rs1_shamt (
768  ISA32_RV64IMACFD,
769  "sraiw",
770  (uint32_t) 0x4000501b,
771  (uint32_t) 0xfe00707f,
772  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
773  {
774 
775 // -----------------------------------------------------------------------------
776 
777 // -----------------------------------------------------------------------------
778 
779 // -----------------------------------------------------------------------------
780 etiss_uint8 rd = 0;
781 static BitArrayRange R_rd_0(11, 7);
782 rd += R_rd_0.read(ba) << 0;
783 etiss_uint8 rs1 = 0;
784 static BitArrayRange R_rs1_0(19, 15);
785 rs1 += R_rs1_0.read(ba) << 0;
786 etiss_uint8 shamt = 0;
787 static BitArrayRange R_shamt_0(24, 20);
788 shamt += R_shamt_0.read(ba) << 0;
789 
790 // -----------------------------------------------------------------------------
791 
792  {
793  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
794 
795  cp.code() = std::string("//SRAIW\n");
796 
797 // -----------------------------------------------------------------------------
798 { // block
799 cp.code() += "{ // block\n";
800 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
801 cp.code() += "} // block\n";
802 } // block
803 { // block
804 cp.code() += "{ // block\n";
805 if ((rd % 32ULL) != 0LL) { // conditional
806 { // block
807 cp.code() += "{ // block\n";
808 cp.code() += "etiss_int32 sh_val = ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) >> " + std::to_string(shamt) + "ULL;\n";
809 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(sh_val);\n";
810 cp.code() += "} // block\n";
811 } // block
812 } // conditional
813 cp.code() += "} // block\n";
814 } // block
815 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
816 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
817 // -----------------------------------------------------------------------------
818  cp.getAffectedRegisters().add("instructionPointer", 32);
819  }
820 
821  return true;
822  },
823  0,
824  [] (BitArray & ba, Instruction & instr)
825  {
826 // -----------------------------------------------------------------------------
827 etiss_uint8 rd = 0;
828 static BitArrayRange R_rd_0(11, 7);
829 rd += R_rd_0.read(ba) << 0;
830 etiss_uint8 rs1 = 0;
831 static BitArrayRange R_rs1_0(19, 15);
832 rs1 += R_rs1_0.read(ba) << 0;
833 etiss_uint8 shamt = 0;
834 static BitArrayRange R_shamt_0(24, 20);
835 shamt += R_shamt_0.read(ba) << 0;
836 
837 // -----------------------------------------------------------------------------
838 
839  std::stringstream ss;
840 // -----------------------------------------------------------------------------
841 ss << "sraiw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
842 // -----------------------------------------------------------------------------
843  return ss.str();
844  }
845 );
846 
847 // ADDW ------------------------------------------------------------------------
848 static InstructionDefinition addw_rd_rs1_rs2 (
849  ISA32_RV64IMACFD,
850  "addw",
851  (uint32_t) 0x00003b,
852  (uint32_t) 0xfe00707f,
853  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
854  {
855 
856 // -----------------------------------------------------------------------------
857 
858 // -----------------------------------------------------------------------------
859 
860 // -----------------------------------------------------------------------------
861 etiss_uint8 rd = 0;
862 static BitArrayRange R_rd_0(11, 7);
863 rd += R_rd_0.read(ba) << 0;
864 etiss_uint8 rs1 = 0;
865 static BitArrayRange R_rs1_0(19, 15);
866 rs1 += R_rs1_0.read(ba) << 0;
867 etiss_uint8 rs2 = 0;
868 static BitArrayRange R_rs2_0(24, 20);
869 rs2 += R_rs2_0.read(ba) << 0;
870 
871 // -----------------------------------------------------------------------------
872 
873  {
874  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
875 
876  cp.code() = std::string("//ADDW\n");
877 
878 // -----------------------------------------------------------------------------
879 { // block
880 cp.code() += "{ // block\n";
881 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
882 cp.code() += "} // block\n";
883 } // block
884 { // block
885 cp.code() += "{ // block\n";
886 if ((rd % 32ULL) != 0LL) { // conditional
887 { // block
888 cp.code() += "{ // block\n";
889 cp.code() += "etiss_int32 res = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) + (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
890 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res);\n";
891 cp.code() += "} // block\n";
892 } // block
893 } // conditional
894 cp.code() += "} // block\n";
895 } // block
896 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
897 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
898 // -----------------------------------------------------------------------------
899  cp.getAffectedRegisters().add("instructionPointer", 32);
900  }
901 
902  return true;
903  },
904  0,
905  [] (BitArray & ba, Instruction & instr)
906  {
907 // -----------------------------------------------------------------------------
908 etiss_uint8 rd = 0;
909 static BitArrayRange R_rd_0(11, 7);
910 rd += R_rd_0.read(ba) << 0;
911 etiss_uint8 rs1 = 0;
912 static BitArrayRange R_rs1_0(19, 15);
913 rs1 += R_rs1_0.read(ba) << 0;
914 etiss_uint8 rs2 = 0;
915 static BitArrayRange R_rs2_0(24, 20);
916 rs2 += R_rs2_0.read(ba) << 0;
917 
918 // -----------------------------------------------------------------------------
919 
920  std::stringstream ss;
921 // -----------------------------------------------------------------------------
922 ss << "addw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
923 // -----------------------------------------------------------------------------
924  return ss.str();
925  }
926 );
927 
928 // SUBW ------------------------------------------------------------------------
929 static InstructionDefinition subw_rd_rs1_rs2 (
930  ISA32_RV64IMACFD,
931  "subw",
932  (uint32_t) 0x4000003b,
933  (uint32_t) 0xfe00707f,
934  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
935  {
936 
937 // -----------------------------------------------------------------------------
938 
939 // -----------------------------------------------------------------------------
940 
941 // -----------------------------------------------------------------------------
942 etiss_uint8 rd = 0;
943 static BitArrayRange R_rd_0(11, 7);
944 rd += R_rd_0.read(ba) << 0;
945 etiss_uint8 rs1 = 0;
946 static BitArrayRange R_rs1_0(19, 15);
947 rs1 += R_rs1_0.read(ba) << 0;
948 etiss_uint8 rs2 = 0;
949 static BitArrayRange R_rs2_0(24, 20);
950 rs2 += R_rs2_0.read(ba) << 0;
951 
952 // -----------------------------------------------------------------------------
953 
954  {
955  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
956 
957  cp.code() = std::string("//SUBW\n");
958 
959 // -----------------------------------------------------------------------------
960 { // block
961 cp.code() += "{ // block\n";
962 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
963 cp.code() += "} // block\n";
964 } // block
965 { // block
966 cp.code() += "{ // block\n";
967 if ((rd % 32ULL) != 0LL) { // conditional
968 { // block
969 cp.code() += "{ // block\n";
970 cp.code() += "etiss_int32 res = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) - (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
971 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res);\n";
972 cp.code() += "} // block\n";
973 } // block
974 } // conditional
975 cp.code() += "} // block\n";
976 } // block
977 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
978 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
979 // -----------------------------------------------------------------------------
980  cp.getAffectedRegisters().add("instructionPointer", 32);
981  }
982 
983  return true;
984  },
985  0,
986  [] (BitArray & ba, Instruction & instr)
987  {
988 // -----------------------------------------------------------------------------
989 etiss_uint8 rd = 0;
990 static BitArrayRange R_rd_0(11, 7);
991 rd += R_rd_0.read(ba) << 0;
992 etiss_uint8 rs1 = 0;
993 static BitArrayRange R_rs1_0(19, 15);
994 rs1 += R_rs1_0.read(ba) << 0;
995 etiss_uint8 rs2 = 0;
996 static BitArrayRange R_rs2_0(24, 20);
997 rs2 += R_rs2_0.read(ba) << 0;
998 
999 // -----------------------------------------------------------------------------
1000 
1001  std::stringstream ss;
1002 // -----------------------------------------------------------------------------
1003 ss << "subw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1004 // -----------------------------------------------------------------------------
1005  return ss.str();
1006  }
1007 );
1008 
1009 // SLLW ------------------------------------------------------------------------
1010 static InstructionDefinition sllw_rd_rs1_rs2 (
1011  ISA32_RV64IMACFD,
1012  "sllw",
1013  (uint32_t) 0x00103b,
1014  (uint32_t) 0xfe00707f,
1015  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1016  {
1017 
1018 // -----------------------------------------------------------------------------
1019 
1020 // -----------------------------------------------------------------------------
1021 
1022 // -----------------------------------------------------------------------------
1023 etiss_uint8 rd = 0;
1024 static BitArrayRange R_rd_0(11, 7);
1025 rd += R_rd_0.read(ba) << 0;
1026 etiss_uint8 rs1 = 0;
1027 static BitArrayRange R_rs1_0(19, 15);
1028 rs1 += R_rs1_0.read(ba) << 0;
1029 etiss_uint8 rs2 = 0;
1030 static BitArrayRange R_rs2_0(24, 20);
1031 rs2 += R_rs2_0.read(ba) << 0;
1032 
1033 // -----------------------------------------------------------------------------
1034 
1035  {
1036  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1037 
1038  cp.code() = std::string("//SLLW\n");
1039 
1040 // -----------------------------------------------------------------------------
1041 { // block
1042 cp.code() += "{ // block\n";
1043 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1044 cp.code() += "} // block\n";
1045 } // block
1046 { // block
1047 cp.code() += "{ // block\n";
1048 if ((rd % 32ULL) != 0LL) { // conditional
1049 { // block
1050 cp.code() += "{ // block\n";
1051 cp.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) & 31ULL;\n";
1052 cp.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) << count;\n";
1053 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(sh_val));\n";
1054 cp.code() += "} // block\n";
1055 } // block
1056 } // conditional
1057 cp.code() += "} // block\n";
1058 } // block
1059 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1060 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1061 // -----------------------------------------------------------------------------
1062  cp.getAffectedRegisters().add("instructionPointer", 32);
1063  }
1064 
1065  return true;
1066  },
1067  0,
1068  [] (BitArray & ba, Instruction & instr)
1069  {
1070 // -----------------------------------------------------------------------------
1071 etiss_uint8 rd = 0;
1072 static BitArrayRange R_rd_0(11, 7);
1073 rd += R_rd_0.read(ba) << 0;
1074 etiss_uint8 rs1 = 0;
1075 static BitArrayRange R_rs1_0(19, 15);
1076 rs1 += R_rs1_0.read(ba) << 0;
1077 etiss_uint8 rs2 = 0;
1078 static BitArrayRange R_rs2_0(24, 20);
1079 rs2 += R_rs2_0.read(ba) << 0;
1080 
1081 // -----------------------------------------------------------------------------
1082 
1083  std::stringstream ss;
1084 // -----------------------------------------------------------------------------
1085 ss << "sllw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1086 // -----------------------------------------------------------------------------
1087  return ss.str();
1088  }
1089 );
1090 
1091 // SRLW ------------------------------------------------------------------------
1092 static InstructionDefinition srlw_rd_rs1_rs2 (
1093  ISA32_RV64IMACFD,
1094  "srlw",
1095  (uint32_t) 0x00503b,
1096  (uint32_t) 0xfe00707f,
1097  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1098  {
1099 
1100 // -----------------------------------------------------------------------------
1101 
1102 // -----------------------------------------------------------------------------
1103 
1104 // -----------------------------------------------------------------------------
1105 etiss_uint8 rd = 0;
1106 static BitArrayRange R_rd_0(11, 7);
1107 rd += R_rd_0.read(ba) << 0;
1108 etiss_uint8 rs1 = 0;
1109 static BitArrayRange R_rs1_0(19, 15);
1110 rs1 += R_rs1_0.read(ba) << 0;
1111 etiss_uint8 rs2 = 0;
1112 static BitArrayRange R_rs2_0(24, 20);
1113 rs2 += R_rs2_0.read(ba) << 0;
1114 
1115 // -----------------------------------------------------------------------------
1116 
1117  {
1118  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1119 
1120  cp.code() = std::string("//SRLW\n");
1121 
1122 // -----------------------------------------------------------------------------
1123 { // block
1124 cp.code() += "{ // block\n";
1125 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1126 cp.code() += "} // block\n";
1127 } // block
1128 { // block
1129 cp.code() += "{ // block\n";
1130 if ((rd % 32ULL) != 0LL) { // conditional
1131 { // block
1132 cp.code() += "{ // block\n";
1133 cp.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) & 31ULL;\n";
1134 cp.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) >> count;\n";
1135 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(sh_val));\n";
1136 cp.code() += "} // block\n";
1137 } // block
1138 } // conditional
1139 cp.code() += "} // block\n";
1140 } // block
1141 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1142 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1143 // -----------------------------------------------------------------------------
1144  cp.getAffectedRegisters().add("instructionPointer", 32);
1145  }
1146 
1147  return true;
1148  },
1149  0,
1150  [] (BitArray & ba, Instruction & instr)
1151  {
1152 // -----------------------------------------------------------------------------
1153 etiss_uint8 rd = 0;
1154 static BitArrayRange R_rd_0(11, 7);
1155 rd += R_rd_0.read(ba) << 0;
1156 etiss_uint8 rs1 = 0;
1157 static BitArrayRange R_rs1_0(19, 15);
1158 rs1 += R_rs1_0.read(ba) << 0;
1159 etiss_uint8 rs2 = 0;
1160 static BitArrayRange R_rs2_0(24, 20);
1161 rs2 += R_rs2_0.read(ba) << 0;
1162 
1163 // -----------------------------------------------------------------------------
1164 
1165  std::stringstream ss;
1166 // -----------------------------------------------------------------------------
1167 ss << "srlw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1168 // -----------------------------------------------------------------------------
1169  return ss.str();
1170  }
1171 );
1172 
1173 // SRAW ------------------------------------------------------------------------
1174 static InstructionDefinition sraw_rd_rs1_rs2 (
1175  ISA32_RV64IMACFD,
1176  "sraw",
1177  (uint32_t) 0x4000503b,
1178  (uint32_t) 0xfe00707f,
1179  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1180  {
1181 
1182 // -----------------------------------------------------------------------------
1183 
1184 // -----------------------------------------------------------------------------
1185 
1186 // -----------------------------------------------------------------------------
1187 etiss_uint8 rd = 0;
1188 static BitArrayRange R_rd_0(11, 7);
1189 rd += R_rd_0.read(ba) << 0;
1190 etiss_uint8 rs1 = 0;
1191 static BitArrayRange R_rs1_0(19, 15);
1192 rs1 += R_rs1_0.read(ba) << 0;
1193 etiss_uint8 rs2 = 0;
1194 static BitArrayRange R_rs2_0(24, 20);
1195 rs2 += R_rs2_0.read(ba) << 0;
1196 
1197 // -----------------------------------------------------------------------------
1198 
1199  {
1200  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1201 
1202  cp.code() = std::string("//SRAW\n");
1203 
1204 // -----------------------------------------------------------------------------
1205 { // block
1206 cp.code() += "{ // block\n";
1207 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1208 cp.code() += "} // block\n";
1209 } // block
1210 { // block
1211 cp.code() += "{ // block\n";
1212 if ((rd % 32ULL) != 0LL) { // conditional
1213 { // block
1214 cp.code() += "{ // block\n";
1215 cp.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) & 31ULL;\n";
1216 cp.code() += "etiss_int32 sh_val = ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) >> count;\n";
1217 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(sh_val);\n";
1218 cp.code() += "} // block\n";
1219 } // block
1220 } // conditional
1221 cp.code() += "} // block\n";
1222 } // block
1223 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1224 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1225 // -----------------------------------------------------------------------------
1226  cp.getAffectedRegisters().add("instructionPointer", 32);
1227  }
1228 
1229  return true;
1230  },
1231  0,
1232  [] (BitArray & ba, Instruction & instr)
1233  {
1234 // -----------------------------------------------------------------------------
1235 etiss_uint8 rd = 0;
1236 static BitArrayRange R_rd_0(11, 7);
1237 rd += R_rd_0.read(ba) << 0;
1238 etiss_uint8 rs1 = 0;
1239 static BitArrayRange R_rs1_0(19, 15);
1240 rs1 += R_rs1_0.read(ba) << 0;
1241 etiss_uint8 rs2 = 0;
1242 static BitArrayRange R_rs2_0(24, 20);
1243 rs2 += R_rs2_0.read(ba) << 0;
1244 
1245 // -----------------------------------------------------------------------------
1246 
1247  std::stringstream ss;
1248 // -----------------------------------------------------------------------------
1249 ss << "sraw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1250 // -----------------------------------------------------------------------------
1251  return ss.str();
1252  }
1253 );
ISA32_RV64IMACFD
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
addiw_rd_rs1_imm
static InstructionDefinition addiw_rd_rs1_imm(ISA32_RV64IMACFD, "addiw",(uint32_t) 0x00001b,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//ADDIW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if((rd % 32ULL) !=0LL) { { cp.code()+="{ // block\n";cp.code()+="etiss_int32 res = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(res);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "addiw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
srlw_rd_rs1_rs2
static InstructionDefinition srlw_rd_rs1_rs2(ISA32_RV64IMACFD, "srlw",(uint32_t) 0x00503b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRLW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if((rd % 32ULL) !=0LL) { { cp.code()+="{ // block\n";cp.code()+="etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) & 31ULL;\n";cp.code()+="etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL])) >> count;\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)((etiss_int32)(sh_val));\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "srlw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
sraw_rd_rs1_rs2
static InstructionDefinition sraw_rd_rs1_rs2(ISA32_RV64IMACFD, "sraw",(uint32_t) 0x4000503b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRAW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if((rd % 32ULL) !=0LL) { { cp.code()+="{ // block\n";cp.code()+="etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) & 31ULL;\n";cp.code()+="etiss_int32 sh_val = ((etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL])) >> count;\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(sh_val);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "sraw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
srli_rd_rs1_shamt
static InstructionDefinition srli_rd_rs1_shamt(ISA32_RV64IMACFD, "srli",(uint32_t) 0x005013,(uint32_t) 0xfc00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(25, 20);shamt+=R_shamt_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRLI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] >> "+std::to_string(shamt)+"ULL;\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(25, 20);shamt+=R_shamt_0.read(ba)<< 0;std::stringstream ss;ss<< "srli"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | shamt="+std::to_string(shamt)+"]");return ss.str();})
srliw_rd_rs1_shamt
static InstructionDefinition srliw_rd_rs1_shamt(ISA32_RV64IMACFD, "srliw",(uint32_t) 0x00501b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRLIW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if((rd % 32ULL) !=0LL) { { cp.code()+="{ // block\n";cp.code()+="etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL])) >> "+std::to_string(shamt)+"ULL;\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)((etiss_int32)(sh_val));\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;std::stringstream ss;ss<< "srliw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | shamt="+std::to_string(shamt)+"]");return ss.str();})
sraiw_rd_rs1_shamt
static InstructionDefinition sraiw_rd_rs1_shamt(ISA32_RV64IMACFD, "sraiw",(uint32_t) 0x4000501b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRAIW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if((rd % 32ULL) !=0LL) { { cp.code()+="{ // block\n";cp.code()+="etiss_int32 sh_val = ((etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL])) >> "+std::to_string(shamt)+"ULL;\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)(sh_val);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;std::stringstream ss;ss<< "sraiw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | shamt="+std::to_string(shamt)+"]");return ss.str();})
slli_rd_rs1_shamt
static InstructionDefinition slli_rd_rs1_shamt(ISA32_RV64IMACFD, "slli",(uint32_t) 0x001013,(uint32_t) 0xfc00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(25, 20);shamt+=R_shamt_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SLLI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] << "+std::to_string(shamt)+"ULL;\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(25, 20);shamt+=R_shamt_0.read(ba)<< 0;std::stringstream ss;ss<< "slli"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | shamt="+std::to_string(shamt)+"]");return ss.str();})
sllw_rd_rs1_rs2
static InstructionDefinition sllw_rd_rs1_rs2(ISA32_RV64IMACFD, "sllw",(uint32_t) 0x00103b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SLLW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if((rd % 32ULL) !=0LL) { { cp.code()+="{ // block\n";cp.code()+="etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) & 31ULL;\n";cp.code()+="etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL])) << count;\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)((etiss_int32)(sh_val));\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "sllw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
srai_rd_rs1_shamt
static InstructionDefinition srai_rd_rs1_shamt(ISA32_RV64IMACFD, "srai",(uint32_t) 0x40005013,(uint32_t) 0xfc00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(25, 20);shamt+=R_shamt_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRAI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL])) >> "+std::to_string(shamt)+"ULL;\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(25, 20);shamt+=R_shamt_0.read(ba)<< 0;std::stringstream ss;ss<< "srai"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | shamt="+std::to_string(shamt)+"]");return ss.str();})
lwu_rd_rs1_imm
static InstructionDefinition lwu_rd_rs1_imm(ISA32_RV64IMACFD, "lwu",(uint32_t) 0x006003,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//LWU\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)(res);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//LWU\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "lwu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
sd_imm_rs1_rs2
static InstructionDefinition sd_imm_rs1_rs2(ISA32_RV64IMACFD, "sd",(uint32_t) 0x003023,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SD\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//SD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "sd"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
slliw_rd_rs1_shamt
static InstructionDefinition slliw_rd_rs1_shamt(ISA32_RV64IMACFD, "slliw",(uint32_t) 0x00101b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SLLIW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if((rd % 32ULL) !=0LL) { { cp.code()+="{ // block\n";cp.code()+="etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL])) << "+std::to_string(shamt)+"ULL;\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)((etiss_int32)(sh_val));\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;std::stringstream ss;ss<< "slliw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | shamt="+std::to_string(shamt)+"]");return ss.str();})
addw_rd_rs1_rs2
static InstructionDefinition addw_rd_rs1_rs2(ISA32_RV64IMACFD, "addw",(uint32_t) 0x00003b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//ADDW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if((rd % 32ULL) !=0LL) { { cp.code()+="{ // block\n";cp.code()+="etiss_int32 res = (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) + (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(res);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "addw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
ld_rd_rs1_imm
static InstructionDefinition ld_rd_rs1_imm(ISA32_RV64IMACFD, "ld",(uint32_t) 0x003003,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//LD\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res = (etiss_int64)(mem_val_0);\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)(res);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//LD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "ld"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
subw_rd_rs1_rs2
static InstructionDefinition subw_rd_rs1_rs2(ISA32_RV64IMACFD, "subw",(uint32_t) 0x4000003b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SUBW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if((rd % 32ULL) !=0LL) { { cp.code()+="{ // block\n";cp.code()+="etiss_int32 res = (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) - (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(res);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "subw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
uint32_t
static __inline__ uint32_t
Definition: arm_cde.h:25
etiss_int16
int16_t etiss_int16
Definition: types.h:89
etiss_uint8
uint8_t etiss_uint8
Definition: types.h:87
etiss_uint16
uint16_t etiss_uint16
Definition: types.h:90
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:386
etiss::CodePart::APPENDEDRETURNINGREQUIRED
@ APPENDEDRETURNINGREQUIRED
Definition: CodePart.h:402
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition: Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition: Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
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