RV64IMACFD_RV64IInstr.cpp

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#include "RV64IMACFDArch.h"
#include "RV64IMACFDFuncs.h"
 
using namespace etiss;
using namespace etiss::instr;
 
 
// LWU -------------------------------------------------------------------------
static InstructionDefinition lwu_rd_rs1_imm (
        ISA32_RV64IMACFD,
        "lwu",
        (uint32_t) 0x006003,
        (uint32_t) 0x00707f,
        [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
        {
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
etiss_uint8 rd = 0;
static BitArrayRange R_rd_0(11, 7);
rd += R_rd_0.read(ba) << 0;
etiss_uint8 rs1 = 0;
static BitArrayRange R_rs1_0(19, 15);
rs1 += R_rs1_0.read(ba) << 0;
etiss_uint16 imm = 0;
static BitArrayRange R_imm_0(31, 20);
imm += R_imm_0.read(ba) << 0;
 
// -----------------------------------------------------------------------------
 
        {
                CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
                cp.code() = std::string("//LWU\n");
 
// -----------------------------------------------------------------------------
cp.code() += "etiss_coverage_count(1, 184);\n";
{ // block
cp.code() += "etiss_coverage_count(1, 1169);\n";
cp.code() += "{ // block\n";
cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
cp.code() += "} // block\n";
} // block
{ // block
cp.code() += "etiss_coverage_count(1, 6976);\n";
cp.code() += "{ // block\n";
cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
cp.code() += "etiss_coverage_count(7, 6952, 6951, 6947, 6946, 6944, 6950, 6948);\n";
cp.code() += "etiss_uint32 mem_val_0;\n";
cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
cp.code() += "if (cpu->exception) { // conditional\n";
{ // procedure
cp.code() += "{ // procedure\n";
cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
cp.code() += "} // procedure\n";
} // procedure
cp.code() += "} // conditional\n";
cp.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
cp.code() += "etiss_coverage_count(4, 6959, 6958, 6956, 6955);\n";
cp.code() += "etiss_coverage_count(1, 6960);\n";
if ((rd % 32ULL) != 0LL) { // conditional
cp.code() += "etiss_coverage_count(5, 6966, 6963, 6961, 6964, 6965);\n";
cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
cp.code() += "etiss_coverage_count(6, 6975, 6971, 6970, 6968, 6974, 6972);\n";
} // conditional
cp.code() += "} // block\n";
} // block
cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
// -----------------------------------------------------------------------------
                cp.getAffectedRegisters().add("instructionPointer", 32);
        }
        {
                CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
                cp.code() = std::string("//LWU\n");
 
// -----------------------------------------------------------------------------
cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
// -----------------------------------------------------------------------------
        }
 
                return true;
        },
        0,
        [] (BitArray & ba, Instruction & instr)
        {
// -----------------------------------------------------------------------------
etiss_uint8 rd = 0;
static BitArrayRange R_rd_0(11, 7);
rd += R_rd_0.read(ba) << 0;
etiss_uint8 rs1 = 0;
static BitArrayRange R_rs1_0(19, 15);
rs1 += R_rs1_0.read(ba) << 0;
etiss_uint16 imm = 0;
static BitArrayRange R_imm_0(31, 20);
imm += R_imm_0.read(ba) << 0;
 
// -----------------------------------------------------------------------------
 
                std::stringstream ss;
// -----------------------------------------------------------------------------
ss << "lwu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
// -----------------------------------------------------------------------------
                return ss.str();
        }
);
 
// LD --------------------------------------------------------------------------
static InstructionDefinition ld_rd_rs1_imm (
        ISA32_RV64IMACFD,
        "ld",
        (uint32_t) 0x003003,
        (uint32_t) 0x00707f,
        [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
        {
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
etiss_uint8 rd = 0;
static BitArrayRange R_rd_0(11, 7);
rd += R_rd_0.read(ba) << 0;
etiss_uint8 rs1 = 0;
static BitArrayRange R_rs1_0(19, 15);
rs1 += R_rs1_0.read(ba) << 0;
etiss_uint16 imm = 0;
static BitArrayRange R_imm_0(31, 20);
imm += R_imm_0.read(ba) << 0;
 
// -----------------------------------------------------------------------------
 
        {
                CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
                cp.code() = std::string("//LD\n");
 
// -----------------------------------------------------------------------------
cp.code() += "etiss_coverage_count(1, 185);\n";
{ // block
cp.code() += "etiss_coverage_count(1, 1169);\n";
cp.code() += "{ // block\n";
cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
cp.code() += "} // block\n";
} // block
{ // block
cp.code() += "etiss_coverage_count(1, 7010);\n";
cp.code() += "{ // block\n";
cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
cp.code() += "etiss_coverage_count(7, 6986, 6985, 6982, 6981, 6979, 6984, 6983);\n";
cp.code() += "etiss_uint64 mem_val_0;\n";
cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
cp.code() += "if (cpu->exception) { // conditional\n";
{ // procedure
cp.code() += "{ // procedure\n";
cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
cp.code() += "} // procedure\n";
} // procedure
cp.code() += "} // conditional\n";
cp.code() += "etiss_int64 res = (etiss_int64)(mem_val_0);\n";
cp.code() += "etiss_coverage_count(4, 6993, 6992, 6990, 6989);\n";
cp.code() += "etiss_coverage_count(1, 6994);\n";
if ((rd % 32ULL) != 0LL) { // conditional
cp.code() += "etiss_coverage_count(5, 7000, 6997, 6995, 6998, 6999);\n";
cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
cp.code() += "etiss_coverage_count(6, 7009, 7005, 7004, 7002, 7008, 7006);\n";
} // conditional
cp.code() += "} // block\n";
} // block
cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
// -----------------------------------------------------------------------------
                cp.getAffectedRegisters().add("instructionPointer", 32);
        }
        {
                CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
                cp.code() = std::string("//LD\n");
 
// -----------------------------------------------------------------------------
cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
// -----------------------------------------------------------------------------
        }
 
                return true;
        },
        0,
        [] (BitArray & ba, Instruction & instr)
        {
// -----------------------------------------------------------------------------
etiss_uint8 rd = 0;
static BitArrayRange R_rd_0(11, 7);
rd += R_rd_0.read(ba) << 0;
etiss_uint8 rs1 = 0;
static BitArrayRange R_rs1_0(19, 15);
rs1 += R_rs1_0.read(ba) << 0;
etiss_uint16 imm = 0;
static BitArrayRange R_imm_0(31, 20);
imm += R_imm_0.read(ba) << 0;
 
// -----------------------------------------------------------------------------
 
                std::stringstream ss;
// -----------------------------------------------------------------------------
ss << "ld" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
// -----------------------------------------------------------------------------
                return ss.str();
        }
);
 
// SD --------------------------------------------------------------------------
static InstructionDefinition sd_imm_rs1_rs2 (
        ISA32_RV64IMACFD,
        "sd",
        (uint32_t) 0x003023,
        (uint32_t) 0x00707f,
        [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
        {
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
etiss_uint16 imm = 0;
static BitArrayRange R_imm_0(11, 7);
imm += R_imm_0.read(ba) << 0;
etiss_uint8 rs1 = 0;
static BitArrayRange R_rs1_0(19, 15);
rs1 += R_rs1_0.read(ba) << 0;
etiss_uint8 rs2 = 0;
static BitArrayRange R_rs2_0(24, 20);
rs2 += R_rs2_0.read(ba) << 0;
static BitArrayRange R_imm_5(31, 25);
imm += R_imm_5.read(ba) << 5;
 
// -----------------------------------------------------------------------------
 
        {
                CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
                cp.code() = std::string("//SD\n");
 
// -----------------------------------------------------------------------------
cp.code() += "etiss_coverage_count(1, 186);\n";
{ // block
cp.code() += "etiss_coverage_count(1, 1169);\n";
cp.code() += "{ // block\n";
cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
cp.code() += "} // block\n";
} // block
{ // block
cp.code() += "etiss_coverage_count(1, 7032);\n";
cp.code() += "{ // block\n";
cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
cp.code() += "etiss_coverage_count(7, 7020, 7019, 7016, 7015, 7013, 7018, 7017);\n";
cp.code() += "etiss_uint64 mem_val_0;\n";
cp.code() += "mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
cp.code() += "etiss_coverage_count(7, 7031, 7023, 7022, 7030, 7028, 7027, 7025);\n";
cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
cp.code() += "if (cpu->exception) { // conditional\n";
{ // procedure
cp.code() += "{ // procedure\n";
cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
cp.code() += "} // procedure\n";
} // procedure
cp.code() += "} // conditional\n";
cp.code() += "} // block\n";
} // block
cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
// -----------------------------------------------------------------------------
                cp.getAffectedRegisters().add("instructionPointer", 32);
        }
        {
                CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
 
                cp.code() = std::string("//SD\n");
 
// -----------------------------------------------------------------------------
cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
// -----------------------------------------------------------------------------
        }
 
                return true;
        },
        0,
        [] (BitArray & ba, Instruction & instr)
        {
// -----------------------------------------------------------------------------
etiss_uint16 imm = 0;
static BitArrayRange R_imm_0(11, 7);
imm += R_imm_0.read(ba) << 0;
etiss_uint8 rs1 = 0;
static BitArrayRange R_rs1_0(19, 15);
rs1 += R_rs1_0.read(ba) << 0;
etiss_uint8 rs2 = 0;
static BitArrayRange R_rs2_0(24, 20);
rs2 += R_rs2_0.read(ba) << 0;
static BitArrayRange R_imm_5(31, 25);
imm += R_imm_5.read(ba) << 5;
 
// -----------------------------------------------------------------------------
 
                std::stringstream ss;
// -----------------------------------------------------------------------------
ss << "sd" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
// -----------------------------------------------------------------------------
                return ss.str();
        }
);
 
// SLLI ------------------------------------------------------------------------
static InstructionDefinition slli_rd_rs1_shamt (
        ISA32_RV64IMACFD,
        "slli",
        (uint32_t) 0x001013,
        (uint32_t) 0xfc00707f,
        [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
        {
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
etiss_uint8 rd = 0;
static BitArrayRange R_rd_0(11, 7);
rd += R_rd_0.read(ba) << 0;
etiss_uint8 rs1 = 0;
static BitArrayRange R_rs1_0(19, 15);
rs1 += R_rs1_0.read(ba) << 0;
etiss_uint8 shamt = 0;
static BitArrayRange R_shamt_0(25, 20);
shamt += R_shamt_0.read(ba) << 0;
 
// -----------------------------------------------------------------------------
 
        {
                CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
                cp.code() = std::string("//SLLI\n");
 
// -----------------------------------------------------------------------------
cp.code() += "etiss_coverage_count(1, 187);\n";
{ // block
cp.code() += "etiss_coverage_count(1, 1169);\n";
cp.code() += "{ // block\n";
cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
cp.code() += "} // block\n";
} // block
cp.code() += "etiss_coverage_count(1, 7033);\n";
if ((rd % 32ULL) != 0LL) { // conditional
cp.code() += "etiss_coverage_count(5, 7039, 7036, 7034, 7037, 7038);\n";
cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << " + std::to_string(shamt) + "ULL;\n";
cp.code() += "etiss_coverage_count(9, 7052, 7044, 7043, 7041, 7051, 7049, 7048, 7046, 7050);\n";
} // conditional
cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
// -----------------------------------------------------------------------------
                cp.getAffectedRegisters().add("instructionPointer", 32);
        }
 
                return true;
        },
        0,
        [] (BitArray & ba, Instruction & instr)
        {
// -----------------------------------------------------------------------------
etiss_uint8 rd = 0;
static BitArrayRange R_rd_0(11, 7);
rd += R_rd_0.read(ba) << 0;
etiss_uint8 rs1 = 0;
static BitArrayRange R_rs1_0(19, 15);
rs1 += R_rs1_0.read(ba) << 0;
etiss_uint8 shamt = 0;
static BitArrayRange R_shamt_0(25, 20);
shamt += R_shamt_0.read(ba) << 0;
 
// -----------------------------------------------------------------------------
 
                std::stringstream ss;
// -----------------------------------------------------------------------------
ss << "slli" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
// -----------------------------------------------------------------------------
                return ss.str();
        }
);
 
// SRLI ------------------------------------------------------------------------
static InstructionDefinition srli_rd_rs1_shamt (
        ISA32_RV64IMACFD,
        "srli",
        (uint32_t) 0x005013,
        (uint32_t) 0xfc00707f,
        [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
        {
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
etiss_uint8 rd = 0;
static BitArrayRange R_rd_0(11, 7);
rd += R_rd_0.read(ba) << 0;
etiss_uint8 rs1 = 0;
static BitArrayRange R_rs1_0(19, 15);
rs1 += R_rs1_0.read(ba) << 0;
etiss_uint8 shamt = 0;
static BitArrayRange R_shamt_0(25, 20);
shamt += R_shamt_0.read(ba) << 0;
 
// -----------------------------------------------------------------------------
 
        {
                CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
                cp.code() = std::string("//SRLI\n");
 
// -----------------------------------------------------------------------------
cp.code() += "etiss_coverage_count(1, 188);\n";
{ // block
cp.code() += "etiss_coverage_count(1, 1169);\n";
cp.code() += "{ // block\n";
cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
cp.code() += "} // block\n";
} // block
cp.code() += "etiss_coverage_count(1, 7053);\n";
if ((rd % 32ULL) != 0LL) { // conditional
cp.code() += "etiss_coverage_count(5, 7059, 7056, 7054, 7057, 7058);\n";
cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >> " + std::to_string(shamt) + "ULL;\n";
cp.code() += "etiss_coverage_count(9, 7072, 7064, 7063, 7061, 7071, 7069, 7068, 7066, 7070);\n";
} // conditional
cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
// -----------------------------------------------------------------------------
                cp.getAffectedRegisters().add("instructionPointer", 32);
        }
 
                return true;
        },
        0,
        [] (BitArray & ba, Instruction & instr)
        {
// -----------------------------------------------------------------------------
etiss_uint8 rd = 0;
static BitArrayRange R_rd_0(11, 7);
rd += R_rd_0.read(ba) << 0;
etiss_uint8 rs1 = 0;
static BitArrayRange R_rs1_0(19, 15);
rs1 += R_rs1_0.read(ba) << 0;
etiss_uint8 shamt = 0;
static BitArrayRange R_shamt_0(25, 20);
shamt += R_shamt_0.read(ba) << 0;
 
// -----------------------------------------------------------------------------
 
                std::stringstream ss;
// -----------------------------------------------------------------------------
ss << "srli" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
// -----------------------------------------------------------------------------
                return ss.str();
        }
);
 
// SRAI ------------------------------------------------------------------------
static InstructionDefinition srai_rd_rs1_shamt (
        ISA32_RV64IMACFD,
        "srai",
        (uint32_t) 0x40005013,
        (uint32_t) 0xfc00707f,
        [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
        {
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
etiss_uint8 rd = 0;
static BitArrayRange R_rd_0(11, 7);
rd += R_rd_0.read(ba) << 0;
etiss_uint8 rs1 = 0;
static BitArrayRange R_rs1_0(19, 15);
rs1 += R_rs1_0.read(ba) << 0;
etiss_uint8 shamt = 0;
static BitArrayRange R_shamt_0(25, 20);
shamt += R_shamt_0.read(ba) << 0;
 
// -----------------------------------------------------------------------------
 
        {
                CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
                cp.code() = std::string("//SRAI\n");
 
// -----------------------------------------------------------------------------
cp.code() += "etiss_coverage_count(1, 189);\n";
{ // block
cp.code() += "etiss_coverage_count(1, 1169);\n";
cp.code() += "{ // block\n";
cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
cp.code() += "} // block\n";
} // block
cp.code() += "etiss_coverage_count(1, 7073);\n";
if ((rd % 32ULL) != 0LL) { // conditional
cp.code() += "etiss_coverage_count(5, 7079, 7076, 7074, 7077, 7078);\n";
cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) >> " + std::to_string(shamt) + "ULL;\n";
cp.code() += "etiss_coverage_count(11, 7094, 7084, 7083, 7081, 7093, 7090, 7089, 7088, 7086, 7091, 7092);\n";
} // conditional
cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
// -----------------------------------------------------------------------------
                cp.getAffectedRegisters().add("instructionPointer", 32);
        }
 
                return true;
        },
        0,
        [] (BitArray & ba, Instruction & instr)
        {
// -----------------------------------------------------------------------------
etiss_uint8 rd = 0;
static BitArrayRange R_rd_0(11, 7);
rd += R_rd_0.read(ba) << 0;
etiss_uint8 rs1 = 0;
static BitArrayRange R_rs1_0(19, 15);
rs1 += R_rs1_0.read(ba) << 0;
etiss_uint8 shamt = 0;
static BitArrayRange R_shamt_0(25, 20);
shamt += R_shamt_0.read(ba) << 0;
 
// -----------------------------------------------------------------------------
 
                std::stringstream ss;
// -----------------------------------------------------------------------------
ss << "srai" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
// -----------------------------------------------------------------------------
                return ss.str();
        }
);
 
// ADDIW -----------------------------------------------------------------------
static InstructionDefinition addiw_rd_rs1_imm (
        ISA32_RV64IMACFD,
        "addiw",
        (uint32_t) 0x00001b,
        (uint32_t) 0x00707f,
        [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
        {
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
etiss_uint8 rd = 0;
static BitArrayRange R_rd_0(11, 7);
rd += R_rd_0.read(ba) << 0;
etiss_uint8 rs1 = 0;
static BitArrayRange R_rs1_0(19, 15);
rs1 += R_rs1_0.read(ba) << 0;
etiss_uint16 imm = 0;
static BitArrayRange R_imm_0(31, 20);
imm += R_imm_0.read(ba) << 0;
 
// -----------------------------------------------------------------------------
 
        {
                CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
                cp.code() = std::string("//ADDIW\n");
 
// -----------------------------------------------------------------------------
cp.code() += "etiss_coverage_count(1, 190);\n";
{ // block
cp.code() += "etiss_coverage_count(1, 1169);\n";
cp.code() += "{ // block\n";
cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
cp.code() += "} // block\n";
} // block
{ // block
cp.code() += "etiss_coverage_count(1, 7122);\n";
cp.code() += "{ // block\n";
cp.code() += "etiss_coverage_count(1, 7095);\n";
if ((rd % 32ULL) != 0LL) { // conditional
cp.code() += "etiss_coverage_count(5, 7101, 7098, 7096, 7099, 7100);\n";
{ // block
cp.code() += "etiss_coverage_count(1, 7121);\n";
cp.code() += "{ // block\n";
cp.code() += "etiss_int32 res = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
cp.code() += "etiss_coverage_count(7, 7111, 7110, 7107, 7106, 7104, 7109, 7108);\n";
cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res);\n";
cp.code() += "etiss_coverage_count(6, 7120, 7116, 7115, 7113, 7119, 7117);\n";
cp.code() += "} // block\n";
} // block
} // conditional
cp.code() += "} // block\n";
} // block
cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
// -----------------------------------------------------------------------------
                cp.getAffectedRegisters().add("instructionPointer", 32);
        }
 
                return true;
        },
        0,
        [] (BitArray & ba, Instruction & instr)
        {
// -----------------------------------------------------------------------------
etiss_uint8 rd = 0;
static BitArrayRange R_rd_0(11, 7);
rd += R_rd_0.read(ba) << 0;
etiss_uint8 rs1 = 0;
static BitArrayRange R_rs1_0(19, 15);
rs1 += R_rs1_0.read(ba) << 0;
etiss_uint16 imm = 0;
static BitArrayRange R_imm_0(31, 20);
imm += R_imm_0.read(ba) << 0;
 
// -----------------------------------------------------------------------------
 
                std::stringstream ss;
// -----------------------------------------------------------------------------
ss << "addiw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
// -----------------------------------------------------------------------------
                return ss.str();
        }
);
 
// SLLIW -----------------------------------------------------------------------
static InstructionDefinition slliw_rd_rs1_shamt (
        ISA32_RV64IMACFD,
        "slliw",
        (uint32_t) 0x00101b,
        (uint32_t) 0xfe00707f,
        [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
        {
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
etiss_uint8 rd = 0;
static BitArrayRange R_rd_0(11, 7);
rd += R_rd_0.read(ba) << 0;
etiss_uint8 rs1 = 0;
static BitArrayRange R_rs1_0(19, 15);
rs1 += R_rs1_0.read(ba) << 0;
etiss_uint8 shamt = 0;
static BitArrayRange R_shamt_0(24, 20);
shamt += R_shamt_0.read(ba) << 0;
 
// -----------------------------------------------------------------------------
 
        {
                CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
                cp.code() = std::string("//SLLIW\n");
 
// -----------------------------------------------------------------------------
cp.code() += "etiss_coverage_count(1, 191);\n";
{ // block
cp.code() += "etiss_coverage_count(1, 1169);\n";
cp.code() += "{ // block\n";
cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
cp.code() += "} // block\n";
} // block
{ // block
cp.code() += "etiss_coverage_count(1, 7153);\n";
cp.code() += "{ // block\n";
cp.code() += "etiss_coverage_count(1, 7123);\n";
if ((rd % 32ULL) != 0LL) { // conditional
cp.code() += "etiss_coverage_count(5, 7129, 7126, 7124, 7127, 7128);\n";
{ // block
cp.code() += "etiss_coverage_count(1, 7152);\n";
cp.code() += "{ // block\n";
cp.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) << " + std::to_string(shamt) + "ULL;\n";
cp.code() += "etiss_coverage_count(8, 7141, 7140, 7137, 7135, 7134, 7132, 7138, 7139);\n";
cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(sh_val));\n";
cp.code() += "etiss_coverage_count(7, 7151, 7146, 7145, 7143, 7150, 7148, 7147);\n";
cp.code() += "} // block\n";
} // block
} // conditional
cp.code() += "} // block\n";
} // block
cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
// -----------------------------------------------------------------------------
                cp.getAffectedRegisters().add("instructionPointer", 32);
        }
 
                return true;
        },
        0,
        [] (BitArray & ba, Instruction & instr)
        {
// -----------------------------------------------------------------------------
etiss_uint8 rd = 0;
static BitArrayRange R_rd_0(11, 7);
rd += R_rd_0.read(ba) << 0;
etiss_uint8 rs1 = 0;
static BitArrayRange R_rs1_0(19, 15);
rs1 += R_rs1_0.read(ba) << 0;
etiss_uint8 shamt = 0;
static BitArrayRange R_shamt_0(24, 20);
shamt += R_shamt_0.read(ba) << 0;
 
// -----------------------------------------------------------------------------
 
                std::stringstream ss;
// -----------------------------------------------------------------------------
ss << "slliw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
// -----------------------------------------------------------------------------
                return ss.str();
        }
);
 
// SRLIW -----------------------------------------------------------------------
static InstructionDefinition srliw_rd_rs1_shamt (
        ISA32_RV64IMACFD,
        "srliw",
        (uint32_t) 0x00501b,
        (uint32_t) 0xfe00707f,
        [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
        {
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
etiss_uint8 rd = 0;
static BitArrayRange R_rd_0(11, 7);
rd += R_rd_0.read(ba) << 0;
etiss_uint8 rs1 = 0;
static BitArrayRange R_rs1_0(19, 15);
rs1 += R_rs1_0.read(ba) << 0;
etiss_uint8 shamt = 0;
static BitArrayRange R_shamt_0(24, 20);
shamt += R_shamt_0.read(ba) << 0;
 
// -----------------------------------------------------------------------------
 
        {
                CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
                cp.code() = std::string("//SRLIW\n");
 
// -----------------------------------------------------------------------------
cp.code() += "etiss_coverage_count(1, 192);\n";
{ // block
cp.code() += "etiss_coverage_count(1, 1169);\n";
cp.code() += "{ // block\n";
cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
cp.code() += "} // block\n";
} // block
{ // block
cp.code() += "etiss_coverage_count(1, 7184);\n";
cp.code() += "{ // block\n";
cp.code() += "etiss_coverage_count(1, 7154);\n";
if ((rd % 32ULL) != 0LL) { // conditional
cp.code() += "etiss_coverage_count(5, 7160, 7157, 7155, 7158, 7159);\n";
{ // block
cp.code() += "etiss_coverage_count(1, 7183);\n";
cp.code() += "{ // block\n";
cp.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) >> " + std::to_string(shamt) + "ULL;\n";
cp.code() += "etiss_coverage_count(8, 7172, 7171, 7168, 7166, 7165, 7163, 7169, 7170);\n";
cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(sh_val));\n";
cp.code() += "etiss_coverage_count(7, 7182, 7177, 7176, 7174, 7181, 7179, 7178);\n";
cp.code() += "} // block\n";
} // block
} // conditional
cp.code() += "} // block\n";
} // block
cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
// -----------------------------------------------------------------------------
                cp.getAffectedRegisters().add("instructionPointer", 32);
        }
 
                return true;
        },
        0,
        [] (BitArray & ba, Instruction & instr)
        {
// -----------------------------------------------------------------------------
etiss_uint8 rd = 0;
static BitArrayRange R_rd_0(11, 7);
rd += R_rd_0.read(ba) << 0;
etiss_uint8 rs1 = 0;
static BitArrayRange R_rs1_0(19, 15);
rs1 += R_rs1_0.read(ba) << 0;
etiss_uint8 shamt = 0;
static BitArrayRange R_shamt_0(24, 20);
shamt += R_shamt_0.read(ba) << 0;
 
// -----------------------------------------------------------------------------
 
                std::stringstream ss;
// -----------------------------------------------------------------------------
ss << "srliw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
// -----------------------------------------------------------------------------
                return ss.str();
        }
);
 
// SRAIW -----------------------------------------------------------------------
static InstructionDefinition sraiw_rd_rs1_shamt (
        ISA32_RV64IMACFD,
        "sraiw",
        (uint32_t) 0x4000501b,
        (uint32_t) 0xfe00707f,
        [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
        {
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
etiss_uint8 rd = 0;
static BitArrayRange R_rd_0(11, 7);
rd += R_rd_0.read(ba) << 0;
etiss_uint8 rs1 = 0;
static BitArrayRange R_rs1_0(19, 15);
rs1 += R_rs1_0.read(ba) << 0;
etiss_uint8 shamt = 0;
static BitArrayRange R_shamt_0(24, 20);
shamt += R_shamt_0.read(ba) << 0;
 
// -----------------------------------------------------------------------------
 
        {
                CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
                cp.code() = std::string("//SRAIW\n");
 
// -----------------------------------------------------------------------------
cp.code() += "etiss_coverage_count(1, 193);\n";
{ // block
cp.code() += "etiss_coverage_count(1, 1169);\n";
cp.code() += "{ // block\n";
cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
cp.code() += "} // block\n";
} // block
{ // block
cp.code() += "etiss_coverage_count(1, 7214);\n";
cp.code() += "{ // block\n";
cp.code() += "etiss_coverage_count(1, 7185);\n";
if ((rd % 32ULL) != 0LL) { // conditional
cp.code() += "etiss_coverage_count(5, 7191, 7188, 7186, 7189, 7190);\n";
{ // block
cp.code() += "etiss_coverage_count(1, 7213);\n";
cp.code() += "{ // block\n";
cp.code() += "etiss_int32 sh_val = ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) >> " + std::to_string(shamt) + "ULL;\n";
cp.code() += "etiss_coverage_count(8, 7203, 7202, 7199, 7197, 7196, 7194, 7200, 7201);\n";
cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(sh_val);\n";
cp.code() += "etiss_coverage_count(6, 7212, 7208, 7207, 7205, 7211, 7209);\n";
cp.code() += "} // block\n";
} // block
} // conditional
cp.code() += "} // block\n";
} // block
cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
// -----------------------------------------------------------------------------
                cp.getAffectedRegisters().add("instructionPointer", 32);
        }
 
                return true;
        },
        0,
        [] (BitArray & ba, Instruction & instr)
        {
// -----------------------------------------------------------------------------
etiss_uint8 rd = 0;
static BitArrayRange R_rd_0(11, 7);
rd += R_rd_0.read(ba) << 0;
etiss_uint8 rs1 = 0;
static BitArrayRange R_rs1_0(19, 15);
rs1 += R_rs1_0.read(ba) << 0;
etiss_uint8 shamt = 0;
static BitArrayRange R_shamt_0(24, 20);
shamt += R_shamt_0.read(ba) << 0;
 
// -----------------------------------------------------------------------------
 
                std::stringstream ss;
// -----------------------------------------------------------------------------
ss << "sraiw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
// -----------------------------------------------------------------------------
                return ss.str();
        }
);
 
// ADDW ------------------------------------------------------------------------
static InstructionDefinition addw_rd_rs1_rs2 (
        ISA32_RV64IMACFD,
        "addw",
        (uint32_t) 0x00003b,
        (uint32_t) 0xfe00707f,
        [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
        {
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
etiss_uint8 rd = 0;
static BitArrayRange R_rd_0(11, 7);
rd += R_rd_0.read(ba) << 0;
etiss_uint8 rs1 = 0;
static BitArrayRange R_rs1_0(19, 15);
rs1 += R_rs1_0.read(ba) << 0;
etiss_uint8 rs2 = 0;
static BitArrayRange R_rs2_0(24, 20);
rs2 += R_rs2_0.read(ba) << 0;
 
// -----------------------------------------------------------------------------
 
        {
                CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
                cp.code() = std::string("//ADDW\n");
 
// -----------------------------------------------------------------------------
cp.code() += "etiss_coverage_count(1, 194);\n";
{ // block
cp.code() += "etiss_coverage_count(1, 1169);\n";
cp.code() += "{ // block\n";
cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
cp.code() += "} // block\n";
} // block
{ // block
cp.code() += "etiss_coverage_count(1, 7249);\n";
cp.code() += "{ // block\n";
cp.code() += "etiss_coverage_count(1, 7215);\n";
if ((rd % 32ULL) != 0LL) { // conditional
cp.code() += "etiss_coverage_count(5, 7221, 7218, 7216, 7219, 7220);\n";
{ // block
cp.code() += "etiss_coverage_count(1, 7248);\n";
cp.code() += "{ // block\n";
cp.code() += "etiss_int32 res = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) + (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
cp.code() += "etiss_coverage_count(10, 7238, 7237, 7229, 7227, 7226, 7224, 7236, 7234, 7233, 7231);\n";
cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res);\n";
cp.code() += "etiss_coverage_count(6, 7247, 7243, 7242, 7240, 7246, 7244);\n";
cp.code() += "} // block\n";
} // block
} // conditional
cp.code() += "} // block\n";
} // block
cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
// -----------------------------------------------------------------------------
                cp.getAffectedRegisters().add("instructionPointer", 32);
        }
 
                return true;
        },
        0,
        [] (BitArray & ba, Instruction & instr)
        {
// -----------------------------------------------------------------------------
etiss_uint8 rd = 0;
static BitArrayRange R_rd_0(11, 7);
rd += R_rd_0.read(ba) << 0;
etiss_uint8 rs1 = 0;
static BitArrayRange R_rs1_0(19, 15);
rs1 += R_rs1_0.read(ba) << 0;
etiss_uint8 rs2 = 0;
static BitArrayRange R_rs2_0(24, 20);
rs2 += R_rs2_0.read(ba) << 0;
 
// -----------------------------------------------------------------------------
 
                std::stringstream ss;
// -----------------------------------------------------------------------------
ss << "addw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
// -----------------------------------------------------------------------------
                return ss.str();
        }
);
 
// SUBW ------------------------------------------------------------------------
static InstructionDefinition subw_rd_rs1_rs2 (
        ISA32_RV64IMACFD,
        "subw",
        (uint32_t) 0x4000003b,
        (uint32_t) 0xfe00707f,
        [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
        {
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
etiss_uint8 rd = 0;
static BitArrayRange R_rd_0(11, 7);
rd += R_rd_0.read(ba) << 0;
etiss_uint8 rs1 = 0;
static BitArrayRange R_rs1_0(19, 15);
rs1 += R_rs1_0.read(ba) << 0;
etiss_uint8 rs2 = 0;
static BitArrayRange R_rs2_0(24, 20);
rs2 += R_rs2_0.read(ba) << 0;
 
// -----------------------------------------------------------------------------
 
        {
                CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
                cp.code() = std::string("//SUBW\n");
 
// -----------------------------------------------------------------------------
cp.code() += "etiss_coverage_count(1, 195);\n";
{ // block
cp.code() += "etiss_coverage_count(1, 1169);\n";
cp.code() += "{ // block\n";
cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
cp.code() += "} // block\n";
} // block
{ // block
cp.code() += "etiss_coverage_count(1, 7284);\n";
cp.code() += "{ // block\n";
cp.code() += "etiss_coverage_count(1, 7250);\n";
if ((rd % 32ULL) != 0LL) { // conditional
cp.code() += "etiss_coverage_count(5, 7256, 7253, 7251, 7254, 7255);\n";
{ // block
cp.code() += "etiss_coverage_count(1, 7283);\n";
cp.code() += "{ // block\n";
cp.code() += "etiss_int32 res = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) - (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
cp.code() += "etiss_coverage_count(10, 7273, 7272, 7264, 7262, 7261, 7259, 7271, 7269, 7268, 7266);\n";
cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res);\n";
cp.code() += "etiss_coverage_count(6, 7282, 7278, 7277, 7275, 7281, 7279);\n";
cp.code() += "} // block\n";
} // block
} // conditional
cp.code() += "} // block\n";
} // block
cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
// -----------------------------------------------------------------------------
                cp.getAffectedRegisters().add("instructionPointer", 32);
        }
 
                return true;
        },
        0,
        [] (BitArray & ba, Instruction & instr)
        {
// -----------------------------------------------------------------------------
etiss_uint8 rd = 0;
static BitArrayRange R_rd_0(11, 7);
rd += R_rd_0.read(ba) << 0;
etiss_uint8 rs1 = 0;
static BitArrayRange R_rs1_0(19, 15);
rs1 += R_rs1_0.read(ba) << 0;
etiss_uint8 rs2 = 0;
static BitArrayRange R_rs2_0(24, 20);
rs2 += R_rs2_0.read(ba) << 0;
 
// -----------------------------------------------------------------------------
 
                std::stringstream ss;
// -----------------------------------------------------------------------------
ss << "subw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
// -----------------------------------------------------------------------------
                return ss.str();
        }
);
 
// SLLW ------------------------------------------------------------------------
static InstructionDefinition sllw_rd_rs1_rs2 (
        ISA32_RV64IMACFD,
        "sllw",
        (uint32_t) 0x00103b,
        (uint32_t) 0xfe00707f,
        [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
        {
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
etiss_uint8 rd = 0;
static BitArrayRange R_rd_0(11, 7);
rd += R_rd_0.read(ba) << 0;
etiss_uint8 rs1 = 0;
static BitArrayRange R_rs1_0(19, 15);
rs1 += R_rs1_0.read(ba) << 0;
etiss_uint8 rs2 = 0;
static BitArrayRange R_rs2_0(24, 20);
rs2 += R_rs2_0.read(ba) << 0;
 
// -----------------------------------------------------------------------------
 
        {
                CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
                cp.code() = std::string("//SLLW\n");
 
// -----------------------------------------------------------------------------
cp.code() += "etiss_coverage_count(1, 196);\n";
{ // block
cp.code() += "etiss_coverage_count(1, 1169);\n";
cp.code() += "{ // block\n";
cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
cp.code() += "} // block\n";
} // block
{ // block
cp.code() += "etiss_coverage_count(1, 7325);\n";
cp.code() += "{ // block\n";
cp.code() += "etiss_coverage_count(1, 7285);\n";
if ((rd % 32ULL) != 0LL) { // conditional
cp.code() += "etiss_coverage_count(5, 7291, 7288, 7286, 7289, 7290);\n";
{ // block
cp.code() += "etiss_coverage_count(1, 7324);\n";
cp.code() += "{ // block\n";
cp.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) & 31ULL;\n";
cp.code() += "etiss_coverage_count(7, 7301, 7300, 7298, 7297, 7296, 7294, 7299);\n";
cp.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) << count;\n";
cp.code() += "etiss_coverage_count(8, 7313, 7312, 7309, 7307, 7306, 7304, 7310, 7311);\n";
cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(sh_val));\n";
cp.code() += "etiss_coverage_count(7, 7323, 7318, 7317, 7315, 7322, 7320, 7319);\n";
cp.code() += "} // block\n";
} // block
} // conditional
cp.code() += "} // block\n";
} // block
cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
// -----------------------------------------------------------------------------
                cp.getAffectedRegisters().add("instructionPointer", 32);
        }
 
                return true;
        },
        0,
        [] (BitArray & ba, Instruction & instr)
        {
// -----------------------------------------------------------------------------
etiss_uint8 rd = 0;
static BitArrayRange R_rd_0(11, 7);
rd += R_rd_0.read(ba) << 0;
etiss_uint8 rs1 = 0;
static BitArrayRange R_rs1_0(19, 15);
rs1 += R_rs1_0.read(ba) << 0;
etiss_uint8 rs2 = 0;
static BitArrayRange R_rs2_0(24, 20);
rs2 += R_rs2_0.read(ba) << 0;
 
// -----------------------------------------------------------------------------
 
                std::stringstream ss;
// -----------------------------------------------------------------------------
ss << "sllw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
// -----------------------------------------------------------------------------
                return ss.str();
        }
);
 
// SRLW ------------------------------------------------------------------------
static InstructionDefinition srlw_rd_rs1_rs2 (
        ISA32_RV64IMACFD,
        "srlw",
        (uint32_t) 0x00503b,
        (uint32_t) 0xfe00707f,
        [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
        {
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
etiss_uint8 rd = 0;
static BitArrayRange R_rd_0(11, 7);
rd += R_rd_0.read(ba) << 0;
etiss_uint8 rs1 = 0;
static BitArrayRange R_rs1_0(19, 15);
rs1 += R_rs1_0.read(ba) << 0;
etiss_uint8 rs2 = 0;
static BitArrayRange R_rs2_0(24, 20);
rs2 += R_rs2_0.read(ba) << 0;
 
// -----------------------------------------------------------------------------
 
        {
                CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
                cp.code() = std::string("//SRLW\n");
 
// -----------------------------------------------------------------------------
cp.code() += "etiss_coverage_count(1, 197);\n";
{ // block
cp.code() += "etiss_coverage_count(1, 1169);\n";
cp.code() += "{ // block\n";
cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
cp.code() += "} // block\n";
} // block
{ // block
cp.code() += "etiss_coverage_count(1, 7366);\n";
cp.code() += "{ // block\n";
cp.code() += "etiss_coverage_count(1, 7326);\n";
if ((rd % 32ULL) != 0LL) { // conditional
cp.code() += "etiss_coverage_count(5, 7332, 7329, 7327, 7330, 7331);\n";
{ // block
cp.code() += "etiss_coverage_count(1, 7365);\n";
cp.code() += "{ // block\n";
cp.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) & 31ULL;\n";
cp.code() += "etiss_coverage_count(7, 7342, 7341, 7339, 7338, 7337, 7335, 7340);\n";
cp.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) >> count;\n";
cp.code() += "etiss_coverage_count(8, 7354, 7353, 7350, 7348, 7347, 7345, 7351, 7352);\n";
cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(sh_val));\n";
cp.code() += "etiss_coverage_count(7, 7364, 7359, 7358, 7356, 7363, 7361, 7360);\n";
cp.code() += "} // block\n";
} // block
} // conditional
cp.code() += "} // block\n";
} // block
cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
// -----------------------------------------------------------------------------
                cp.getAffectedRegisters().add("instructionPointer", 32);
        }
 
                return true;
        },
        0,
        [] (BitArray & ba, Instruction & instr)
        {
// -----------------------------------------------------------------------------
etiss_uint8 rd = 0;
static BitArrayRange R_rd_0(11, 7);
rd += R_rd_0.read(ba) << 0;
etiss_uint8 rs1 = 0;
static BitArrayRange R_rs1_0(19, 15);
rs1 += R_rs1_0.read(ba) << 0;
etiss_uint8 rs2 = 0;
static BitArrayRange R_rs2_0(24, 20);
rs2 += R_rs2_0.read(ba) << 0;
 
// -----------------------------------------------------------------------------
 
                std::stringstream ss;
// -----------------------------------------------------------------------------
ss << "srlw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
// -----------------------------------------------------------------------------
                return ss.str();
        }
);
 
// SRAW ------------------------------------------------------------------------
static InstructionDefinition sraw_rd_rs1_rs2 (
        ISA32_RV64IMACFD,
        "sraw",
        (uint32_t) 0x4000503b,
        (uint32_t) 0xfe00707f,
        [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
        {
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
 
// -----------------------------------------------------------------------------
etiss_uint8 rd = 0;
static BitArrayRange R_rd_0(11, 7);
rd += R_rd_0.read(ba) << 0;
etiss_uint8 rs1 = 0;
static BitArrayRange R_rs1_0(19, 15);
rs1 += R_rs1_0.read(ba) << 0;
etiss_uint8 rs2 = 0;
static BitArrayRange R_rs2_0(24, 20);
rs2 += R_rs2_0.read(ba) << 0;
 
// -----------------------------------------------------------------------------
 
        {
                CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
 
                cp.code() = std::string("//SRAW\n");
 
// -----------------------------------------------------------------------------
cp.code() += "etiss_coverage_count(1, 198);\n";
{ // block
cp.code() += "etiss_coverage_count(1, 1169);\n";
cp.code() += "{ // block\n";
cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
cp.code() += "} // block\n";
} // block
{ // block
cp.code() += "etiss_coverage_count(1, 7406);\n";
cp.code() += "{ // block\n";
cp.code() += "etiss_coverage_count(1, 7367);\n";
if ((rd % 32ULL) != 0LL) { // conditional
cp.code() += "etiss_coverage_count(5, 7373, 7370, 7368, 7371, 7372);\n";
{ // block
cp.code() += "etiss_coverage_count(1, 7405);\n";
cp.code() += "{ // block\n";
cp.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) & 31ULL;\n";
cp.code() += "etiss_coverage_count(7, 7383, 7382, 7380, 7379, 7378, 7376, 7381);\n";
cp.code() += "etiss_int32 sh_val = ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) >> count;\n";
cp.code() += "etiss_coverage_count(8, 7395, 7394, 7391, 7389, 7388, 7386, 7392, 7393);\n";
cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(sh_val);\n";
cp.code() += "etiss_coverage_count(6, 7404, 7400, 7399, 7397, 7403, 7401);\n";
cp.code() += "} // block\n";
} // block
} // conditional
cp.code() += "} // block\n";
} // block
cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
// -----------------------------------------------------------------------------
                cp.getAffectedRegisters().add("instructionPointer", 32);
        }
 
                return true;
        },
        0,
        [] (BitArray & ba, Instruction & instr)
        {
// -----------------------------------------------------------------------------
etiss_uint8 rd = 0;
static BitArrayRange R_rd_0(11, 7);
rd += R_rd_0.read(ba) << 0;
etiss_uint8 rs1 = 0;
static BitArrayRange R_rs1_0(19, 15);
rs1 += R_rs1_0.read(ba) << 0;
etiss_uint8 rs2 = 0;
static BitArrayRange R_rs2_0(24, 20);
rs2 += R_rs2_0.read(ba) << 0;
 
// -----------------------------------------------------------------------------
 
                std::stringstream ss;
// -----------------------------------------------------------------------------
ss << "sraw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
// -----------------------------------------------------------------------------
                return ss.str();
        }
);