ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV64IMACFD_RV64IInstr.cpp
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1 
8 #include "RV64IMACFDArch.h"
9 #include "RV64IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // LWU -------------------------------------------------------------------------
16 static InstructionDefinition lwu_rd_rs1_imm (
17  ISA32_RV64IMACFD,
18  "lwu",
19  (uint32_t) 0x006003,
20  (uint32_t) 0x00707f,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 etiss_uint8 rd = 0;
30 static BitArrayRange R_rd_0(11, 7);
31 rd += R_rd_0.read(ba) << 0;
32 etiss_uint8 rs1 = 0;
33 static BitArrayRange R_rs1_0(19, 15);
34 rs1 += R_rs1_0.read(ba) << 0;
35 etiss_uint16 imm = 0;
36 static BitArrayRange R_imm_0(31, 20);
37 imm += R_imm_0.read(ba) << 0;
38 
39 // -----------------------------------------------------------------------------
40 
41  {
42  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
43 
44  cp.code() = std::string("//LWU\n");
45 
46 // -----------------------------------------------------------------------------
47 cp.code() += "etiss_coverage_count(1, 184);\n";
48 { // block
49 cp.code() += "etiss_coverage_count(1, 1169);\n";
50 cp.code() += "{ // block\n";
51 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
52 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
53 cp.code() += "} // block\n";
54 } // block
55 { // block
56 cp.code() += "etiss_coverage_count(1, 6976);\n";
57 cp.code() += "{ // block\n";
58 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
59 cp.code() += "etiss_coverage_count(7, 6952, 6951, 6947, 6946, 6944, 6950, 6948);\n";
60 cp.code() += "etiss_uint32 mem_val_0;\n";
61 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
62 cp.code() += "if (cpu->exception) { // conditional\n";
63 { // procedure
64 cp.code() += "{ // procedure\n";
65 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
66 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
67 cp.code() += "} // procedure\n";
68 } // procedure
69 cp.code() += "} // conditional\n";
70 cp.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
71 cp.code() += "etiss_coverage_count(4, 6959, 6958, 6956, 6955);\n";
72 cp.code() += "etiss_coverage_count(1, 6960);\n";
73 if ((rd % 32ULL) != 0LL) { // conditional
74 cp.code() += "etiss_coverage_count(5, 6966, 6963, 6961, 6964, 6965);\n";
75 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
76 cp.code() += "etiss_coverage_count(6, 6975, 6971, 6970, 6968, 6974, 6972);\n";
77 } // conditional
78 cp.code() += "} // block\n";
79 } // block
80 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
81 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
82 // -----------------------------------------------------------------------------
83  cp.getAffectedRegisters().add("instructionPointer", 32);
84  }
85  {
86  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
87 
88  cp.code() = std::string("//LWU\n");
89 
90 // -----------------------------------------------------------------------------
91 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
92 // -----------------------------------------------------------------------------
93  }
94 
95  return true;
96  },
97  0,
98  [] (BitArray & ba, Instruction & instr)
99  {
100 // -----------------------------------------------------------------------------
101 etiss_uint8 rd = 0;
102 static BitArrayRange R_rd_0(11, 7);
103 rd += R_rd_0.read(ba) << 0;
104 etiss_uint8 rs1 = 0;
105 static BitArrayRange R_rs1_0(19, 15);
106 rs1 += R_rs1_0.read(ba) << 0;
107 etiss_uint16 imm = 0;
108 static BitArrayRange R_imm_0(31, 20);
109 imm += R_imm_0.read(ba) << 0;
110 
111 // -----------------------------------------------------------------------------
112 
113  std::stringstream ss;
114 // -----------------------------------------------------------------------------
115 ss << "lwu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
116 // -----------------------------------------------------------------------------
117  return ss.str();
118  }
119 );
120 
121 // LD --------------------------------------------------------------------------
122 static InstructionDefinition ld_rd_rs1_imm (
123  ISA32_RV64IMACFD,
124  "ld",
125  (uint32_t) 0x003003,
126  (uint32_t) 0x00707f,
127  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
128  {
129 
130 // -----------------------------------------------------------------------------
131 
132 // -----------------------------------------------------------------------------
133 
134 // -----------------------------------------------------------------------------
135 etiss_uint8 rd = 0;
136 static BitArrayRange R_rd_0(11, 7);
137 rd += R_rd_0.read(ba) << 0;
138 etiss_uint8 rs1 = 0;
139 static BitArrayRange R_rs1_0(19, 15);
140 rs1 += R_rs1_0.read(ba) << 0;
141 etiss_uint16 imm = 0;
142 static BitArrayRange R_imm_0(31, 20);
143 imm += R_imm_0.read(ba) << 0;
144 
145 // -----------------------------------------------------------------------------
146 
147  {
148  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
149 
150  cp.code() = std::string("//LD\n");
151 
152 // -----------------------------------------------------------------------------
153 cp.code() += "etiss_coverage_count(1, 185);\n";
154 { // block
155 cp.code() += "etiss_coverage_count(1, 1169);\n";
156 cp.code() += "{ // block\n";
157 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
158 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
159 cp.code() += "} // block\n";
160 } // block
161 { // block
162 cp.code() += "etiss_coverage_count(1, 7010);\n";
163 cp.code() += "{ // block\n";
164 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
165 cp.code() += "etiss_coverage_count(7, 6986, 6985, 6982, 6981, 6979, 6984, 6983);\n";
166 cp.code() += "etiss_uint64 mem_val_0;\n";
167 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
168 cp.code() += "if (cpu->exception) { // conditional\n";
169 { // procedure
170 cp.code() += "{ // procedure\n";
171 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
172 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
173 cp.code() += "} // procedure\n";
174 } // procedure
175 cp.code() += "} // conditional\n";
176 cp.code() += "etiss_int64 res = (etiss_int64)(mem_val_0);\n";
177 cp.code() += "etiss_coverage_count(4, 6993, 6992, 6990, 6989);\n";
178 cp.code() += "etiss_coverage_count(1, 6994);\n";
179 if ((rd % 32ULL) != 0LL) { // conditional
180 cp.code() += "etiss_coverage_count(5, 7000, 6997, 6995, 6998, 6999);\n";
181 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(res);\n";
182 cp.code() += "etiss_coverage_count(6, 7009, 7005, 7004, 7002, 7008, 7006);\n";
183 } // conditional
184 cp.code() += "} // block\n";
185 } // block
186 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
187 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
188 // -----------------------------------------------------------------------------
189  cp.getAffectedRegisters().add("instructionPointer", 32);
190  }
191  {
192  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
193 
194  cp.code() = std::string("//LD\n");
195 
196 // -----------------------------------------------------------------------------
197 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
198 // -----------------------------------------------------------------------------
199  }
200 
201  return true;
202  },
203  0,
204  [] (BitArray & ba, Instruction & instr)
205  {
206 // -----------------------------------------------------------------------------
207 etiss_uint8 rd = 0;
208 static BitArrayRange R_rd_0(11, 7);
209 rd += R_rd_0.read(ba) << 0;
210 etiss_uint8 rs1 = 0;
211 static BitArrayRange R_rs1_0(19, 15);
212 rs1 += R_rs1_0.read(ba) << 0;
213 etiss_uint16 imm = 0;
214 static BitArrayRange R_imm_0(31, 20);
215 imm += R_imm_0.read(ba) << 0;
216 
217 // -----------------------------------------------------------------------------
218 
219  std::stringstream ss;
220 // -----------------------------------------------------------------------------
221 ss << "ld" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
222 // -----------------------------------------------------------------------------
223  return ss.str();
224  }
225 );
226 
227 // SD --------------------------------------------------------------------------
228 static InstructionDefinition sd_imm_rs1_rs2 (
229  ISA32_RV64IMACFD,
230  "sd",
231  (uint32_t) 0x003023,
232  (uint32_t) 0x00707f,
233  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
234  {
235 
236 // -----------------------------------------------------------------------------
237 
238 // -----------------------------------------------------------------------------
239 
240 // -----------------------------------------------------------------------------
241 etiss_uint16 imm = 0;
242 static BitArrayRange R_imm_0(11, 7);
243 imm += R_imm_0.read(ba) << 0;
244 etiss_uint8 rs1 = 0;
245 static BitArrayRange R_rs1_0(19, 15);
246 rs1 += R_rs1_0.read(ba) << 0;
247 etiss_uint8 rs2 = 0;
248 static BitArrayRange R_rs2_0(24, 20);
249 rs2 += R_rs2_0.read(ba) << 0;
250 static BitArrayRange R_imm_5(31, 25);
251 imm += R_imm_5.read(ba) << 5;
252 
253 // -----------------------------------------------------------------------------
254 
255  {
256  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
257 
258  cp.code() = std::string("//SD\n");
259 
260 // -----------------------------------------------------------------------------
261 cp.code() += "etiss_coverage_count(1, 186);\n";
262 { // block
263 cp.code() += "etiss_coverage_count(1, 1169);\n";
264 cp.code() += "{ // block\n";
265 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
266 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
267 cp.code() += "} // block\n";
268 } // block
269 { // block
270 cp.code() += "etiss_coverage_count(1, 7032);\n";
271 cp.code() += "{ // block\n";
272 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
273 cp.code() += "etiss_coverage_count(7, 7020, 7019, 7016, 7015, 7013, 7018, 7017);\n";
274 cp.code() += "etiss_uint64 mem_val_0;\n";
275 cp.code() += "mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
276 cp.code() += "etiss_coverage_count(7, 7031, 7023, 7022, 7030, 7028, 7027, 7025);\n";
277 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
278 cp.code() += "if (cpu->exception) { // conditional\n";
279 { // procedure
280 cp.code() += "{ // procedure\n";
281 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
282 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
283 cp.code() += "} // procedure\n";
284 } // procedure
285 cp.code() += "} // conditional\n";
286 cp.code() += "} // block\n";
287 } // block
288 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
289 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
290 // -----------------------------------------------------------------------------
291  cp.getAffectedRegisters().add("instructionPointer", 32);
292  }
293  {
294  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
295 
296  cp.code() = std::string("//SD\n");
297 
298 // -----------------------------------------------------------------------------
299 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
300 // -----------------------------------------------------------------------------
301  }
302 
303  return true;
304  },
305  0,
306  [] (BitArray & ba, Instruction & instr)
307  {
308 // -----------------------------------------------------------------------------
309 etiss_uint16 imm = 0;
310 static BitArrayRange R_imm_0(11, 7);
311 imm += R_imm_0.read(ba) << 0;
312 etiss_uint8 rs1 = 0;
313 static BitArrayRange R_rs1_0(19, 15);
314 rs1 += R_rs1_0.read(ba) << 0;
315 etiss_uint8 rs2 = 0;
316 static BitArrayRange R_rs2_0(24, 20);
317 rs2 += R_rs2_0.read(ba) << 0;
318 static BitArrayRange R_imm_5(31, 25);
319 imm += R_imm_5.read(ba) << 5;
320 
321 // -----------------------------------------------------------------------------
322 
323  std::stringstream ss;
324 // -----------------------------------------------------------------------------
325 ss << "sd" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
326 // -----------------------------------------------------------------------------
327  return ss.str();
328  }
329 );
330 
331 // SLLI ------------------------------------------------------------------------
332 static InstructionDefinition slli_rd_rs1_shamt (
333  ISA32_RV64IMACFD,
334  "slli",
335  (uint32_t) 0x001013,
336  (uint32_t) 0xfc00707f,
337  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
338  {
339 
340 // -----------------------------------------------------------------------------
341 
342 // -----------------------------------------------------------------------------
343 
344 // -----------------------------------------------------------------------------
345 etiss_uint8 rd = 0;
346 static BitArrayRange R_rd_0(11, 7);
347 rd += R_rd_0.read(ba) << 0;
348 etiss_uint8 rs1 = 0;
349 static BitArrayRange R_rs1_0(19, 15);
350 rs1 += R_rs1_0.read(ba) << 0;
351 etiss_uint8 shamt = 0;
352 static BitArrayRange R_shamt_0(25, 20);
353 shamt += R_shamt_0.read(ba) << 0;
354 
355 // -----------------------------------------------------------------------------
356 
357  {
358  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
359 
360  cp.code() = std::string("//SLLI\n");
361 
362 // -----------------------------------------------------------------------------
363 cp.code() += "etiss_coverage_count(1, 187);\n";
364 { // block
365 cp.code() += "etiss_coverage_count(1, 1169);\n";
366 cp.code() += "{ // block\n";
367 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
368 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
369 cp.code() += "} // block\n";
370 } // block
371 cp.code() += "etiss_coverage_count(1, 7033);\n";
372 if ((rd % 32ULL) != 0LL) { // conditional
373 cp.code() += "etiss_coverage_count(5, 7039, 7036, 7034, 7037, 7038);\n";
374 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << " + std::to_string(shamt) + "ULL;\n";
375 cp.code() += "etiss_coverage_count(9, 7052, 7044, 7043, 7041, 7051, 7049, 7048, 7046, 7050);\n";
376 } // conditional
377 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
378 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
379 // -----------------------------------------------------------------------------
380  cp.getAffectedRegisters().add("instructionPointer", 32);
381  }
382 
383  return true;
384  },
385  0,
386  [] (BitArray & ba, Instruction & instr)
387  {
388 // -----------------------------------------------------------------------------
389 etiss_uint8 rd = 0;
390 static BitArrayRange R_rd_0(11, 7);
391 rd += R_rd_0.read(ba) << 0;
392 etiss_uint8 rs1 = 0;
393 static BitArrayRange R_rs1_0(19, 15);
394 rs1 += R_rs1_0.read(ba) << 0;
395 etiss_uint8 shamt = 0;
396 static BitArrayRange R_shamt_0(25, 20);
397 shamt += R_shamt_0.read(ba) << 0;
398 
399 // -----------------------------------------------------------------------------
400 
401  std::stringstream ss;
402 // -----------------------------------------------------------------------------
403 ss << "slli" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
404 // -----------------------------------------------------------------------------
405  return ss.str();
406  }
407 );
408 
409 // SRLI ------------------------------------------------------------------------
410 static InstructionDefinition srli_rd_rs1_shamt (
411  ISA32_RV64IMACFD,
412  "srli",
413  (uint32_t) 0x005013,
414  (uint32_t) 0xfc00707f,
415  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
416  {
417 
418 // -----------------------------------------------------------------------------
419 
420 // -----------------------------------------------------------------------------
421 
422 // -----------------------------------------------------------------------------
423 etiss_uint8 rd = 0;
424 static BitArrayRange R_rd_0(11, 7);
425 rd += R_rd_0.read(ba) << 0;
426 etiss_uint8 rs1 = 0;
427 static BitArrayRange R_rs1_0(19, 15);
428 rs1 += R_rs1_0.read(ba) << 0;
429 etiss_uint8 shamt = 0;
430 static BitArrayRange R_shamt_0(25, 20);
431 shamt += R_shamt_0.read(ba) << 0;
432 
433 // -----------------------------------------------------------------------------
434 
435  {
436  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
437 
438  cp.code() = std::string("//SRLI\n");
439 
440 // -----------------------------------------------------------------------------
441 cp.code() += "etiss_coverage_count(1, 188);\n";
442 { // block
443 cp.code() += "etiss_coverage_count(1, 1169);\n";
444 cp.code() += "{ // block\n";
445 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
446 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
447 cp.code() += "} // block\n";
448 } // block
449 cp.code() += "etiss_coverage_count(1, 7053);\n";
450 if ((rd % 32ULL) != 0LL) { // conditional
451 cp.code() += "etiss_coverage_count(5, 7059, 7056, 7054, 7057, 7058);\n";
452 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] >> " + std::to_string(shamt) + "ULL;\n";
453 cp.code() += "etiss_coverage_count(9, 7072, 7064, 7063, 7061, 7071, 7069, 7068, 7066, 7070);\n";
454 } // conditional
455 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
456 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
457 // -----------------------------------------------------------------------------
458  cp.getAffectedRegisters().add("instructionPointer", 32);
459  }
460 
461  return true;
462  },
463  0,
464  [] (BitArray & ba, Instruction & instr)
465  {
466 // -----------------------------------------------------------------------------
467 etiss_uint8 rd = 0;
468 static BitArrayRange R_rd_0(11, 7);
469 rd += R_rd_0.read(ba) << 0;
470 etiss_uint8 rs1 = 0;
471 static BitArrayRange R_rs1_0(19, 15);
472 rs1 += R_rs1_0.read(ba) << 0;
473 etiss_uint8 shamt = 0;
474 static BitArrayRange R_shamt_0(25, 20);
475 shamt += R_shamt_0.read(ba) << 0;
476 
477 // -----------------------------------------------------------------------------
478 
479  std::stringstream ss;
480 // -----------------------------------------------------------------------------
481 ss << "srli" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
482 // -----------------------------------------------------------------------------
483  return ss.str();
484  }
485 );
486 
487 // SRAI ------------------------------------------------------------------------
488 static InstructionDefinition srai_rd_rs1_shamt (
489  ISA32_RV64IMACFD,
490  "srai",
491  (uint32_t) 0x40005013,
492  (uint32_t) 0xfc00707f,
493  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
494  {
495 
496 // -----------------------------------------------------------------------------
497 
498 // -----------------------------------------------------------------------------
499 
500 // -----------------------------------------------------------------------------
501 etiss_uint8 rd = 0;
502 static BitArrayRange R_rd_0(11, 7);
503 rd += R_rd_0.read(ba) << 0;
504 etiss_uint8 rs1 = 0;
505 static BitArrayRange R_rs1_0(19, 15);
506 rs1 += R_rs1_0.read(ba) << 0;
507 etiss_uint8 shamt = 0;
508 static BitArrayRange R_shamt_0(25, 20);
509 shamt += R_shamt_0.read(ba) << 0;
510 
511 // -----------------------------------------------------------------------------
512 
513  {
514  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
515 
516  cp.code() = std::string("//SRAI\n");
517 
518 // -----------------------------------------------------------------------------
519 cp.code() += "etiss_coverage_count(1, 189);\n";
520 { // block
521 cp.code() += "etiss_coverage_count(1, 1169);\n";
522 cp.code() += "{ // block\n";
523 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
524 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
525 cp.code() += "} // block\n";
526 } // block
527 cp.code() += "etiss_coverage_count(1, 7073);\n";
528 if ((rd % 32ULL) != 0LL) { // conditional
529 cp.code() += "etiss_coverage_count(5, 7079, 7076, 7074, 7077, 7078);\n";
530 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) >> " + std::to_string(shamt) + "ULL;\n";
531 cp.code() += "etiss_coverage_count(11, 7094, 7084, 7083, 7081, 7093, 7090, 7089, 7088, 7086, 7091, 7092);\n";
532 } // conditional
533 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
534 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
535 // -----------------------------------------------------------------------------
536  cp.getAffectedRegisters().add("instructionPointer", 32);
537  }
538 
539  return true;
540  },
541  0,
542  [] (BitArray & ba, Instruction & instr)
543  {
544 // -----------------------------------------------------------------------------
545 etiss_uint8 rd = 0;
546 static BitArrayRange R_rd_0(11, 7);
547 rd += R_rd_0.read(ba) << 0;
548 etiss_uint8 rs1 = 0;
549 static BitArrayRange R_rs1_0(19, 15);
550 rs1 += R_rs1_0.read(ba) << 0;
551 etiss_uint8 shamt = 0;
552 static BitArrayRange R_shamt_0(25, 20);
553 shamt += R_shamt_0.read(ba) << 0;
554 
555 // -----------------------------------------------------------------------------
556 
557  std::stringstream ss;
558 // -----------------------------------------------------------------------------
559 ss << "srai" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
560 // -----------------------------------------------------------------------------
561  return ss.str();
562  }
563 );
564 
565 // ADDIW -----------------------------------------------------------------------
566 static InstructionDefinition addiw_rd_rs1_imm (
567  ISA32_RV64IMACFD,
568  "addiw",
569  (uint32_t) 0x00001b,
570  (uint32_t) 0x00707f,
571  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
572  {
573 
574 // -----------------------------------------------------------------------------
575 
576 // -----------------------------------------------------------------------------
577 
578 // -----------------------------------------------------------------------------
579 etiss_uint8 rd = 0;
580 static BitArrayRange R_rd_0(11, 7);
581 rd += R_rd_0.read(ba) << 0;
582 etiss_uint8 rs1 = 0;
583 static BitArrayRange R_rs1_0(19, 15);
584 rs1 += R_rs1_0.read(ba) << 0;
585 etiss_uint16 imm = 0;
586 static BitArrayRange R_imm_0(31, 20);
587 imm += R_imm_0.read(ba) << 0;
588 
589 // -----------------------------------------------------------------------------
590 
591  {
592  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
593 
594  cp.code() = std::string("//ADDIW\n");
595 
596 // -----------------------------------------------------------------------------
597 cp.code() += "etiss_coverage_count(1, 190);\n";
598 { // block
599 cp.code() += "etiss_coverage_count(1, 1169);\n";
600 cp.code() += "{ // block\n";
601 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
602 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
603 cp.code() += "} // block\n";
604 } // block
605 { // block
606 cp.code() += "etiss_coverage_count(1, 7122);\n";
607 cp.code() += "{ // block\n";
608 cp.code() += "etiss_coverage_count(1, 7095);\n";
609 if ((rd % 32ULL) != 0LL) { // conditional
610 cp.code() += "etiss_coverage_count(5, 7101, 7098, 7096, 7099, 7100);\n";
611 { // block
612 cp.code() += "etiss_coverage_count(1, 7121);\n";
613 cp.code() += "{ // block\n";
614 cp.code() += "etiss_int32 res = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
615 cp.code() += "etiss_coverage_count(7, 7111, 7110, 7107, 7106, 7104, 7109, 7108);\n";
616 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res);\n";
617 cp.code() += "etiss_coverage_count(6, 7120, 7116, 7115, 7113, 7119, 7117);\n";
618 cp.code() += "} // block\n";
619 } // block
620 } // conditional
621 cp.code() += "} // block\n";
622 } // block
623 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
624 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
625 // -----------------------------------------------------------------------------
626  cp.getAffectedRegisters().add("instructionPointer", 32);
627  }
628 
629  return true;
630  },
631  0,
632  [] (BitArray & ba, Instruction & instr)
633  {
634 // -----------------------------------------------------------------------------
635 etiss_uint8 rd = 0;
636 static BitArrayRange R_rd_0(11, 7);
637 rd += R_rd_0.read(ba) << 0;
638 etiss_uint8 rs1 = 0;
639 static BitArrayRange R_rs1_0(19, 15);
640 rs1 += R_rs1_0.read(ba) << 0;
641 etiss_uint16 imm = 0;
642 static BitArrayRange R_imm_0(31, 20);
643 imm += R_imm_0.read(ba) << 0;
644 
645 // -----------------------------------------------------------------------------
646 
647  std::stringstream ss;
648 // -----------------------------------------------------------------------------
649 ss << "addiw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
650 // -----------------------------------------------------------------------------
651  return ss.str();
652  }
653 );
654 
655 // SLLIW -----------------------------------------------------------------------
656 static InstructionDefinition slliw_rd_rs1_shamt (
657  ISA32_RV64IMACFD,
658  "slliw",
659  (uint32_t) 0x00101b,
660  (uint32_t) 0xfe00707f,
661  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
662  {
663 
664 // -----------------------------------------------------------------------------
665 
666 // -----------------------------------------------------------------------------
667 
668 // -----------------------------------------------------------------------------
669 etiss_uint8 rd = 0;
670 static BitArrayRange R_rd_0(11, 7);
671 rd += R_rd_0.read(ba) << 0;
672 etiss_uint8 rs1 = 0;
673 static BitArrayRange R_rs1_0(19, 15);
674 rs1 += R_rs1_0.read(ba) << 0;
675 etiss_uint8 shamt = 0;
676 static BitArrayRange R_shamt_0(24, 20);
677 shamt += R_shamt_0.read(ba) << 0;
678 
679 // -----------------------------------------------------------------------------
680 
681  {
682  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
683 
684  cp.code() = std::string("//SLLIW\n");
685 
686 // -----------------------------------------------------------------------------
687 cp.code() += "etiss_coverage_count(1, 191);\n";
688 { // block
689 cp.code() += "etiss_coverage_count(1, 1169);\n";
690 cp.code() += "{ // block\n";
691 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
692 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
693 cp.code() += "} // block\n";
694 } // block
695 { // block
696 cp.code() += "etiss_coverage_count(1, 7153);\n";
697 cp.code() += "{ // block\n";
698 cp.code() += "etiss_coverage_count(1, 7123);\n";
699 if ((rd % 32ULL) != 0LL) { // conditional
700 cp.code() += "etiss_coverage_count(5, 7129, 7126, 7124, 7127, 7128);\n";
701 { // block
702 cp.code() += "etiss_coverage_count(1, 7152);\n";
703 cp.code() += "{ // block\n";
704 cp.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) << " + std::to_string(shamt) + "ULL;\n";
705 cp.code() += "etiss_coverage_count(8, 7141, 7140, 7137, 7135, 7134, 7132, 7138, 7139);\n";
706 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(sh_val));\n";
707 cp.code() += "etiss_coverage_count(7, 7151, 7146, 7145, 7143, 7150, 7148, 7147);\n";
708 cp.code() += "} // block\n";
709 } // block
710 } // conditional
711 cp.code() += "} // block\n";
712 } // block
713 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
714 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
715 // -----------------------------------------------------------------------------
716  cp.getAffectedRegisters().add("instructionPointer", 32);
717  }
718 
719  return true;
720  },
721  0,
722  [] (BitArray & ba, Instruction & instr)
723  {
724 // -----------------------------------------------------------------------------
725 etiss_uint8 rd = 0;
726 static BitArrayRange R_rd_0(11, 7);
727 rd += R_rd_0.read(ba) << 0;
728 etiss_uint8 rs1 = 0;
729 static BitArrayRange R_rs1_0(19, 15);
730 rs1 += R_rs1_0.read(ba) << 0;
731 etiss_uint8 shamt = 0;
732 static BitArrayRange R_shamt_0(24, 20);
733 shamt += R_shamt_0.read(ba) << 0;
734 
735 // -----------------------------------------------------------------------------
736 
737  std::stringstream ss;
738 // -----------------------------------------------------------------------------
739 ss << "slliw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
740 // -----------------------------------------------------------------------------
741  return ss.str();
742  }
743 );
744 
745 // SRLIW -----------------------------------------------------------------------
746 static InstructionDefinition srliw_rd_rs1_shamt (
747  ISA32_RV64IMACFD,
748  "srliw",
749  (uint32_t) 0x00501b,
750  (uint32_t) 0xfe00707f,
751  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
752  {
753 
754 // -----------------------------------------------------------------------------
755 
756 // -----------------------------------------------------------------------------
757 
758 // -----------------------------------------------------------------------------
759 etiss_uint8 rd = 0;
760 static BitArrayRange R_rd_0(11, 7);
761 rd += R_rd_0.read(ba) << 0;
762 etiss_uint8 rs1 = 0;
763 static BitArrayRange R_rs1_0(19, 15);
764 rs1 += R_rs1_0.read(ba) << 0;
765 etiss_uint8 shamt = 0;
766 static BitArrayRange R_shamt_0(24, 20);
767 shamt += R_shamt_0.read(ba) << 0;
768 
769 // -----------------------------------------------------------------------------
770 
771  {
772  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
773 
774  cp.code() = std::string("//SRLIW\n");
775 
776 // -----------------------------------------------------------------------------
777 cp.code() += "etiss_coverage_count(1, 192);\n";
778 { // block
779 cp.code() += "etiss_coverage_count(1, 1169);\n";
780 cp.code() += "{ // block\n";
781 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
782 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
783 cp.code() += "} // block\n";
784 } // block
785 { // block
786 cp.code() += "etiss_coverage_count(1, 7184);\n";
787 cp.code() += "{ // block\n";
788 cp.code() += "etiss_coverage_count(1, 7154);\n";
789 if ((rd % 32ULL) != 0LL) { // conditional
790 cp.code() += "etiss_coverage_count(5, 7160, 7157, 7155, 7158, 7159);\n";
791 { // block
792 cp.code() += "etiss_coverage_count(1, 7183);\n";
793 cp.code() += "{ // block\n";
794 cp.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) >> " + std::to_string(shamt) + "ULL;\n";
795 cp.code() += "etiss_coverage_count(8, 7172, 7171, 7168, 7166, 7165, 7163, 7169, 7170);\n";
796 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(sh_val));\n";
797 cp.code() += "etiss_coverage_count(7, 7182, 7177, 7176, 7174, 7181, 7179, 7178);\n";
798 cp.code() += "} // block\n";
799 } // block
800 } // conditional
801 cp.code() += "} // block\n";
802 } // block
803 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
804 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
805 // -----------------------------------------------------------------------------
806  cp.getAffectedRegisters().add("instructionPointer", 32);
807  }
808 
809  return true;
810  },
811  0,
812  [] (BitArray & ba, Instruction & instr)
813  {
814 // -----------------------------------------------------------------------------
815 etiss_uint8 rd = 0;
816 static BitArrayRange R_rd_0(11, 7);
817 rd += R_rd_0.read(ba) << 0;
818 etiss_uint8 rs1 = 0;
819 static BitArrayRange R_rs1_0(19, 15);
820 rs1 += R_rs1_0.read(ba) << 0;
821 etiss_uint8 shamt = 0;
822 static BitArrayRange R_shamt_0(24, 20);
823 shamt += R_shamt_0.read(ba) << 0;
824 
825 // -----------------------------------------------------------------------------
826 
827  std::stringstream ss;
828 // -----------------------------------------------------------------------------
829 ss << "srliw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
830 // -----------------------------------------------------------------------------
831  return ss.str();
832  }
833 );
834 
835 // SRAIW -----------------------------------------------------------------------
836 static InstructionDefinition sraiw_rd_rs1_shamt (
837  ISA32_RV64IMACFD,
838  "sraiw",
839  (uint32_t) 0x4000501b,
840  (uint32_t) 0xfe00707f,
841  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
842  {
843 
844 // -----------------------------------------------------------------------------
845 
846 // -----------------------------------------------------------------------------
847 
848 // -----------------------------------------------------------------------------
849 etiss_uint8 rd = 0;
850 static BitArrayRange R_rd_0(11, 7);
851 rd += R_rd_0.read(ba) << 0;
852 etiss_uint8 rs1 = 0;
853 static BitArrayRange R_rs1_0(19, 15);
854 rs1 += R_rs1_0.read(ba) << 0;
855 etiss_uint8 shamt = 0;
856 static BitArrayRange R_shamt_0(24, 20);
857 shamt += R_shamt_0.read(ba) << 0;
858 
859 // -----------------------------------------------------------------------------
860 
861  {
862  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
863 
864  cp.code() = std::string("//SRAIW\n");
865 
866 // -----------------------------------------------------------------------------
867 cp.code() += "etiss_coverage_count(1, 193);\n";
868 { // block
869 cp.code() += "etiss_coverage_count(1, 1169);\n";
870 cp.code() += "{ // block\n";
871 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
872 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
873 cp.code() += "} // block\n";
874 } // block
875 { // block
876 cp.code() += "etiss_coverage_count(1, 7214);\n";
877 cp.code() += "{ // block\n";
878 cp.code() += "etiss_coverage_count(1, 7185);\n";
879 if ((rd % 32ULL) != 0LL) { // conditional
880 cp.code() += "etiss_coverage_count(5, 7191, 7188, 7186, 7189, 7190);\n";
881 { // block
882 cp.code() += "etiss_coverage_count(1, 7213);\n";
883 cp.code() += "{ // block\n";
884 cp.code() += "etiss_int32 sh_val = ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) >> " + std::to_string(shamt) + "ULL;\n";
885 cp.code() += "etiss_coverage_count(8, 7203, 7202, 7199, 7197, 7196, 7194, 7200, 7201);\n";
886 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)(sh_val);\n";
887 cp.code() += "etiss_coverage_count(6, 7212, 7208, 7207, 7205, 7211, 7209);\n";
888 cp.code() += "} // block\n";
889 } // block
890 } // conditional
891 cp.code() += "} // block\n";
892 } // block
893 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
894 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
895 // -----------------------------------------------------------------------------
896  cp.getAffectedRegisters().add("instructionPointer", 32);
897  }
898 
899  return true;
900  },
901  0,
902  [] (BitArray & ba, Instruction & instr)
903  {
904 // -----------------------------------------------------------------------------
905 etiss_uint8 rd = 0;
906 static BitArrayRange R_rd_0(11, 7);
907 rd += R_rd_0.read(ba) << 0;
908 etiss_uint8 rs1 = 0;
909 static BitArrayRange R_rs1_0(19, 15);
910 rs1 += R_rs1_0.read(ba) << 0;
911 etiss_uint8 shamt = 0;
912 static BitArrayRange R_shamt_0(24, 20);
913 shamt += R_shamt_0.read(ba) << 0;
914 
915 // -----------------------------------------------------------------------------
916 
917  std::stringstream ss;
918 // -----------------------------------------------------------------------------
919 ss << "sraiw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | shamt=" + std::to_string(shamt) + "]");
920 // -----------------------------------------------------------------------------
921  return ss.str();
922  }
923 );
924 
925 // ADDW ------------------------------------------------------------------------
926 static InstructionDefinition addw_rd_rs1_rs2 (
927  ISA32_RV64IMACFD,
928  "addw",
929  (uint32_t) 0x00003b,
930  (uint32_t) 0xfe00707f,
931  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
932  {
933 
934 // -----------------------------------------------------------------------------
935 
936 // -----------------------------------------------------------------------------
937 
938 // -----------------------------------------------------------------------------
939 etiss_uint8 rd = 0;
940 static BitArrayRange R_rd_0(11, 7);
941 rd += R_rd_0.read(ba) << 0;
942 etiss_uint8 rs1 = 0;
943 static BitArrayRange R_rs1_0(19, 15);
944 rs1 += R_rs1_0.read(ba) << 0;
945 etiss_uint8 rs2 = 0;
946 static BitArrayRange R_rs2_0(24, 20);
947 rs2 += R_rs2_0.read(ba) << 0;
948 
949 // -----------------------------------------------------------------------------
950 
951  {
952  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
953 
954  cp.code() = std::string("//ADDW\n");
955 
956 // -----------------------------------------------------------------------------
957 cp.code() += "etiss_coverage_count(1, 194);\n";
958 { // block
959 cp.code() += "etiss_coverage_count(1, 1169);\n";
960 cp.code() += "{ // block\n";
961 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
962 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
963 cp.code() += "} // block\n";
964 } // block
965 { // block
966 cp.code() += "etiss_coverage_count(1, 7249);\n";
967 cp.code() += "{ // block\n";
968 cp.code() += "etiss_coverage_count(1, 7215);\n";
969 if ((rd % 32ULL) != 0LL) { // conditional
970 cp.code() += "etiss_coverage_count(5, 7221, 7218, 7216, 7219, 7220);\n";
971 { // block
972 cp.code() += "etiss_coverage_count(1, 7248);\n";
973 cp.code() += "{ // block\n";
974 cp.code() += "etiss_int32 res = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) + (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
975 cp.code() += "etiss_coverage_count(10, 7238, 7237, 7229, 7227, 7226, 7224, 7236, 7234, 7233, 7231);\n";
976 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res);\n";
977 cp.code() += "etiss_coverage_count(6, 7247, 7243, 7242, 7240, 7246, 7244);\n";
978 cp.code() += "} // block\n";
979 } // block
980 } // conditional
981 cp.code() += "} // block\n";
982 } // block
983 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
984 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
985 // -----------------------------------------------------------------------------
986  cp.getAffectedRegisters().add("instructionPointer", 32);
987  }
988 
989  return true;
990  },
991  0,
992  [] (BitArray & ba, Instruction & instr)
993  {
994 // -----------------------------------------------------------------------------
995 etiss_uint8 rd = 0;
996 static BitArrayRange R_rd_0(11, 7);
997 rd += R_rd_0.read(ba) << 0;
998 etiss_uint8 rs1 = 0;
999 static BitArrayRange R_rs1_0(19, 15);
1000 rs1 += R_rs1_0.read(ba) << 0;
1001 etiss_uint8 rs2 = 0;
1002 static BitArrayRange R_rs2_0(24, 20);
1003 rs2 += R_rs2_0.read(ba) << 0;
1004 
1005 // -----------------------------------------------------------------------------
1006 
1007  std::stringstream ss;
1008 // -----------------------------------------------------------------------------
1009 ss << "addw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1010 // -----------------------------------------------------------------------------
1011  return ss.str();
1012  }
1013 );
1014 
1015 // SUBW ------------------------------------------------------------------------
1016 static InstructionDefinition subw_rd_rs1_rs2 (
1017  ISA32_RV64IMACFD,
1018  "subw",
1019  (uint32_t) 0x4000003b,
1020  (uint32_t) 0xfe00707f,
1021  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1022  {
1023 
1024 // -----------------------------------------------------------------------------
1025 
1026 // -----------------------------------------------------------------------------
1027 
1028 // -----------------------------------------------------------------------------
1029 etiss_uint8 rd = 0;
1030 static BitArrayRange R_rd_0(11, 7);
1031 rd += R_rd_0.read(ba) << 0;
1032 etiss_uint8 rs1 = 0;
1033 static BitArrayRange R_rs1_0(19, 15);
1034 rs1 += R_rs1_0.read(ba) << 0;
1035 etiss_uint8 rs2 = 0;
1036 static BitArrayRange R_rs2_0(24, 20);
1037 rs2 += R_rs2_0.read(ba) << 0;
1038 
1039 // -----------------------------------------------------------------------------
1040 
1041  {
1042  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1043 
1044  cp.code() = std::string("//SUBW\n");
1045 
1046 // -----------------------------------------------------------------------------
1047 cp.code() += "etiss_coverage_count(1, 195);\n";
1048 { // block
1049 cp.code() += "etiss_coverage_count(1, 1169);\n";
1050 cp.code() += "{ // block\n";
1051 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1052 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1053 cp.code() += "} // block\n";
1054 } // block
1055 { // block
1056 cp.code() += "etiss_coverage_count(1, 7284);\n";
1057 cp.code() += "{ // block\n";
1058 cp.code() += "etiss_coverage_count(1, 7250);\n";
1059 if ((rd % 32ULL) != 0LL) { // conditional
1060 cp.code() += "etiss_coverage_count(5, 7256, 7253, 7251, 7254, 7255);\n";
1061 { // block
1062 cp.code() += "etiss_coverage_count(1, 7283);\n";
1063 cp.code() += "{ // block\n";
1064 cp.code() += "etiss_int32 res = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) - (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
1065 cp.code() += "etiss_coverage_count(10, 7273, 7272, 7264, 7262, 7261, 7259, 7271, 7269, 7268, 7266);\n";
1066 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res);\n";
1067 cp.code() += "etiss_coverage_count(6, 7282, 7278, 7277, 7275, 7281, 7279);\n";
1068 cp.code() += "} // block\n";
1069 } // block
1070 } // conditional
1071 cp.code() += "} // block\n";
1072 } // block
1073 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1074 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1075 // -----------------------------------------------------------------------------
1076  cp.getAffectedRegisters().add("instructionPointer", 32);
1077  }
1078 
1079  return true;
1080  },
1081  0,
1082  [] (BitArray & ba, Instruction & instr)
1083  {
1084 // -----------------------------------------------------------------------------
1085 etiss_uint8 rd = 0;
1086 static BitArrayRange R_rd_0(11, 7);
1087 rd += R_rd_0.read(ba) << 0;
1088 etiss_uint8 rs1 = 0;
1089 static BitArrayRange R_rs1_0(19, 15);
1090 rs1 += R_rs1_0.read(ba) << 0;
1091 etiss_uint8 rs2 = 0;
1092 static BitArrayRange R_rs2_0(24, 20);
1093 rs2 += R_rs2_0.read(ba) << 0;
1094 
1095 // -----------------------------------------------------------------------------
1096 
1097  std::stringstream ss;
1098 // -----------------------------------------------------------------------------
1099 ss << "subw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1100 // -----------------------------------------------------------------------------
1101  return ss.str();
1102  }
1103 );
1104 
1105 // SLLW ------------------------------------------------------------------------
1106 static InstructionDefinition sllw_rd_rs1_rs2 (
1107  ISA32_RV64IMACFD,
1108  "sllw",
1109  (uint32_t) 0x00103b,
1110  (uint32_t) 0xfe00707f,
1111  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1112  {
1113 
1114 // -----------------------------------------------------------------------------
1115 
1116 // -----------------------------------------------------------------------------
1117 
1118 // -----------------------------------------------------------------------------
1119 etiss_uint8 rd = 0;
1120 static BitArrayRange R_rd_0(11, 7);
1121 rd += R_rd_0.read(ba) << 0;
1122 etiss_uint8 rs1 = 0;
1123 static BitArrayRange R_rs1_0(19, 15);
1124 rs1 += R_rs1_0.read(ba) << 0;
1125 etiss_uint8 rs2 = 0;
1126 static BitArrayRange R_rs2_0(24, 20);
1127 rs2 += R_rs2_0.read(ba) << 0;
1128 
1129 // -----------------------------------------------------------------------------
1130 
1131  {
1132  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1133 
1134  cp.code() = std::string("//SLLW\n");
1135 
1136 // -----------------------------------------------------------------------------
1137 cp.code() += "etiss_coverage_count(1, 196);\n";
1138 { // block
1139 cp.code() += "etiss_coverage_count(1, 1169);\n";
1140 cp.code() += "{ // block\n";
1141 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1142 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1143 cp.code() += "} // block\n";
1144 } // block
1145 { // block
1146 cp.code() += "etiss_coverage_count(1, 7325);\n";
1147 cp.code() += "{ // block\n";
1148 cp.code() += "etiss_coverage_count(1, 7285);\n";
1149 if ((rd % 32ULL) != 0LL) { // conditional
1150 cp.code() += "etiss_coverage_count(5, 7291, 7288, 7286, 7289, 7290);\n";
1151 { // block
1152 cp.code() += "etiss_coverage_count(1, 7324);\n";
1153 cp.code() += "{ // block\n";
1154 cp.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) & 31ULL;\n";
1155 cp.code() += "etiss_coverage_count(7, 7301, 7300, 7298, 7297, 7296, 7294, 7299);\n";
1156 cp.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) << count;\n";
1157 cp.code() += "etiss_coverage_count(8, 7313, 7312, 7309, 7307, 7306, 7304, 7310, 7311);\n";
1158 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(sh_val));\n";
1159 cp.code() += "etiss_coverage_count(7, 7323, 7318, 7317, 7315, 7322, 7320, 7319);\n";
1160 cp.code() += "} // block\n";
1161 } // block
1162 } // conditional
1163 cp.code() += "} // block\n";
1164 } // block
1165 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1166 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1167 // -----------------------------------------------------------------------------
1168  cp.getAffectedRegisters().add("instructionPointer", 32);
1169  }
1170 
1171  return true;
1172  },
1173  0,
1174  [] (BitArray & ba, Instruction & instr)
1175  {
1176 // -----------------------------------------------------------------------------
1177 etiss_uint8 rd = 0;
1178 static BitArrayRange R_rd_0(11, 7);
1179 rd += R_rd_0.read(ba) << 0;
1180 etiss_uint8 rs1 = 0;
1181 static BitArrayRange R_rs1_0(19, 15);
1182 rs1 += R_rs1_0.read(ba) << 0;
1183 etiss_uint8 rs2 = 0;
1184 static BitArrayRange R_rs2_0(24, 20);
1185 rs2 += R_rs2_0.read(ba) << 0;
1186 
1187 // -----------------------------------------------------------------------------
1188 
1189  std::stringstream ss;
1190 // -----------------------------------------------------------------------------
1191 ss << "sllw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1192 // -----------------------------------------------------------------------------
1193  return ss.str();
1194  }
1195 );
1196 
1197 // SRLW ------------------------------------------------------------------------
1198 static InstructionDefinition srlw_rd_rs1_rs2 (
1199  ISA32_RV64IMACFD,
1200  "srlw",
1201  (uint32_t) 0x00503b,
1202  (uint32_t) 0xfe00707f,
1203  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1204  {
1205 
1206 // -----------------------------------------------------------------------------
1207 
1208 // -----------------------------------------------------------------------------
1209 
1210 // -----------------------------------------------------------------------------
1211 etiss_uint8 rd = 0;
1212 static BitArrayRange R_rd_0(11, 7);
1213 rd += R_rd_0.read(ba) << 0;
1214 etiss_uint8 rs1 = 0;
1215 static BitArrayRange R_rs1_0(19, 15);
1216 rs1 += R_rs1_0.read(ba) << 0;
1217 etiss_uint8 rs2 = 0;
1218 static BitArrayRange R_rs2_0(24, 20);
1219 rs2 += R_rs2_0.read(ba) << 0;
1220 
1221 // -----------------------------------------------------------------------------
1222 
1223  {
1224  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1225 
1226  cp.code() = std::string("//SRLW\n");
1227 
1228 // -----------------------------------------------------------------------------
1229 cp.code() += "etiss_coverage_count(1, 197);\n";
1230 { // block
1231 cp.code() += "etiss_coverage_count(1, 1169);\n";
1232 cp.code() += "{ // block\n";
1233 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1234 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1235 cp.code() += "} // block\n";
1236 } // block
1237 { // block
1238 cp.code() += "etiss_coverage_count(1, 7366);\n";
1239 cp.code() += "{ // block\n";
1240 cp.code() += "etiss_coverage_count(1, 7326);\n";
1241 if ((rd % 32ULL) != 0LL) { // conditional
1242 cp.code() += "etiss_coverage_count(5, 7332, 7329, 7327, 7330, 7331);\n";
1243 { // block
1244 cp.code() += "etiss_coverage_count(1, 7365);\n";
1245 cp.code() += "{ // block\n";
1246 cp.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) & 31ULL;\n";
1247 cp.code() += "etiss_coverage_count(7, 7342, 7341, 7339, 7338, 7337, 7335, 7340);\n";
1248 cp.code() += "etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) >> count;\n";
1249 cp.code() += "etiss_coverage_count(8, 7354, 7353, 7350, 7348, 7347, 7345, 7351, 7352);\n";
1250 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint64)((etiss_int32)(sh_val));\n";
1251 cp.code() += "etiss_coverage_count(7, 7364, 7359, 7358, 7356, 7363, 7361, 7360);\n";
1252 cp.code() += "} // block\n";
1253 } // block
1254 } // conditional
1255 cp.code() += "} // block\n";
1256 } // block
1257 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1258 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1259 // -----------------------------------------------------------------------------
1260  cp.getAffectedRegisters().add("instructionPointer", 32);
1261  }
1262 
1263  return true;
1264  },
1265  0,
1266  [] (BitArray & ba, Instruction & instr)
1267  {
1268 // -----------------------------------------------------------------------------
1269 etiss_uint8 rd = 0;
1270 static BitArrayRange R_rd_0(11, 7);
1271 rd += R_rd_0.read(ba) << 0;
1272 etiss_uint8 rs1 = 0;
1273 static BitArrayRange R_rs1_0(19, 15);
1274 rs1 += R_rs1_0.read(ba) << 0;
1275 etiss_uint8 rs2 = 0;
1276 static BitArrayRange R_rs2_0(24, 20);
1277 rs2 += R_rs2_0.read(ba) << 0;
1278 
1279 // -----------------------------------------------------------------------------
1280 
1281  std::stringstream ss;
1282 // -----------------------------------------------------------------------------
1283 ss << "srlw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1284 // -----------------------------------------------------------------------------
1285  return ss.str();
1286  }
1287 );
1288 
1289 // SRAW ------------------------------------------------------------------------
1290 static InstructionDefinition sraw_rd_rs1_rs2 (
1291  ISA32_RV64IMACFD,
1292  "sraw",
1293  (uint32_t) 0x4000503b,
1294  (uint32_t) 0xfe00707f,
1295  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1296  {
1297 
1298 // -----------------------------------------------------------------------------
1299 
1300 // -----------------------------------------------------------------------------
1301 
1302 // -----------------------------------------------------------------------------
1303 etiss_uint8 rd = 0;
1304 static BitArrayRange R_rd_0(11, 7);
1305 rd += R_rd_0.read(ba) << 0;
1306 etiss_uint8 rs1 = 0;
1307 static BitArrayRange R_rs1_0(19, 15);
1308 rs1 += R_rs1_0.read(ba) << 0;
1309 etiss_uint8 rs2 = 0;
1310 static BitArrayRange R_rs2_0(24, 20);
1311 rs2 += R_rs2_0.read(ba) << 0;
1312 
1313 // -----------------------------------------------------------------------------
1314 
1315  {
1316  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1317 
1318  cp.code() = std::string("//SRAW\n");
1319 
1320 // -----------------------------------------------------------------------------
1321 cp.code() += "etiss_coverage_count(1, 198);\n";
1322 { // block
1323 cp.code() += "etiss_coverage_count(1, 1169);\n";
1324 cp.code() += "{ // block\n";
1325 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1326 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1327 cp.code() += "} // block\n";
1328 } // block
1329 { // block
1330 cp.code() += "etiss_coverage_count(1, 7406);\n";
1331 cp.code() += "{ // block\n";
1332 cp.code() += "etiss_coverage_count(1, 7367);\n";
1333 if ((rd % 32ULL) != 0LL) { // conditional
1334 cp.code() += "etiss_coverage_count(5, 7373, 7370, 7368, 7371, 7372);\n";
1335 { // block
1336 cp.code() += "etiss_coverage_count(1, 7405);\n";
1337 cp.code() += "{ // block\n";
1338 cp.code() += "etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) & 31ULL;\n";
1339 cp.code() += "etiss_coverage_count(7, 7383, 7382, 7380, 7379, 7378, 7376, 7381);\n";
1340 cp.code() += "etiss_int32 sh_val = ((etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) >> count;\n";
1341 cp.code() += "etiss_coverage_count(8, 7395, 7394, 7391, 7389, 7388, 7386, 7392, 7393);\n";
1342 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(sh_val);\n";
1343 cp.code() += "etiss_coverage_count(6, 7404, 7400, 7399, 7397, 7403, 7401);\n";
1344 cp.code() += "} // block\n";
1345 } // block
1346 } // conditional
1347 cp.code() += "} // block\n";
1348 } // block
1349 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1350 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1351 // -----------------------------------------------------------------------------
1352  cp.getAffectedRegisters().add("instructionPointer", 32);
1353  }
1354 
1355  return true;
1356  },
1357  0,
1358  [] (BitArray & ba, Instruction & instr)
1359  {
1360 // -----------------------------------------------------------------------------
1361 etiss_uint8 rd = 0;
1362 static BitArrayRange R_rd_0(11, 7);
1363 rd += R_rd_0.read(ba) << 0;
1364 etiss_uint8 rs1 = 0;
1365 static BitArrayRange R_rs1_0(19, 15);
1366 rs1 += R_rs1_0.read(ba) << 0;
1367 etiss_uint8 rs2 = 0;
1368 static BitArrayRange R_rs2_0(24, 20);
1369 rs2 += R_rs2_0.read(ba) << 0;
1370 
1371 // -----------------------------------------------------------------------------
1372 
1373  std::stringstream ss;
1374 // -----------------------------------------------------------------------------
1375 ss << "sraw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1376 // -----------------------------------------------------------------------------
1377  return ss.str();
1378  }
1379 );
ISA32_RV64IMACFD
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
addiw_rd_rs1_imm
static InstructionDefinition addiw_rd_rs1_imm(ISA32_RV64IMACFD, "addiw",(uint32_t) 0x00001b,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//ADDIW\n");cp.code()+="etiss_coverage_count(1, 190);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7122);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 7095);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 7101, 7098, 7096, 7099, 7100);\n";{ cp.code()+="etiss_coverage_count(1, 7121);\n";cp.code()+="{ // block\n";cp.code()+="etiss_int32 res = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 7111, 7110, 7107, 7106, 7104, 7109, 7108);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(res);\n";cp.code()+="etiss_coverage_count(6, 7120, 7116, 7115, 7113, 7119, 7117);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "addiw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
addw_rd_rs1_rs2
static InstructionDefinition addw_rd_rs1_rs2(ISA32_RV64IMACFD, "addw",(uint32_t) 0x00003b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//ADDW\n");cp.code()+="etiss_coverage_count(1, 194);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7249);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 7215);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 7221, 7218, 7216, 7219, 7220);\n";{ cp.code()+="etiss_coverage_count(1, 7248);\n";cp.code()+="{ // block\n";cp.code()+="etiss_int32 res = (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) + (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(10, 7238, 7237, 7229, 7227, 7226, 7224, 7236, 7234, 7233, 7231);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(res);\n";cp.code()+="etiss_coverage_count(6, 7247, 7243, 7242, 7240, 7246, 7244);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "addw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
lwu_rd_rs1_imm
static InstructionDefinition lwu_rd_rs1_imm(ISA32_RV64IMACFD, "lwu",(uint32_t) 0x006003,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//LWU\n");cp.code()+="etiss_coverage_count(1, 184);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6976);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 6952, 6951, 6947, 6946, 6944, 6950, 6948);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 6959, 6958, 6956, 6955);\n";cp.code()+="etiss_coverage_count(1, 6960);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 6966, 6963, 6961, 6964, 6965);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 6975, 6971, 6970, 6968, 6974, 6972);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//LWU\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "lwu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
sd_imm_rs1_rs2
static InstructionDefinition sd_imm_rs1_rs2(ISA32_RV64IMACFD, "sd",(uint32_t) 0x003023,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SD\n");cp.code()+="etiss_coverage_count(1, 186);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7032);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 7020, 7019, 7016, 7015, 7013, 7018, 7017);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_uint64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(7, 7031, 7023, 7022, 7030, 7028, 7027, 7025);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//SD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "sd"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
ld_rd_rs1_imm
static InstructionDefinition ld_rd_rs1_imm(ISA32_RV64IMACFD, "ld",(uint32_t) 0x003003,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//LD\n");cp.code()+="etiss_coverage_count(1, 185);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7010);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 6986, 6985, 6982, 6981, 6979, 6984, 6983);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res = (etiss_int64)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 6993, 6992, 6990, 6989);\n";cp.code()+="etiss_coverage_count(1, 6994);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 7000, 6997, 6995, 6998, 6999);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 7009, 7005, 7004, 7002, 7008, 7006);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//LD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "ld"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
srai_rd_rs1_shamt
static InstructionDefinition srai_rd_rs1_shamt(ISA32_RV64IMACFD, "srai",(uint32_t) 0x40005013,(uint32_t) 0xfc00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(25, 20);shamt+=R_shamt_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRAI\n");cp.code()+="etiss_coverage_count(1, 189);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 7073);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 7079, 7076, 7074, 7077, 7078);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL])) >> "+std::to_string(shamt)+"ULL;\n";cp.code()+="etiss_coverage_count(11, 7094, 7084, 7083, 7081, 7093, 7090, 7089, 7088, 7086, 7091, 7092);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(25, 20);shamt+=R_shamt_0.read(ba)<< 0;std::stringstream ss;ss<< "srai"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | shamt="+std::to_string(shamt)+"]");return ss.str();})
subw_rd_rs1_rs2
static InstructionDefinition subw_rd_rs1_rs2(ISA32_RV64IMACFD, "subw",(uint32_t) 0x4000003b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SUBW\n");cp.code()+="etiss_coverage_count(1, 195);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7284);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 7250);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 7256, 7253, 7251, 7254, 7255);\n";{ cp.code()+="etiss_coverage_count(1, 7283);\n";cp.code()+="{ // block\n";cp.code()+="etiss_int32 res = (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) - (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(10, 7273, 7272, 7264, 7262, 7261, 7259, 7271, 7269, 7268, 7266);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(res);\n";cp.code()+="etiss_coverage_count(6, 7282, 7278, 7277, 7275, 7281, 7279);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "subw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
sllw_rd_rs1_rs2
static InstructionDefinition sllw_rd_rs1_rs2(ISA32_RV64IMACFD, "sllw",(uint32_t) 0x00103b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SLLW\n");cp.code()+="etiss_coverage_count(1, 196);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7325);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 7285);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 7291, 7288, 7286, 7289, 7290);\n";{ cp.code()+="etiss_coverage_count(1, 7324);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) & 31ULL;\n";cp.code()+="etiss_coverage_count(7, 7301, 7300, 7298, 7297, 7296, 7294, 7299);\n";cp.code()+="etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL])) << count;\n";cp.code()+="etiss_coverage_count(8, 7313, 7312, 7309, 7307, 7306, 7304, 7310, 7311);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)((etiss_int32)(sh_val));\n";cp.code()+="etiss_coverage_count(7, 7323, 7318, 7317, 7315, 7322, 7320, 7319);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "sllw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
sraw_rd_rs1_rs2
static InstructionDefinition sraw_rd_rs1_rs2(ISA32_RV64IMACFD, "sraw",(uint32_t) 0x4000503b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRAW\n");cp.code()+="etiss_coverage_count(1, 198);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7406);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 7367);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 7373, 7370, 7368, 7371, 7372);\n";{ cp.code()+="etiss_coverage_count(1, 7405);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) & 31ULL;\n";cp.code()+="etiss_coverage_count(7, 7383, 7382, 7380, 7379, 7378, 7376, 7381);\n";cp.code()+="etiss_int32 sh_val = ((etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL])) >> count;\n";cp.code()+="etiss_coverage_count(8, 7395, 7394, 7391, 7389, 7388, 7386, 7392, 7393);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(sh_val);\n";cp.code()+="etiss_coverage_count(6, 7404, 7400, 7399, 7397, 7403, 7401);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "sraw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
srliw_rd_rs1_shamt
static InstructionDefinition srliw_rd_rs1_shamt(ISA32_RV64IMACFD, "srliw",(uint32_t) 0x00501b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRLIW\n");cp.code()+="etiss_coverage_count(1, 192);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7184);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 7154);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 7160, 7157, 7155, 7158, 7159);\n";{ cp.code()+="etiss_coverage_count(1, 7183);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL])) >> "+std::to_string(shamt)+"ULL;\n";cp.code()+="etiss_coverage_count(8, 7172, 7171, 7168, 7166, 7165, 7163, 7169, 7170);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)((etiss_int32)(sh_val));\n";cp.code()+="etiss_coverage_count(7, 7182, 7177, 7176, 7174, 7181, 7179, 7178);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;std::stringstream ss;ss<< "srliw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | shamt="+std::to_string(shamt)+"]");return ss.str();})
slliw_rd_rs1_shamt
static InstructionDefinition slliw_rd_rs1_shamt(ISA32_RV64IMACFD, "slliw",(uint32_t) 0x00101b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SLLIW\n");cp.code()+="etiss_coverage_count(1, 191);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7153);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 7123);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 7129, 7126, 7124, 7127, 7128);\n";{ cp.code()+="etiss_coverage_count(1, 7152);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL])) << "+std::to_string(shamt)+"ULL;\n";cp.code()+="etiss_coverage_count(8, 7141, 7140, 7137, 7135, 7134, 7132, 7138, 7139);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)((etiss_int32)(sh_val));\n";cp.code()+="etiss_coverage_count(7, 7151, 7146, 7145, 7143, 7150, 7148, 7147);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;std::stringstream ss;ss<< "slliw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | shamt="+std::to_string(shamt)+"]");return ss.str();})
slli_rd_rs1_shamt
static InstructionDefinition slli_rd_rs1_shamt(ISA32_RV64IMACFD, "slli",(uint32_t) 0x001013,(uint32_t) 0xfc00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(25, 20);shamt+=R_shamt_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SLLI\n");cp.code()+="etiss_coverage_count(1, 187);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 7033);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 7039, 7036, 7034, 7037, 7038);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] << "+std::to_string(shamt)+"ULL;\n";cp.code()+="etiss_coverage_count(9, 7052, 7044, 7043, 7041, 7051, 7049, 7048, 7046, 7050);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(25, 20);shamt+=R_shamt_0.read(ba)<< 0;std::stringstream ss;ss<< "slli"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | shamt="+std::to_string(shamt)+"]");return ss.str();})
srli_rd_rs1_shamt
static InstructionDefinition srli_rd_rs1_shamt(ISA32_RV64IMACFD, "srli",(uint32_t) 0x005013,(uint32_t) 0xfc00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(25, 20);shamt+=R_shamt_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRLI\n");cp.code()+="etiss_coverage_count(1, 188);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 7053);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 7059, 7056, 7054, 7057, 7058);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] >> "+std::to_string(shamt)+"ULL;\n";cp.code()+="etiss_coverage_count(9, 7072, 7064, 7063, 7061, 7071, 7069, 7068, 7066, 7070);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(25, 20);shamt+=R_shamt_0.read(ba)<< 0;std::stringstream ss;ss<< "srli"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | shamt="+std::to_string(shamt)+"]");return ss.str();})
sraiw_rd_rs1_shamt
static InstructionDefinition sraiw_rd_rs1_shamt(ISA32_RV64IMACFD, "sraiw",(uint32_t) 0x4000501b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRAIW\n");cp.code()+="etiss_coverage_count(1, 193);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7214);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 7185);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 7191, 7188, 7186, 7189, 7190);\n";{ cp.code()+="etiss_coverage_count(1, 7213);\n";cp.code()+="{ // block\n";cp.code()+="etiss_int32 sh_val = ((etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL])) >> "+std::to_string(shamt)+"ULL;\n";cp.code()+="etiss_coverage_count(8, 7203, 7202, 7199, 7197, 7196, 7194, 7200, 7201);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)(sh_val);\n";cp.code()+="etiss_coverage_count(6, 7212, 7208, 7207, 7205, 7211, 7209);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(24, 20);shamt+=R_shamt_0.read(ba)<< 0;std::stringstream ss;ss<< "sraiw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | shamt="+std::to_string(shamt)+"]");return ss.str();})
srlw_rd_rs1_rs2
static InstructionDefinition srlw_rd_rs1_rs2(ISA32_RV64IMACFD, "srlw",(uint32_t) 0x00503b,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SRLW\n");cp.code()+="etiss_coverage_count(1, 197);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7366);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 7326);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 7332, 7329, 7327, 7330, 7331);\n";{ cp.code()+="etiss_coverage_count(1, 7365);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 count = (etiss_uint64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) & 31ULL;\n";cp.code()+="etiss_coverage_count(7, 7342, 7341, 7339, 7338, 7337, 7335, 7340);\n";cp.code()+="etiss_uint32 sh_val = ((etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL])) >> count;\n";cp.code()+="etiss_coverage_count(8, 7354, 7353, 7350, 7348, 7347, 7345, 7351, 7352);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint64)((etiss_int32)(sh_val));\n";cp.code()+="etiss_coverage_count(7, 7364, 7359, 7358, 7356, 7363, 7361, 7360);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "srlw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
uint32_t
static __inline__ uint32_t
Definition: arm_cde.h:25
etiss_int16
int16_t etiss_int16
Definition: types.h:89
etiss_uint8
uint8_t etiss_uint8
Definition: types.h:87
etiss_uint16
uint16_t etiss_uint16
Definition: types.h:90
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:386
etiss::CodePart::APPENDEDRETURNINGREQUIRED
@ APPENDEDRETURNINGREQUIRED
Definition: CodePart.h:402
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition: Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition: Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
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