ETISS 0.11.2
ExtendableTranslatingInstructionSetSimulator(version0.11.2)
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RV64IMACFD_RV64DInstr.cpp
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1// clang-format off
9#include "RV64IMACFDArch.h"
10#include "RV64IMACFDFuncs.h"
11
12using namespace etiss;
13using namespace etiss::instr;
14
15// FCVT_L_D --------------------------------------------------------------------
16static InstructionDefinition fcvt_l_d_rd_rm_rs1 (
17 ISA32_RV64IMACFD,
18 "fcvt_l_d",
19 (uint32_t) 0xc2200053,
20 (uint32_t) 0xfff0007f,
21 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22 {
23
24// -----------------------------------------------------------------------------
25
26// -----------------------------------------------------------------------------
27
28// -----------------------------------------------------------------------------
29// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
30etiss_uint8 rd = 0;
31static BitArrayRange R_rd_0(11, 7);
32rd += R_rd_0.read(ba) << 0;
33etiss_uint8 rm = 0;
34static BitArrayRange R_rm_0(14, 12);
35rm += R_rm_0.read(ba) << 0;
36etiss_uint8 rs1 = 0;
37static BitArrayRange R_rs1_0(19, 15);
38rs1 += R_rs1_0.read(ba) << 0;
39
40// NOLINTEND(clang-diagnostic-unused-but-set-variable)
41// -----------------------------------------------------------------------------
42
43 {
44 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
45
46 cp.code() = std::string("//FCVT_L_D\n");
47
48// -----------------------------------------------------------------------------
49cp.code() += "etiss_coverage_count(1, 218);\n";
50{ // block
51cp.code() += "etiss_coverage_count(1, 1169);\n";
52cp.code() += "{ // block\n";
53cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
54cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
55cp.code() += "} // block\n";
56} // block
57{ // block
58cp.code() += "etiss_coverage_count(1, 8244);\n";
59cp.code() += "{ // block\n";
60cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = fcvt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), 0LL, " + std::to_string(rm) + "ULL);\n";
61cp.code() += "etiss_coverage_count(10, 8228, 8219, 8218, 8216, 8227, 8224, 8222, 8221, 8225, 8226);\n";
62cp.code() += "etiss_uint32 flags = fget_flags();\n";
63cp.code() += "etiss_coverage_count(2, 8231, 8230);\n";
64cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
65cp.code() += "etiss_coverage_count(9, 8243, 8232, 8242, 8236, 8233, 8237, 8240, 8238, 8241);\n";
66cp.code() += "} // block\n";
67} // block
68cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
69cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
70// -----------------------------------------------------------------------------
71 cp.getAffectedRegisters().add("instructionPointer", 32);
72 }
73
74 return true;
75 },
76 0,
77 [] (BitArray & ba, Instruction & instr)
78 {
79// -----------------------------------------------------------------------------
80etiss_uint8 rd = 0;
81static BitArrayRange R_rd_0(11, 7);
82rd += R_rd_0.read(ba) << 0;
83etiss_uint8 rm = 0;
84static BitArrayRange R_rm_0(14, 12);
85rm += R_rm_0.read(ba) << 0;
86etiss_uint8 rs1 = 0;
87static BitArrayRange R_rs1_0(19, 15);
88rs1 += R_rs1_0.read(ba) << 0;
89
90// -----------------------------------------------------------------------------
91
92 std::stringstream ss;
93// -----------------------------------------------------------------------------
94ss << "fcvt_l_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
95// -----------------------------------------------------------------------------
96 return ss.str();
97 }
98);
99
100// FCVT_LU_D -------------------------------------------------------------------
101static InstructionDefinition fcvt_lu_d_rd_rm_rs1 (
102 ISA32_RV64IMACFD,
103 "fcvt_lu_d",
104 (uint32_t) 0xc2300053,
105 (uint32_t) 0xfff0007f,
106 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
107 {
108
109// -----------------------------------------------------------------------------
110
111// -----------------------------------------------------------------------------
112
113// -----------------------------------------------------------------------------
114// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
115etiss_uint8 rd = 0;
116static BitArrayRange R_rd_0(11, 7);
117rd += R_rd_0.read(ba) << 0;
118etiss_uint8 rm = 0;
119static BitArrayRange R_rm_0(14, 12);
120rm += R_rm_0.read(ba) << 0;
121etiss_uint8 rs1 = 0;
122static BitArrayRange R_rs1_0(19, 15);
123rs1 += R_rs1_0.read(ba) << 0;
124
125// NOLINTEND(clang-diagnostic-unused-but-set-variable)
126// -----------------------------------------------------------------------------
127
128 {
129 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
130
131 cp.code() = std::string("//FCVT_LU_D\n");
132
133// -----------------------------------------------------------------------------
134cp.code() += "etiss_coverage_count(1, 219);\n";
135{ // block
136cp.code() += "etiss_coverage_count(1, 1169);\n";
137cp.code() += "{ // block\n";
138cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
139cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
140cp.code() += "} // block\n";
141} // block
142{ // block
143cp.code() += "etiss_coverage_count(1, 8274);\n";
144cp.code() += "{ // block\n";
145cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = fcvt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), 1ULL, " + std::to_string(rm) + "ULL);\n";
146cp.code() += "etiss_coverage_count(10, 8258, 8249, 8248, 8246, 8257, 8254, 8252, 8251, 8255, 8256);\n";
147cp.code() += "etiss_uint32 flags = fget_flags();\n";
148cp.code() += "etiss_coverage_count(2, 8261, 8260);\n";
149cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
150cp.code() += "etiss_coverage_count(9, 8273, 8262, 8272, 8266, 8263, 8267, 8270, 8268, 8271);\n";
151cp.code() += "} // block\n";
152} // block
153cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
154cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
155// -----------------------------------------------------------------------------
156 cp.getAffectedRegisters().add("instructionPointer", 32);
157 }
158
159 return true;
160 },
161 0,
162 [] (BitArray & ba, Instruction & instr)
163 {
164// -----------------------------------------------------------------------------
165etiss_uint8 rd = 0;
166static BitArrayRange R_rd_0(11, 7);
167rd += R_rd_0.read(ba) << 0;
168etiss_uint8 rm = 0;
169static BitArrayRange R_rm_0(14, 12);
170rm += R_rm_0.read(ba) << 0;
171etiss_uint8 rs1 = 0;
172static BitArrayRange R_rs1_0(19, 15);
173rs1 += R_rs1_0.read(ba) << 0;
174
175// -----------------------------------------------------------------------------
176
177 std::stringstream ss;
178// -----------------------------------------------------------------------------
179ss << "fcvt_lu_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
180// -----------------------------------------------------------------------------
181 return ss.str();
182 }
183);
184
185// FCVT_D_L --------------------------------------------------------------------
186static InstructionDefinition fcvt_d_l_rd_rm_rs1 (
187 ISA32_RV64IMACFD,
188 "fcvt_d_l",
189 (uint32_t) 0xd2200053,
190 (uint32_t) 0xfff0007f,
191 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
192 {
193
194// -----------------------------------------------------------------------------
195
196// -----------------------------------------------------------------------------
197
198// -----------------------------------------------------------------------------
199// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
200etiss_uint8 rd = 0;
201static BitArrayRange R_rd_0(11, 7);
202rd += R_rd_0.read(ba) << 0;
203etiss_uint8 rm = 0;
204static BitArrayRange R_rm_0(14, 12);
205rm += R_rm_0.read(ba) << 0;
206etiss_uint8 rs1 = 0;
207static BitArrayRange R_rs1_0(19, 15);
208rs1 += R_rs1_0.read(ba) << 0;
209
210// NOLINTEND(clang-diagnostic-unused-but-set-variable)
211// -----------------------------------------------------------------------------
212
213 {
214 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
215
216 cp.code() = std::string("//FCVT_D_L\n");
217
218// -----------------------------------------------------------------------------
219cp.code() += "etiss_coverage_count(1, 220);\n";
220{ // block
221cp.code() += "etiss_coverage_count(1, 1169);\n";
222cp.code() += "{ // block\n";
223cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
224cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
225cp.code() += "} // block\n";
226} // block
227{ // block
228cp.code() += "etiss_coverage_count(1, 8306);\n";
229cp.code() += "{ // block\n";
230cp.code() += "etiss_uint64 res = fcvt_d(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL], 2ULL, " + std::to_string(rm) + "ULL);\n";
231cp.code() += "etiss_coverage_count(7, 8284, 8283, 8280, 8279, 8277, 8281, 8282);\n";
232cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
233cp.code() += "etiss_coverage_count(4, 8293, 8291, 8290, 8292);\n";
234cp.code() += "} // block\n";
235} // block
236cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
237cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
238// -----------------------------------------------------------------------------
239 cp.getAffectedRegisters().add("instructionPointer", 32);
240 }
241
242 return true;
243 },
244 0,
245 [] (BitArray & ba, Instruction & instr)
246 {
247// -----------------------------------------------------------------------------
248etiss_uint8 rd = 0;
249static BitArrayRange R_rd_0(11, 7);
250rd += R_rd_0.read(ba) << 0;
251etiss_uint8 rm = 0;
252static BitArrayRange R_rm_0(14, 12);
253rm += R_rm_0.read(ba) << 0;
254etiss_uint8 rs1 = 0;
255static BitArrayRange R_rs1_0(19, 15);
256rs1 += R_rs1_0.read(ba) << 0;
257
258// -----------------------------------------------------------------------------
259
260 std::stringstream ss;
261// -----------------------------------------------------------------------------
262ss << "fcvt_d_l" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
263// -----------------------------------------------------------------------------
264 return ss.str();
265 }
266);
267
268// FCVT_D_LU -------------------------------------------------------------------
269static InstructionDefinition fcvt_d_lu_rd_rm_rs1 (
270 ISA32_RV64IMACFD,
271 "fcvt_d_lu",
272 (uint32_t) 0xd2300053,
273 (uint32_t) 0xfff0007f,
274 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
275 {
276
277// -----------------------------------------------------------------------------
278
279// -----------------------------------------------------------------------------
280
281// -----------------------------------------------------------------------------
282// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
283etiss_uint8 rd = 0;
284static BitArrayRange R_rd_0(11, 7);
285rd += R_rd_0.read(ba) << 0;
286etiss_uint8 rm = 0;
287static BitArrayRange R_rm_0(14, 12);
288rm += R_rm_0.read(ba) << 0;
289etiss_uint8 rs1 = 0;
290static BitArrayRange R_rs1_0(19, 15);
291rs1 += R_rs1_0.read(ba) << 0;
292
293// NOLINTEND(clang-diagnostic-unused-but-set-variable)
294// -----------------------------------------------------------------------------
295
296 {
297 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
298
299 cp.code() = std::string("//FCVT_D_LU\n");
300
301// -----------------------------------------------------------------------------
302cp.code() += "etiss_coverage_count(1, 221);\n";
303{ // block
304cp.code() += "etiss_coverage_count(1, 1169);\n";
305cp.code() += "{ // block\n";
306cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
307cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
308cp.code() += "} // block\n";
309} // block
310{ // block
311cp.code() += "etiss_coverage_count(1, 8338);\n";
312cp.code() += "{ // block\n";
313cp.code() += "etiss_uint64 res = fcvt_d(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL], 3ULL, " + std::to_string(rm) + "ULL);\n";
314cp.code() += "etiss_coverage_count(7, 8316, 8315, 8312, 8311, 8309, 8313, 8314);\n";
315cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
316cp.code() += "etiss_coverage_count(4, 8325, 8323, 8322, 8324);\n";
317cp.code() += "} // block\n";
318} // block
319cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
320cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
321// -----------------------------------------------------------------------------
322 cp.getAffectedRegisters().add("instructionPointer", 32);
323 }
324
325 return true;
326 },
327 0,
328 [] (BitArray & ba, Instruction & instr)
329 {
330// -----------------------------------------------------------------------------
331etiss_uint8 rd = 0;
332static BitArrayRange R_rd_0(11, 7);
333rd += R_rd_0.read(ba) << 0;
334etiss_uint8 rm = 0;
335static BitArrayRange R_rm_0(14, 12);
336rm += R_rm_0.read(ba) << 0;
337etiss_uint8 rs1 = 0;
338static BitArrayRange R_rs1_0(19, 15);
339rs1 += R_rs1_0.read(ba) << 0;
340
341// -----------------------------------------------------------------------------
342
343 std::stringstream ss;
344// -----------------------------------------------------------------------------
345ss << "fcvt_d_lu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
346// -----------------------------------------------------------------------------
347 return ss.str();
348 }
349);
350
351// FMV_X_D ---------------------------------------------------------------------
352static InstructionDefinition fmv_x_d_rd_rs1 (
353 ISA32_RV64IMACFD,
354 "fmv_x_d",
355 (uint32_t) 0xe2000053,
356 (uint32_t) 0xfff0707f,
357 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
358 {
359
360// -----------------------------------------------------------------------------
361
362// -----------------------------------------------------------------------------
363
364// -----------------------------------------------------------------------------
365// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
366etiss_uint8 rd = 0;
367static BitArrayRange R_rd_0(11, 7);
368rd += R_rd_0.read(ba) << 0;
369etiss_uint8 rs1 = 0;
370static BitArrayRange R_rs1_0(19, 15);
371rs1 += R_rs1_0.read(ba) << 0;
372
373// NOLINTEND(clang-diagnostic-unused-but-set-variable)
374// -----------------------------------------------------------------------------
375
376 {
377 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
378
379 cp.code() = std::string("//FMV_X_D\n");
380
381// -----------------------------------------------------------------------------
382cp.code() += "etiss_coverage_count(1, 222);\n";
383{ // block
384cp.code() += "etiss_coverage_count(1, 1169);\n";
385cp.code() += "{ // block\n";
386cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
387cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
388cp.code() += "} // block\n";
389} // block
390{ // block
391cp.code() += "etiss_coverage_count(1, 8348);\n";
392cp.code() += "{ // block\n";
393cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL];\n";
394cp.code() += "etiss_coverage_count(6, 8347, 8343, 8342, 8340, 8346, 8345);\n";
395cp.code() += "} // block\n";
396} // block
397cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
398cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
399// -----------------------------------------------------------------------------
400 cp.getAffectedRegisters().add("instructionPointer", 32);
401 }
402
403 return true;
404 },
405 0,
406 [] (BitArray & ba, Instruction & instr)
407 {
408// -----------------------------------------------------------------------------
409etiss_uint8 rd = 0;
410static BitArrayRange R_rd_0(11, 7);
411rd += R_rd_0.read(ba) << 0;
412etiss_uint8 rs1 = 0;
413static BitArrayRange R_rs1_0(19, 15);
414rs1 += R_rs1_0.read(ba) << 0;
415
416// -----------------------------------------------------------------------------
417
418 std::stringstream ss;
419// -----------------------------------------------------------------------------
420ss << "fmv_x_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + "]");
421// -----------------------------------------------------------------------------
422 return ss.str();
423 }
424);
425
426// FMV_D_X ---------------------------------------------------------------------
427static InstructionDefinition fmv_d_x_rd_rs1 (
428 ISA32_RV64IMACFD,
429 "fmv_d_x",
430 (uint32_t) 0xf2000053,
431 (uint32_t) 0xfff0707f,
432 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
433 {
434
435// -----------------------------------------------------------------------------
436
437// -----------------------------------------------------------------------------
438
439// -----------------------------------------------------------------------------
440// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
441etiss_uint8 rd = 0;
442static BitArrayRange R_rd_0(11, 7);
443rd += R_rd_0.read(ba) << 0;
444etiss_uint8 rs1 = 0;
445static BitArrayRange R_rs1_0(19, 15);
446rs1 += R_rs1_0.read(ba) << 0;
447
448// NOLINTEND(clang-diagnostic-unused-but-set-variable)
449// -----------------------------------------------------------------------------
450
451 {
452 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
453
454 cp.code() = std::string("//FMV_D_X\n");
455
456// -----------------------------------------------------------------------------
457cp.code() += "etiss_coverage_count(1, 223);\n";
458{ // block
459cp.code() += "etiss_coverage_count(1, 1169);\n";
460cp.code() += "{ // block\n";
461cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
462cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
463cp.code() += "} // block\n";
464} // block
465{ // block
466cp.code() += "etiss_coverage_count(1, 8358);\n";
467cp.code() += "{ // block\n";
468cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
469cp.code() += "etiss_coverage_count(6, 8357, 8351, 8350, 8356, 8355, 8353);\n";
470cp.code() += "} // block\n";
471} // block
472cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
473cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
474// -----------------------------------------------------------------------------
475 cp.getAffectedRegisters().add("instructionPointer", 32);
476 }
477
478 return true;
479 },
480 0,
481 [] (BitArray & ba, Instruction & instr)
482 {
483// -----------------------------------------------------------------------------
484etiss_uint8 rd = 0;
485static BitArrayRange R_rd_0(11, 7);
486rd += R_rd_0.read(ba) << 0;
487etiss_uint8 rs1 = 0;
488static BitArrayRange R_rs1_0(19, 15);
489rs1 += R_rs1_0.read(ba) << 0;
490
491// -----------------------------------------------------------------------------
492
493 std::stringstream ss;
494// -----------------------------------------------------------------------------
495ss << "fmv_d_x" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + "]");
496// -----------------------------------------------------------------------------
497 return ss.str();
498 }
499);
500// clang-format on
ISA32_RV64IMACFD
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
fcvt_l_d_rd_rm_rs1
static InstructionDefinition fcvt_l_d_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_l_d",(uint32_t) 0xc2200053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_L_D\n");cp.code()+="etiss_coverage_count(1, 218);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8244);\n";cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = fcvt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), 0LL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(10, 8228, 8219, 8218, 8216, 8227, 8224, 8222, 8221, 8225, 8226);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 8231, 8230);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 8243, 8232, 8242, 8236, 8233, 8237, 8240, 8238, 8241);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_l_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fcvt_lu_d_rd_rm_rs1
static InstructionDefinition fcvt_lu_d_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_lu_d",(uint32_t) 0xc2300053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_LU_D\n");cp.code()+="etiss_coverage_count(1, 219);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8274);\n";cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = fcvt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), 1ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(10, 8258, 8249, 8248, 8246, 8257, 8254, 8252, 8251, 8255, 8256);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 8261, 8260);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 8273, 8262, 8272, 8266, 8263, 8267, 8270, 8268, 8271);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_lu_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fcvt_d_l_rd_rm_rs1
static InstructionDefinition fcvt_d_l_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_d_l",(uint32_t) 0xd2200053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_D_L\n");cp.code()+="etiss_coverage_count(1, 220);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8306);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fcvt_d(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL], 2ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(7, 8284, 8283, 8280, 8279, 8277, 8281, 8282);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 8293, 8291, 8290, 8292);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_d_l"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fmv_d_x_rd_rs1
static InstructionDefinition fmv_d_x_rd_rs1(ISA32_RV64IMACFD, "fmv_d_x",(uint32_t) 0xf2000053,(uint32_t) 0xfff0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMV_D_X\n");cp.code()+="etiss_coverage_count(1, 223);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8358);\n";cp.code()+="{ // block\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(6, 8357, 8351, 8350, 8356, 8355, 8353);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fmv_d_x"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fmv_x_d_rd_rs1
static InstructionDefinition fmv_x_d_rd_rs1(ISA32_RV64IMACFD, "fmv_x_d",(uint32_t) 0xe2000053,(uint32_t) 0xfff0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMV_X_D\n");cp.code()+="etiss_coverage_count(1, 222);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8348);\n";cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = ((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL];\n";cp.code()+="etiss_coverage_count(6, 8347, 8343, 8342, 8340, 8346, 8345);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fmv_x_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fcvt_d_lu_rd_rm_rs1
static InstructionDefinition fcvt_d_lu_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_d_lu",(uint32_t) 0xd2300053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_D_LU\n");cp.code()+="etiss_coverage_count(1, 221);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8338);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fcvt_d(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL], 3ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(7, 8316, 8315, 8312, 8311, 8309, 8313, 8314);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 8325, 8323, 8322, 8324);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_d_lu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
etiss_uint8
uint8_t etiss_uint8
Definition types.h:49
etiss::CodePart
Contains a small code snipped.
Definition CodePart.h:348
etiss::CodePart::code
std::string & code()
Definition CodePart.h:378
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition CodePart.h:376
etiss::CodeSet
A set of CodeParts.
Definition CodePart.h:399
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition CodePart.h:412
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition CodePart.h:184
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition Instruction.h:162
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition Instruction.cpp:171
etiss::instr::BitArray
stores a bit vector
Definition Instruction.h:114
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition Instruction.h:290
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition Instruction.h:319
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition Instruction.h:346
etiss
forwards: include/jit/*
Definition Benchmark.h:17
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