ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
•All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros Modules Pages
RV64IMACFD_RV64DInstr.cpp
Go to the documentation of this file.
1
8#include "RV64IMACFDArch.h"
9#include "RV64IMACFDFuncs.h"
10
11using namespace etiss;
12using namespace etiss::instr;
13
14
15// FCVT_L_D --------------------------------------------------------------------
16static InstructionDefinition fcvt_l_d_rd_rm_rs1 (
17 ISA32_RV64IMACFD,
18 "fcvt_l_d",
19 (uint32_t) 0xc2200053,
20 (uint32_t) 0xfff0007f,
21 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22 {
23
24// -----------------------------------------------------------------------------
25
26// -----------------------------------------------------------------------------
27
28// -----------------------------------------------------------------------------
29etiss_uint8 rd = 0;
30static BitArrayRange R_rd_0(11, 7);
31rd += R_rd_0.read(ba) << 0;
32etiss_uint8 rm = 0;
33static BitArrayRange R_rm_0(14, 12);
34rm += R_rm_0.read(ba) << 0;
35etiss_uint8 rs1 = 0;
36static BitArrayRange R_rs1_0(19, 15);
37rs1 += R_rs1_0.read(ba) << 0;
38
39// -----------------------------------------------------------------------------
40
41 {
42 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
43
44 cp.code() = std::string("//FCVT_L_D\n");
45
46// -----------------------------------------------------------------------------
47cp.code() += "etiss_coverage_count(1, 218);\n";
48{ // block
49cp.code() += "etiss_coverage_count(1, 1169);\n";
50cp.code() += "{ // block\n";
51cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
52cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
53cp.code() += "} // block\n";
54} // block
55{ // block
56cp.code() += "etiss_coverage_count(1, 8244);\n";
57cp.code() += "{ // block\n";
58cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = fcvt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), 0LL, " + std::to_string(rm) + "ULL);\n";
59cp.code() += "etiss_coverage_count(10, 8228, 8219, 8218, 8216, 8227, 8224, 8222, 8221, 8225, 8226);\n";
60cp.code() += "etiss_uint32 flags = fget_flags();\n";
61cp.code() += "etiss_coverage_count(2, 8231, 8230);\n";
62cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
63cp.code() += "etiss_coverage_count(9, 8243, 8232, 8242, 8236, 8233, 8237, 8240, 8238, 8241);\n";
64cp.code() += "} // block\n";
65} // block
66cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
67cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
68// -----------------------------------------------------------------------------
69 cp.getAffectedRegisters().add("instructionPointer", 32);
70 }
71
72 return true;
73 },
74 0,
75 [] (BitArray & ba, Instruction & instr)
76 {
77// -----------------------------------------------------------------------------
78etiss_uint8 rd = 0;
79static BitArrayRange R_rd_0(11, 7);
80rd += R_rd_0.read(ba) << 0;
81etiss_uint8 rm = 0;
82static BitArrayRange R_rm_0(14, 12);
83rm += R_rm_0.read(ba) << 0;
84etiss_uint8 rs1 = 0;
85static BitArrayRange R_rs1_0(19, 15);
86rs1 += R_rs1_0.read(ba) << 0;
87
88// -----------------------------------------------------------------------------
89
90 std::stringstream ss;
91// -----------------------------------------------------------------------------
92ss << "fcvt_l_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
93// -----------------------------------------------------------------------------
94 return ss.str();
95 }
96);
97
98// FCVT_LU_D -------------------------------------------------------------------
99static InstructionDefinition fcvt_lu_d_rd_rm_rs1 (
100 ISA32_RV64IMACFD,
101 "fcvt_lu_d",
102 (uint32_t) 0xc2300053,
103 (uint32_t) 0xfff0007f,
104 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
105 {
106
107// -----------------------------------------------------------------------------
108
109// -----------------------------------------------------------------------------
110
111// -----------------------------------------------------------------------------
112etiss_uint8 rd = 0;
113static BitArrayRange R_rd_0(11, 7);
114rd += R_rd_0.read(ba) << 0;
115etiss_uint8 rm = 0;
116static BitArrayRange R_rm_0(14, 12);
117rm += R_rm_0.read(ba) << 0;
118etiss_uint8 rs1 = 0;
119static BitArrayRange R_rs1_0(19, 15);
120rs1 += R_rs1_0.read(ba) << 0;
121
122// -----------------------------------------------------------------------------
123
124 {
125 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
126
127 cp.code() = std::string("//FCVT_LU_D\n");
128
129// -----------------------------------------------------------------------------
130cp.code() += "etiss_coverage_count(1, 219);\n";
131{ // block
132cp.code() += "etiss_coverage_count(1, 1169);\n";
133cp.code() += "{ // block\n";
134cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
135cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
136cp.code() += "} // block\n";
137} // block
138{ // block
139cp.code() += "etiss_coverage_count(1, 8274);\n";
140cp.code() += "{ // block\n";
141cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = fcvt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), 1ULL, " + std::to_string(rm) + "ULL);\n";
142cp.code() += "etiss_coverage_count(10, 8258, 8249, 8248, 8246, 8257, 8254, 8252, 8251, 8255, 8256);\n";
143cp.code() += "etiss_uint32 flags = fget_flags();\n";
144cp.code() += "etiss_coverage_count(2, 8261, 8260);\n";
145cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
146cp.code() += "etiss_coverage_count(9, 8273, 8262, 8272, 8266, 8263, 8267, 8270, 8268, 8271);\n";
147cp.code() += "} // block\n";
148} // block
149cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
150cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
151// -----------------------------------------------------------------------------
152 cp.getAffectedRegisters().add("instructionPointer", 32);
153 }
154
155 return true;
156 },
157 0,
158 [] (BitArray & ba, Instruction & instr)
159 {
160// -----------------------------------------------------------------------------
161etiss_uint8 rd = 0;
162static BitArrayRange R_rd_0(11, 7);
163rd += R_rd_0.read(ba) << 0;
164etiss_uint8 rm = 0;
165static BitArrayRange R_rm_0(14, 12);
166rm += R_rm_0.read(ba) << 0;
167etiss_uint8 rs1 = 0;
168static BitArrayRange R_rs1_0(19, 15);
169rs1 += R_rs1_0.read(ba) << 0;
170
171// -----------------------------------------------------------------------------
172
173 std::stringstream ss;
174// -----------------------------------------------------------------------------
175ss << "fcvt_lu_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
176// -----------------------------------------------------------------------------
177 return ss.str();
178 }
179);
180
181// FCVT_D_L --------------------------------------------------------------------
182static InstructionDefinition fcvt_d_l_rd_rm_rs1 (
183 ISA32_RV64IMACFD,
184 "fcvt_d_l",
185 (uint32_t) 0xd2200053,
186 (uint32_t) 0xfff0007f,
187 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
188 {
189
190// -----------------------------------------------------------------------------
191
192// -----------------------------------------------------------------------------
193
194// -----------------------------------------------------------------------------
195etiss_uint8 rd = 0;
196static BitArrayRange R_rd_0(11, 7);
197rd += R_rd_0.read(ba) << 0;
198etiss_uint8 rm = 0;
199static BitArrayRange R_rm_0(14, 12);
200rm += R_rm_0.read(ba) << 0;
201etiss_uint8 rs1 = 0;
202static BitArrayRange R_rs1_0(19, 15);
203rs1 += R_rs1_0.read(ba) << 0;
204
205// -----------------------------------------------------------------------------
206
207 {
208 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
209
210 cp.code() = std::string("//FCVT_D_L\n");
211
212// -----------------------------------------------------------------------------
213cp.code() += "etiss_coverage_count(1, 220);\n";
214{ // block
215cp.code() += "etiss_coverage_count(1, 1169);\n";
216cp.code() += "{ // block\n";
217cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
218cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
219cp.code() += "} // block\n";
220} // block
221{ // block
222cp.code() += "etiss_coverage_count(1, 8306);\n";
223cp.code() += "{ // block\n";
224cp.code() += "etiss_uint64 res = fcvt_d(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL], 2ULL, " + std::to_string(rm) + "ULL);\n";
225cp.code() += "etiss_coverage_count(7, 8284, 8283, 8280, 8279, 8277, 8281, 8282);\n";
226cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
227cp.code() += "etiss_coverage_count(4, 8293, 8291, 8290, 8292);\n";
228cp.code() += "} // block\n";
229} // block
230cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
231cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
232// -----------------------------------------------------------------------------
233 cp.getAffectedRegisters().add("instructionPointer", 32);
234 }
235
236 return true;
237 },
238 0,
239 [] (BitArray & ba, Instruction & instr)
240 {
241// -----------------------------------------------------------------------------
242etiss_uint8 rd = 0;
243static BitArrayRange R_rd_0(11, 7);
244rd += R_rd_0.read(ba) << 0;
245etiss_uint8 rm = 0;
246static BitArrayRange R_rm_0(14, 12);
247rm += R_rm_0.read(ba) << 0;
248etiss_uint8 rs1 = 0;
249static BitArrayRange R_rs1_0(19, 15);
250rs1 += R_rs1_0.read(ba) << 0;
251
252// -----------------------------------------------------------------------------
253
254 std::stringstream ss;
255// -----------------------------------------------------------------------------
256ss << "fcvt_d_l" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
257// -----------------------------------------------------------------------------
258 return ss.str();
259 }
260);
261
262// FCVT_D_LU -------------------------------------------------------------------
263static InstructionDefinition fcvt_d_lu_rd_rm_rs1 (
264 ISA32_RV64IMACFD,
265 "fcvt_d_lu",
266 (uint32_t) 0xd2300053,
267 (uint32_t) 0xfff0007f,
268 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
269 {
270
271// -----------------------------------------------------------------------------
272
273// -----------------------------------------------------------------------------
274
275// -----------------------------------------------------------------------------
276etiss_uint8 rd = 0;
277static BitArrayRange R_rd_0(11, 7);
278rd += R_rd_0.read(ba) << 0;
279etiss_uint8 rm = 0;
280static BitArrayRange R_rm_0(14, 12);
281rm += R_rm_0.read(ba) << 0;
282etiss_uint8 rs1 = 0;
283static BitArrayRange R_rs1_0(19, 15);
284rs1 += R_rs1_0.read(ba) << 0;
285
286// -----------------------------------------------------------------------------
287
288 {
289 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
290
291 cp.code() = std::string("//FCVT_D_LU\n");
292
293// -----------------------------------------------------------------------------
294cp.code() += "etiss_coverage_count(1, 221);\n";
295{ // block
296cp.code() += "etiss_coverage_count(1, 1169);\n";
297cp.code() += "{ // block\n";
298cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
299cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
300cp.code() += "} // block\n";
301} // block
302{ // block
303cp.code() += "etiss_coverage_count(1, 8338);\n";
304cp.code() += "{ // block\n";
305cp.code() += "etiss_uint64 res = fcvt_d(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL], 3ULL, " + std::to_string(rm) + "ULL);\n";
306cp.code() += "etiss_coverage_count(7, 8316, 8315, 8312, 8311, 8309, 8313, 8314);\n";
307cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
308cp.code() += "etiss_coverage_count(4, 8325, 8323, 8322, 8324);\n";
309cp.code() += "} // block\n";
310} // block
311cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
312cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
313// -----------------------------------------------------------------------------
314 cp.getAffectedRegisters().add("instructionPointer", 32);
315 }
316
317 return true;
318 },
319 0,
320 [] (BitArray & ba, Instruction & instr)
321 {
322// -----------------------------------------------------------------------------
323etiss_uint8 rd = 0;
324static BitArrayRange R_rd_0(11, 7);
325rd += R_rd_0.read(ba) << 0;
326etiss_uint8 rm = 0;
327static BitArrayRange R_rm_0(14, 12);
328rm += R_rm_0.read(ba) << 0;
329etiss_uint8 rs1 = 0;
330static BitArrayRange R_rs1_0(19, 15);
331rs1 += R_rs1_0.read(ba) << 0;
332
333// -----------------------------------------------------------------------------
334
335 std::stringstream ss;
336// -----------------------------------------------------------------------------
337ss << "fcvt_d_lu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
338// -----------------------------------------------------------------------------
339 return ss.str();
340 }
341);
342
343// FMV_X_D ---------------------------------------------------------------------
344static InstructionDefinition fmv_x_d_rd_rs1 (
345 ISA32_RV64IMACFD,
346 "fmv_x_d",
347 (uint32_t) 0xe2000053,
348 (uint32_t) 0xfff0707f,
349 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
350 {
351
352// -----------------------------------------------------------------------------
353
354// -----------------------------------------------------------------------------
355
356// -----------------------------------------------------------------------------
357etiss_uint8 rd = 0;
358static BitArrayRange R_rd_0(11, 7);
359rd += R_rd_0.read(ba) << 0;
360etiss_uint8 rs1 = 0;
361static BitArrayRange R_rs1_0(19, 15);
362rs1 += R_rs1_0.read(ba) << 0;
363
364// -----------------------------------------------------------------------------
365
366 {
367 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
368
369 cp.code() = std::string("//FMV_X_D\n");
370
371// -----------------------------------------------------------------------------
372cp.code() += "etiss_coverage_count(1, 222);\n";
373{ // block
374cp.code() += "etiss_coverage_count(1, 1169);\n";
375cp.code() += "{ // block\n";
376cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
377cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
378cp.code() += "} // block\n";
379} // block
380{ // block
381cp.code() += "etiss_coverage_count(1, 8348);\n";
382cp.code() += "{ // block\n";
383cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL];\n";
384cp.code() += "etiss_coverage_count(6, 8347, 8343, 8342, 8340, 8346, 8345);\n";
385cp.code() += "} // block\n";
386} // block
387cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
388cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
389// -----------------------------------------------------------------------------
390 cp.getAffectedRegisters().add("instructionPointer", 32);
391 }
392
393 return true;
394 },
395 0,
396 [] (BitArray & ba, Instruction & instr)
397 {
398// -----------------------------------------------------------------------------
399etiss_uint8 rd = 0;
400static BitArrayRange R_rd_0(11, 7);
401rd += R_rd_0.read(ba) << 0;
402etiss_uint8 rs1 = 0;
403static BitArrayRange R_rs1_0(19, 15);
404rs1 += R_rs1_0.read(ba) << 0;
405
406// -----------------------------------------------------------------------------
407
408 std::stringstream ss;
409// -----------------------------------------------------------------------------
410ss << "fmv_x_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + "]");
411// -----------------------------------------------------------------------------
412 return ss.str();
413 }
414);
415
416// FMV_D_X ---------------------------------------------------------------------
417static InstructionDefinition fmv_d_x_rd_rs1 (
418 ISA32_RV64IMACFD,
419 "fmv_d_x",
420 (uint32_t) 0xf2000053,
421 (uint32_t) 0xfff0707f,
422 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
423 {
424
425// -----------------------------------------------------------------------------
426
427// -----------------------------------------------------------------------------
428
429// -----------------------------------------------------------------------------
430etiss_uint8 rd = 0;
431static BitArrayRange R_rd_0(11, 7);
432rd += R_rd_0.read(ba) << 0;
433etiss_uint8 rs1 = 0;
434static BitArrayRange R_rs1_0(19, 15);
435rs1 += R_rs1_0.read(ba) << 0;
436
437// -----------------------------------------------------------------------------
438
439 {
440 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
441
442 cp.code() = std::string("//FMV_D_X\n");
443
444// -----------------------------------------------------------------------------
445cp.code() += "etiss_coverage_count(1, 223);\n";
446{ // block
447cp.code() += "etiss_coverage_count(1, 1169);\n";
448cp.code() += "{ // block\n";
449cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
450cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
451cp.code() += "} // block\n";
452} // block
453{ // block
454cp.code() += "etiss_coverage_count(1, 8358);\n";
455cp.code() += "{ // block\n";
456cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
457cp.code() += "etiss_coverage_count(6, 8357, 8351, 8350, 8356, 8355, 8353);\n";
458cp.code() += "} // block\n";
459} // block
460cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
461cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
462// -----------------------------------------------------------------------------
463 cp.getAffectedRegisters().add("instructionPointer", 32);
464 }
465
466 return true;
467 },
468 0,
469 [] (BitArray & ba, Instruction & instr)
470 {
471// -----------------------------------------------------------------------------
472etiss_uint8 rd = 0;
473static BitArrayRange R_rd_0(11, 7);
474rd += R_rd_0.read(ba) << 0;
475etiss_uint8 rs1 = 0;
476static BitArrayRange R_rs1_0(19, 15);
477rs1 += R_rs1_0.read(ba) << 0;
478
479// -----------------------------------------------------------------------------
480
481 std::stringstream ss;
482// -----------------------------------------------------------------------------
483ss << "fmv_d_x" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + "]");
484// -----------------------------------------------------------------------------
485 return ss.str();
486 }
487);
ISA32_RV64IMACFD
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
fcvt_l_d_rd_rm_rs1
static InstructionDefinition fcvt_l_d_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_l_d",(uint32_t) 0xc2200053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_L_D\n");cp.code()+="etiss_coverage_count(1, 218);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8244);\n";cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = fcvt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), 0LL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(10, 8228, 8219, 8218, 8216, 8227, 8224, 8222, 8221, 8225, 8226);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 8231, 8230);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 8243, 8232, 8242, 8236, 8233, 8237, 8240, 8238, 8241);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_l_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fcvt_lu_d_rd_rm_rs1
static InstructionDefinition fcvt_lu_d_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_lu_d",(uint32_t) 0xc2300053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_LU_D\n");cp.code()+="etiss_coverage_count(1, 219);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8274);\n";cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = fcvt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), 1ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(10, 8258, 8249, 8248, 8246, 8257, 8254, 8252, 8251, 8255, 8256);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 8261, 8260);\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 8273, 8262, 8272, 8266, 8263, 8267, 8270, 8268, 8271);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_lu_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fcvt_d_l_rd_rm_rs1
static InstructionDefinition fcvt_d_l_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_d_l",(uint32_t) 0xd2200053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_D_L\n");cp.code()+="etiss_coverage_count(1, 220);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8306);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fcvt_d(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL], 2ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(7, 8284, 8283, 8280, 8279, 8277, 8281, 8282);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 8293, 8291, 8290, 8292);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_d_l"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fmv_d_x_rd_rs1
static InstructionDefinition fmv_d_x_rd_rs1(ISA32_RV64IMACFD, "fmv_d_x",(uint32_t) 0xf2000053,(uint32_t) 0xfff0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMV_D_X\n");cp.code()+="etiss_coverage_count(1, 223);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8358);\n";cp.code()+="{ // block\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(6, 8357, 8351, 8350, 8356, 8355, 8353);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fmv_d_x"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fmv_x_d_rd_rs1
static InstructionDefinition fmv_x_d_rd_rs1(ISA32_RV64IMACFD, "fmv_x_d",(uint32_t) 0xe2000053,(uint32_t) 0xfff0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMV_X_D\n");cp.code()+="etiss_coverage_count(1, 222);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8348);\n";cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = ((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL];\n";cp.code()+="etiss_coverage_count(6, 8347, 8343, 8342, 8340, 8346, 8345);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fmv_x_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fcvt_d_lu_rd_rm_rs1
static InstructionDefinition fcvt_d_lu_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_d_lu",(uint32_t) 0xd2300053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_D_LU\n");cp.code()+="etiss_coverage_count(1, 221);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8338);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fcvt_d(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL], 3ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(7, 8316, 8315, 8312, 8311, 8309, 8313, 8314);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 8325, 8323, 8322, 8324);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_d_lu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
etiss_uint8
uint8_t etiss_uint8
Definition types.h:87
etiss::CodePart
Contains a small code snipped.
Definition CodePart.h:386
etiss::CodePart::code
std::string & code()
Definition CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition Benchmark.h:53
Generated on Mon Feb 17 2025 13:12:29 for ETISS 0.8.0 by doxygen 1.9.8