ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV64IMACFD_RV64DInstr.cpp
Go to the documentation of this file.
1 
8 #include "RV64IMACFDArch.h"
9 #include "RV64IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // FCVT_L_D --------------------------------------------------------------------
16 static InstructionDefinition fcvt_l_d_rd_rm_rs1 (
17  ISA32_RV64IMACFD,
18  "fcvt_l_d",
19  (uint32_t) 0xc2200053,
20  (uint32_t) 0xfff0007f,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 etiss_uint8 rd = 0;
30 static BitArrayRange R_rd_0(11, 7);
31 rd += R_rd_0.read(ba) << 0;
32 etiss_uint8 rm = 0;
33 static BitArrayRange R_rm_0(14, 12);
34 rm += R_rm_0.read(ba) << 0;
35 etiss_uint8 rs1 = 0;
36 static BitArrayRange R_rs1_0(19, 15);
37 rs1 += R_rs1_0.read(ba) << 0;
38 
39 // -----------------------------------------------------------------------------
40 
41  {
42  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
43 
44  cp.code() = std::string("//FCVT_L_D\n");
45 
46 // -----------------------------------------------------------------------------
47 { // block
48 cp.code() += "{ // block\n";
49 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
50 cp.code() += "} // block\n";
51 } // block
52 { // block
53 cp.code() += "{ // block\n";
54 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = fcvt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), 0LL, " + std::to_string(rm) + "ULL);\n";
55 cp.code() += "etiss_uint32 flags = fget_flags();\n";
56 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
57 cp.code() += "} // block\n";
58 } // block
59 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
60 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
61 // -----------------------------------------------------------------------------
62  cp.getAffectedRegisters().add("instructionPointer", 32);
63  }
64 
65  return true;
66  },
67  0,
68  [] (BitArray & ba, Instruction & instr)
69  {
70 // -----------------------------------------------------------------------------
71 etiss_uint8 rd = 0;
72 static BitArrayRange R_rd_0(11, 7);
73 rd += R_rd_0.read(ba) << 0;
74 etiss_uint8 rm = 0;
75 static BitArrayRange R_rm_0(14, 12);
76 rm += R_rm_0.read(ba) << 0;
77 etiss_uint8 rs1 = 0;
78 static BitArrayRange R_rs1_0(19, 15);
79 rs1 += R_rs1_0.read(ba) << 0;
80 
81 // -----------------------------------------------------------------------------
82 
83  std::stringstream ss;
84 // -----------------------------------------------------------------------------
85 ss << "fcvt_l_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
86 // -----------------------------------------------------------------------------
87  return ss.str();
88  }
89 );
90 
91 // FCVT_LU_D -------------------------------------------------------------------
92 static InstructionDefinition fcvt_lu_d_rd_rm_rs1 (
93  ISA32_RV64IMACFD,
94  "fcvt_lu_d",
95  (uint32_t) 0xc2300053,
96  (uint32_t) 0xfff0007f,
97  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
98  {
99 
100 // -----------------------------------------------------------------------------
101 
102 // -----------------------------------------------------------------------------
103 
104 // -----------------------------------------------------------------------------
105 etiss_uint8 rd = 0;
106 static BitArrayRange R_rd_0(11, 7);
107 rd += R_rd_0.read(ba) << 0;
108 etiss_uint8 rm = 0;
109 static BitArrayRange R_rm_0(14, 12);
110 rm += R_rm_0.read(ba) << 0;
111 etiss_uint8 rs1 = 0;
112 static BitArrayRange R_rs1_0(19, 15);
113 rs1 += R_rs1_0.read(ba) << 0;
114 
115 // -----------------------------------------------------------------------------
116 
117  {
118  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
119 
120  cp.code() = std::string("//FCVT_LU_D\n");
121 
122 // -----------------------------------------------------------------------------
123 { // block
124 cp.code() += "{ // block\n";
125 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
126 cp.code() += "} // block\n";
127 } // block
128 { // block
129 cp.code() += "{ // block\n";
130 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = fcvt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), 1ULL, " + std::to_string(rm) + "ULL);\n";
131 cp.code() += "etiss_uint32 flags = fget_flags();\n";
132 cp.code() += "((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
133 cp.code() += "} // block\n";
134 } // block
135 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
136 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
137 // -----------------------------------------------------------------------------
138  cp.getAffectedRegisters().add("instructionPointer", 32);
139  }
140 
141  return true;
142  },
143  0,
144  [] (BitArray & ba, Instruction & instr)
145  {
146 // -----------------------------------------------------------------------------
147 etiss_uint8 rd = 0;
148 static BitArrayRange R_rd_0(11, 7);
149 rd += R_rd_0.read(ba) << 0;
150 etiss_uint8 rm = 0;
151 static BitArrayRange R_rm_0(14, 12);
152 rm += R_rm_0.read(ba) << 0;
153 etiss_uint8 rs1 = 0;
154 static BitArrayRange R_rs1_0(19, 15);
155 rs1 += R_rs1_0.read(ba) << 0;
156 
157 // -----------------------------------------------------------------------------
158 
159  std::stringstream ss;
160 // -----------------------------------------------------------------------------
161 ss << "fcvt_lu_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
162 // -----------------------------------------------------------------------------
163  return ss.str();
164  }
165 );
166 
167 // FCVT_D_L --------------------------------------------------------------------
168 static InstructionDefinition fcvt_d_l_rd_rm_rs1 (
169  ISA32_RV64IMACFD,
170  "fcvt_d_l",
171  (uint32_t) 0xd2200053,
172  (uint32_t) 0xfff0007f,
173  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
174  {
175 
176 // -----------------------------------------------------------------------------
177 
178 // -----------------------------------------------------------------------------
179 
180 // -----------------------------------------------------------------------------
181 etiss_uint8 rd = 0;
182 static BitArrayRange R_rd_0(11, 7);
183 rd += R_rd_0.read(ba) << 0;
184 etiss_uint8 rm = 0;
185 static BitArrayRange R_rm_0(14, 12);
186 rm += R_rm_0.read(ba) << 0;
187 etiss_uint8 rs1 = 0;
188 static BitArrayRange R_rs1_0(19, 15);
189 rs1 += R_rs1_0.read(ba) << 0;
190 
191 // -----------------------------------------------------------------------------
192 
193  {
194  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
195 
196  cp.code() = std::string("//FCVT_D_L\n");
197 
198 // -----------------------------------------------------------------------------
199 { // block
200 cp.code() += "{ // block\n";
201 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
202 cp.code() += "} // block\n";
203 } // block
204 { // block
205 cp.code() += "{ // block\n";
206 cp.code() += "etiss_uint64 res = fcvt_d(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL], 2ULL, " + std::to_string(rm) + "ULL);\n";
207 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
208 cp.code() += "} // block\n";
209 } // block
210 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
211 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
212 // -----------------------------------------------------------------------------
213  cp.getAffectedRegisters().add("instructionPointer", 32);
214  }
215 
216  return true;
217  },
218  0,
219  [] (BitArray & ba, Instruction & instr)
220  {
221 // -----------------------------------------------------------------------------
222 etiss_uint8 rd = 0;
223 static BitArrayRange R_rd_0(11, 7);
224 rd += R_rd_0.read(ba) << 0;
225 etiss_uint8 rm = 0;
226 static BitArrayRange R_rm_0(14, 12);
227 rm += R_rm_0.read(ba) << 0;
228 etiss_uint8 rs1 = 0;
229 static BitArrayRange R_rs1_0(19, 15);
230 rs1 += R_rs1_0.read(ba) << 0;
231 
232 // -----------------------------------------------------------------------------
233 
234  std::stringstream ss;
235 // -----------------------------------------------------------------------------
236 ss << "fcvt_d_l" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
237 // -----------------------------------------------------------------------------
238  return ss.str();
239  }
240 );
241 
242 // FCVT_D_LU -------------------------------------------------------------------
243 static InstructionDefinition fcvt_d_lu_rd_rm_rs1 (
244  ISA32_RV64IMACFD,
245  "fcvt_d_lu",
246  (uint32_t) 0xd2300053,
247  (uint32_t) 0xfff0007f,
248  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
249  {
250 
251 // -----------------------------------------------------------------------------
252 
253 // -----------------------------------------------------------------------------
254 
255 // -----------------------------------------------------------------------------
256 etiss_uint8 rd = 0;
257 static BitArrayRange R_rd_0(11, 7);
258 rd += R_rd_0.read(ba) << 0;
259 etiss_uint8 rm = 0;
260 static BitArrayRange R_rm_0(14, 12);
261 rm += R_rm_0.read(ba) << 0;
262 etiss_uint8 rs1 = 0;
263 static BitArrayRange R_rs1_0(19, 15);
264 rs1 += R_rs1_0.read(ba) << 0;
265 
266 // -----------------------------------------------------------------------------
267 
268  {
269  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
270 
271  cp.code() = std::string("//FCVT_D_LU\n");
272 
273 // -----------------------------------------------------------------------------
274 { // block
275 cp.code() += "{ // block\n";
276 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
277 cp.code() += "} // block\n";
278 } // block
279 { // block
280 cp.code() += "{ // block\n";
281 cp.code() += "etiss_uint64 res = fcvt_d(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL], 3ULL, " + std::to_string(rm) + "ULL);\n";
282 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
283 cp.code() += "} // block\n";
284 } // block
285 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
286 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
287 // -----------------------------------------------------------------------------
288  cp.getAffectedRegisters().add("instructionPointer", 32);
289  }
290 
291  return true;
292  },
293  0,
294  [] (BitArray & ba, Instruction & instr)
295  {
296 // -----------------------------------------------------------------------------
297 etiss_uint8 rd = 0;
298 static BitArrayRange R_rd_0(11, 7);
299 rd += R_rd_0.read(ba) << 0;
300 etiss_uint8 rm = 0;
301 static BitArrayRange R_rm_0(14, 12);
302 rm += R_rm_0.read(ba) << 0;
303 etiss_uint8 rs1 = 0;
304 static BitArrayRange R_rs1_0(19, 15);
305 rs1 += R_rs1_0.read(ba) << 0;
306 
307 // -----------------------------------------------------------------------------
308 
309  std::stringstream ss;
310 // -----------------------------------------------------------------------------
311 ss << "fcvt_d_lu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
312 // -----------------------------------------------------------------------------
313  return ss.str();
314  }
315 );
316 
317 // FMV_X_D ---------------------------------------------------------------------
318 static InstructionDefinition fmv_x_d_rd_rs1 (
319  ISA32_RV64IMACFD,
320  "fmv_x_d",
321  (uint32_t) 0xe2000053,
322  (uint32_t) 0xfff0707f,
323  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
324  {
325 
326 // -----------------------------------------------------------------------------
327 
328 // -----------------------------------------------------------------------------
329 
330 // -----------------------------------------------------------------------------
331 etiss_uint8 rd = 0;
332 static BitArrayRange R_rd_0(11, 7);
333 rd += R_rd_0.read(ba) << 0;
334 etiss_uint8 rs1 = 0;
335 static BitArrayRange R_rs1_0(19, 15);
336 rs1 += R_rs1_0.read(ba) << 0;
337 
338 // -----------------------------------------------------------------------------
339 
340  {
341  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
342 
343  cp.code() = std::string("//FMV_X_D\n");
344 
345 // -----------------------------------------------------------------------------
346 { // block
347 cp.code() += "{ // block\n";
348 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
349 cp.code() += "} // block\n";
350 } // block
351 { // block
352 cp.code() += "{ // block\n";
353 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((RV64IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL];\n";
354 cp.code() += "} // block\n";
355 } // block
356 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
357 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
358 // -----------------------------------------------------------------------------
359  cp.getAffectedRegisters().add("instructionPointer", 32);
360  }
361 
362  return true;
363  },
364  0,
365  [] (BitArray & ba, Instruction & instr)
366  {
367 // -----------------------------------------------------------------------------
368 etiss_uint8 rd = 0;
369 static BitArrayRange R_rd_0(11, 7);
370 rd += R_rd_0.read(ba) << 0;
371 etiss_uint8 rs1 = 0;
372 static BitArrayRange R_rs1_0(19, 15);
373 rs1 += R_rs1_0.read(ba) << 0;
374 
375 // -----------------------------------------------------------------------------
376 
377  std::stringstream ss;
378 // -----------------------------------------------------------------------------
379 ss << "fmv_x_d" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + "]");
380 // -----------------------------------------------------------------------------
381  return ss.str();
382  }
383 );
384 
385 // FMV_D_X ---------------------------------------------------------------------
386 static InstructionDefinition fmv_d_x_rd_rs1 (
387  ISA32_RV64IMACFD,
388  "fmv_d_x",
389  (uint32_t) 0xf2000053,
390  (uint32_t) 0xfff0707f,
391  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
392  {
393 
394 // -----------------------------------------------------------------------------
395 
396 // -----------------------------------------------------------------------------
397 
398 // -----------------------------------------------------------------------------
399 etiss_uint8 rd = 0;
400 static BitArrayRange R_rd_0(11, 7);
401 rd += R_rd_0.read(ba) << 0;
402 etiss_uint8 rs1 = 0;
403 static BitArrayRange R_rs1_0(19, 15);
404 rs1 += R_rs1_0.read(ba) << 0;
405 
406 // -----------------------------------------------------------------------------
407 
408  {
409  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
410 
411  cp.code() = std::string("//FMV_D_X\n");
412 
413 // -----------------------------------------------------------------------------
414 { // block
415 cp.code() += "{ // block\n";
416 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
417 cp.code() += "} // block\n";
418 } // block
419 { // block
420 cp.code() += "{ // block\n";
421 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
422 cp.code() += "} // block\n";
423 } // block
424 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
425 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
426 // -----------------------------------------------------------------------------
427  cp.getAffectedRegisters().add("instructionPointer", 32);
428  }
429 
430  return true;
431  },
432  0,
433  [] (BitArray & ba, Instruction & instr)
434  {
435 // -----------------------------------------------------------------------------
436 etiss_uint8 rd = 0;
437 static BitArrayRange R_rd_0(11, 7);
438 rd += R_rd_0.read(ba) << 0;
439 etiss_uint8 rs1 = 0;
440 static BitArrayRange R_rs1_0(19, 15);
441 rs1 += R_rs1_0.read(ba) << 0;
442 
443 // -----------------------------------------------------------------------------
444 
445  std::stringstream ss;
446 // -----------------------------------------------------------------------------
447 ss << "fmv_d_x" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + "]");
448 // -----------------------------------------------------------------------------
449  return ss.str();
450  }
451 );
ISA32_RV64IMACFD
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
fmv_d_x_rd_rs1
static InstructionDefinition fmv_d_x_rd_rs1(ISA32_RV64IMACFD, "fmv_d_x",(uint32_t) 0xf2000053,(uint32_t) 0xfff0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMV_D_X\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fmv_d_x"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fcvt_lu_d_rd_rm_rs1
static InstructionDefinition fcvt_lu_d_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_lu_d",(uint32_t) 0xc2300053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_LU_D\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = fcvt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), 1ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_lu_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fcvt_d_l_rd_rm_rs1
static InstructionDefinition fcvt_d_l_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_d_l",(uint32_t) 0xd2200053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_D_L\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fcvt_d(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL], 2ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_d_l"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fmv_x_d_rd_rs1
static InstructionDefinition fmv_x_d_rd_rs1(ISA32_RV64IMACFD, "fmv_x_d",(uint32_t) 0xe2000053,(uint32_t) 0xfff0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMV_X_D\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = ((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL];\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fmv_x_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fcvt_d_lu_rd_rm_rs1
static InstructionDefinition fcvt_d_lu_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_d_lu",(uint32_t) 0xd2300053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_D_LU\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = fcvt_d(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL], 3ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_d_lu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fcvt_l_d_rd_rm_rs1
static InstructionDefinition fcvt_l_d_rd_rm_rs1(ISA32_RV64IMACFD, "fcvt_l_d",(uint32_t) 0xc2200053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_L_D\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = fcvt_d((etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), 0LL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV64IMACFD*)cpu)->FCSR = (((RV64IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_l_d"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
uint32_t
static __inline__ uint32_t
Definition: arm_cde.h:25
etiss_uint8
uint8_t etiss_uint8
Definition: types.h:87
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:386
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition: Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition: Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
Generated on Thu Jul 4 2024 12:41:53 for ETISS 0.8.0 by doxygen 1.9.1