20 (uint64_t) 0xf800707f,
32rd += R_rd_0.
read(ba) << 0;
35rs1 += R_rs1_0.
read(ba) << 0;
38rs2 += R_rs2_0.
read(ba) << 0;
41rl += R_rl_0.
read(ba) << 0;
44aq += R_aq_0.
read(ba) << 0;
52 cp.
code() = std::string(
"//AMOSWAPD\n");
55cp.
code() +=
"etiss_coverage_count(1, 226);\n";
57cp.
code() +=
"etiss_coverage_count(1, 1189);\n";
58cp.
code() +=
"{ // block\n";
60cp.
code() +=
"etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
61cp.
code() +=
"} // block\n";
64cp.
code() +=
"etiss_coverage_count(1, 8930);\n";
65cp.
code() +=
"{ // block\n";
66cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
67cp.
code() +=
"etiss_coverage_count(4, 8891, 8890, 8889, 8887);\n";
68cp.
code() +=
"etiss_coverage_count(1, 8892);\n";
69if ((rd % 32ULL) != 0LL) {
70cp.
code() +=
"etiss_coverage_count(5, 8898, 8895, 8893, 8896, 8897);\n";
71cp.
code() +=
"etiss_uint64 mem_val_0;\n";
72cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
73cp.
code() +=
"if (cpu->exception) { // conditional\n";
75cp.
code() +=
"{ // procedure\n";
76cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
78cp.
code() +=
"} // procedure\n";
80cp.
code() +=
"} // conditional\n";
81cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = (etiss_int64)(((etiss_int64)(mem_val_0)));\n";
82cp.
code() +=
"etiss_coverage_count(11, 8915, 8903, 8902, 8900, 8914, 8911, 8909, 8907, 8905, 8906, 8912);\n";
84cp.
code() +=
"etiss_uint64 mem_val_1;\n";
85cp.
code() +=
"mem_val_1 = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL]);\n";
86cp.
code() +=
"etiss_coverage_count(9, 8929, 8921, 8919, 8917, 8918, 8928, 8926, 8925, 8923);\n";
87cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
88cp.
code() +=
"if (cpu->exception) { // conditional\n";
90cp.
code() +=
"{ // procedure\n";
91cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
93cp.
code() +=
"} // procedure\n";
95cp.
code() +=
"} // conditional\n";
96cp.
code() +=
"} // block\n";
99cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
106 cp.
code() = std::string(
"//AMOSWAPD\n");
109cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
121rd += R_rd_0.read(ba) << 0;
124rs1 += R_rs1_0.read(ba) << 0;
127rs2 += R_rs2_0.read(ba) << 0;
130rl += R_rl_0.read(ba) << 0;
133aq += R_aq_0.read(ba) << 0;
137 std::stringstream ss;
139ss <<
"amoswapd" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
150 (uint64_t) 0xf800707f,
162rd += R_rd_0.
read(ba) << 0;
165rs1 += R_rs1_0.
read(ba) << 0;
168rs2 += R_rs2_0.
read(ba) << 0;
171rl += R_rl_0.
read(ba) << 0;
174aq += R_aq_0.
read(ba) << 0;
182 cp.
code() = std::string(
"//AMOADDD\n");
185cp.
code() +=
"etiss_coverage_count(1, 227);\n";
187cp.
code() +=
"etiss_coverage_count(1, 1189);\n";
188cp.
code() +=
"{ // block\n";
190cp.
code() +=
"etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
191cp.
code() +=
"} // block\n";
194cp.
code() +=
"etiss_coverage_count(1, 8977);\n";
195cp.
code() +=
"{ // block\n";
196cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
197cp.
code() +=
"etiss_coverage_count(4, 8937, 8936, 8935, 8933);\n";
198cp.
code() +=
"etiss_uint64 mem_val_0;\n";
199cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
200cp.
code() +=
"if (cpu->exception) { // conditional\n";
202cp.
code() +=
"{ // procedure\n";
203cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
205cp.
code() +=
"} // procedure\n";
207cp.
code() +=
"} // conditional\n";
208cp.
code() +=
"etiss_int64 res = mem_val_0;\n";
209cp.
code() +=
"etiss_coverage_count(5, 8945, 8944, 8942, 8940, 8941);\n";
210cp.
code() +=
"etiss_coverage_count(1, 8946);\n";
211if ((rd % 32ULL) != 0LL) {
212cp.
code() +=
"etiss_coverage_count(5, 8952, 8949, 8947, 8950, 8951);\n";
213cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = res;\n";
214cp.
code() +=
"etiss_coverage_count(5, 8959, 8957, 8956, 8954, 8958);\n";
216cp.
code() +=
"etiss_uint64 res2 = res + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL];\n";
217cp.
code() +=
"etiss_coverage_count(6, 8968, 8967, 8961, 8966, 8965, 8963);\n";
218cp.
code() +=
"etiss_uint64 mem_val_1;\n";
219cp.
code() +=
"mem_val_1 = res2;\n";
220cp.
code() +=
"etiss_coverage_count(6, 8976, 8974, 8972, 8970, 8971, 8975);\n";
221cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
222cp.
code() +=
"if (cpu->exception) { // conditional\n";
224cp.
code() +=
"{ // procedure\n";
225cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
227cp.
code() +=
"} // procedure\n";
229cp.
code() +=
"} // conditional\n";
230cp.
code() +=
"} // block\n";
233cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
240 cp.
code() = std::string(
"//AMOADDD\n");
243cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
255rd += R_rd_0.read(ba) << 0;
258rs1 += R_rs1_0.read(ba) << 0;
261rs2 += R_rs2_0.read(ba) << 0;
264rl += R_rl_0.read(ba) << 0;
267aq += R_aq_0.read(ba) << 0;
271 std::stringstream ss;
273ss <<
"amoaddd" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
283 (uint64_t) 0x2000302f,
284 (uint64_t) 0xf800707f,
296rd += R_rd_0.
read(ba) << 0;
299rs1 += R_rs1_0.
read(ba) << 0;
302rs2 += R_rs2_0.
read(ba) << 0;
305rl += R_rl_0.
read(ba) << 0;
308aq += R_aq_0.
read(ba) << 0;
316 cp.
code() = std::string(
"//AMOXORD\n");
319cp.
code() +=
"etiss_coverage_count(1, 228);\n";
321cp.
code() +=
"etiss_coverage_count(1, 1189);\n";
322cp.
code() +=
"{ // block\n";
324cp.
code() +=
"etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
325cp.
code() +=
"} // block\n";
328cp.
code() +=
"etiss_coverage_count(1, 9024);\n";
329cp.
code() +=
"{ // block\n";
330cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
331cp.
code() +=
"etiss_coverage_count(4, 8984, 8983, 8982, 8980);\n";
332cp.
code() +=
"etiss_uint64 mem_val_0;\n";
333cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
334cp.
code() +=
"if (cpu->exception) { // conditional\n";
336cp.
code() +=
"{ // procedure\n";
337cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
339cp.
code() +=
"} // procedure\n";
341cp.
code() +=
"} // conditional\n";
342cp.
code() +=
"etiss_int64 res = mem_val_0;\n";
343cp.
code() +=
"etiss_coverage_count(5, 8992, 8991, 8989, 8987, 8988);\n";
344cp.
code() +=
"etiss_coverage_count(1, 8993);\n";
345if ((rd % 32ULL) != 0LL) {
346cp.
code() +=
"etiss_coverage_count(5, 8999, 8996, 8994, 8997, 8998);\n";
347cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = res;\n";
348cp.
code() +=
"etiss_coverage_count(5, 9006, 9004, 9003, 9001, 9005);\n";
350cp.
code() +=
"etiss_uint64 res2 = res ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL];\n";
351cp.
code() +=
"etiss_coverage_count(6, 9015, 9014, 9008, 9013, 9012, 9010);\n";
352cp.
code() +=
"etiss_uint64 mem_val_1;\n";
353cp.
code() +=
"mem_val_1 = res2;\n";
354cp.
code() +=
"etiss_coverage_count(6, 9023, 9021, 9019, 9017, 9018, 9022);\n";
355cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
356cp.
code() +=
"if (cpu->exception) { // conditional\n";
358cp.
code() +=
"{ // procedure\n";
359cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
361cp.
code() +=
"} // procedure\n";
363cp.
code() +=
"} // conditional\n";
364cp.
code() +=
"} // block\n";
367cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
374 cp.
code() = std::string(
"//AMOXORD\n");
377cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
389rd += R_rd_0.read(ba) << 0;
392rs1 += R_rs1_0.read(ba) << 0;
395rs2 += R_rs2_0.read(ba) << 0;
398rl += R_rl_0.read(ba) << 0;
401aq += R_aq_0.read(ba) << 0;
405 std::stringstream ss;
407ss <<
"amoxord" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
417 (uint64_t) 0x6000302f,
418 (uint64_t) 0xf800707f,
430rd += R_rd_0.
read(ba) << 0;
433rs1 += R_rs1_0.
read(ba) << 0;
436rs2 += R_rs2_0.
read(ba) << 0;
439rl += R_rl_0.
read(ba) << 0;
442aq += R_aq_0.
read(ba) << 0;
450 cp.
code() = std::string(
"//AMOANDD\n");
453cp.
code() +=
"etiss_coverage_count(1, 229);\n";
455cp.
code() +=
"etiss_coverage_count(1, 1189);\n";
456cp.
code() +=
"{ // block\n";
458cp.
code() +=
"etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
459cp.
code() +=
"} // block\n";
462cp.
code() +=
"etiss_coverage_count(1, 9071);\n";
463cp.
code() +=
"{ // block\n";
464cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
465cp.
code() +=
"etiss_coverage_count(4, 9031, 9030, 9029, 9027);\n";
466cp.
code() +=
"etiss_uint64 mem_val_0;\n";
467cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
468cp.
code() +=
"if (cpu->exception) { // conditional\n";
470cp.
code() +=
"{ // procedure\n";
471cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
473cp.
code() +=
"} // procedure\n";
475cp.
code() +=
"} // conditional\n";
476cp.
code() +=
"etiss_int64 res = mem_val_0;\n";
477cp.
code() +=
"etiss_coverage_count(5, 9039, 9038, 9036, 9034, 9035);\n";
478cp.
code() +=
"etiss_coverage_count(1, 9040);\n";
479if ((rd % 32ULL) != 0LL) {
480cp.
code() +=
"etiss_coverage_count(5, 9046, 9043, 9041, 9044, 9045);\n";
481cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = res;\n";
482cp.
code() +=
"etiss_coverage_count(5, 9053, 9051, 9050, 9048, 9052);\n";
484cp.
code() +=
"etiss_uint64 res2 = res & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL];\n";
485cp.
code() +=
"etiss_coverage_count(6, 9062, 9061, 9055, 9060, 9059, 9057);\n";
486cp.
code() +=
"etiss_uint64 mem_val_1;\n";
487cp.
code() +=
"mem_val_1 = res2;\n";
488cp.
code() +=
"etiss_coverage_count(6, 9070, 9068, 9066, 9064, 9065, 9069);\n";
489cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
490cp.
code() +=
"if (cpu->exception) { // conditional\n";
492cp.
code() +=
"{ // procedure\n";
493cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
495cp.
code() +=
"} // procedure\n";
497cp.
code() +=
"} // conditional\n";
498cp.
code() +=
"} // block\n";
501cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
508 cp.
code() = std::string(
"//AMOANDD\n");
511cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
523rd += R_rd_0.read(ba) << 0;
526rs1 += R_rs1_0.read(ba) << 0;
529rs2 += R_rs2_0.read(ba) << 0;
532rl += R_rl_0.read(ba) << 0;
535aq += R_aq_0.read(ba) << 0;
539 std::stringstream ss;
541ss <<
"amoandd" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
551 (uint64_t) 0x4000302f,
552 (uint64_t) 0xf800707f,
564rd += R_rd_0.
read(ba) << 0;
567rs1 += R_rs1_0.
read(ba) << 0;
570rs2 += R_rs2_0.
read(ba) << 0;
573rl += R_rl_0.
read(ba) << 0;
576aq += R_aq_0.
read(ba) << 0;
584 cp.
code() = std::string(
"//AMOORD\n");
587cp.
code() +=
"etiss_coverage_count(1, 230);\n";
589cp.
code() +=
"etiss_coverage_count(1, 1189);\n";
590cp.
code() +=
"{ // block\n";
592cp.
code() +=
"etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
593cp.
code() +=
"} // block\n";
596cp.
code() +=
"etiss_coverage_count(1, 9118);\n";
597cp.
code() +=
"{ // block\n";
598cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
599cp.
code() +=
"etiss_coverage_count(4, 9078, 9077, 9076, 9074);\n";
600cp.
code() +=
"etiss_uint64 mem_val_0;\n";
601cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
602cp.
code() +=
"if (cpu->exception) { // conditional\n";
604cp.
code() +=
"{ // procedure\n";
605cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
607cp.
code() +=
"} // procedure\n";
609cp.
code() +=
"} // conditional\n";
610cp.
code() +=
"etiss_int64 res = mem_val_0;\n";
611cp.
code() +=
"etiss_coverage_count(5, 9086, 9085, 9083, 9081, 9082);\n";
612cp.
code() +=
"etiss_coverage_count(1, 9087);\n";
613if ((rd % 32ULL) != 0LL) {
614cp.
code() +=
"etiss_coverage_count(5, 9093, 9090, 9088, 9091, 9092);\n";
615cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = res;\n";
616cp.
code() +=
"etiss_coverage_count(5, 9100, 9098, 9097, 9095, 9099);\n";
618cp.
code() +=
"etiss_uint64 res2 = res | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL];\n";
619cp.
code() +=
"etiss_coverage_count(6, 9109, 9108, 9102, 9107, 9106, 9104);\n";
620cp.
code() +=
"etiss_uint64 mem_val_1;\n";
621cp.
code() +=
"mem_val_1 = res2;\n";
622cp.
code() +=
"etiss_coverage_count(6, 9117, 9115, 9113, 9111, 9112, 9116);\n";
623cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
624cp.
code() +=
"if (cpu->exception) { // conditional\n";
626cp.
code() +=
"{ // procedure\n";
627cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
629cp.
code() +=
"} // procedure\n";
631cp.
code() +=
"} // conditional\n";
632cp.
code() +=
"} // block\n";
635cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
642 cp.
code() = std::string(
"//AMOORD\n");
645cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
657rd += R_rd_0.read(ba) << 0;
660rs1 += R_rs1_0.read(ba) << 0;
663rs2 += R_rs2_0.read(ba) << 0;
666rl += R_rl_0.read(ba) << 0;
669aq += R_aq_0.read(ba) << 0;
673 std::stringstream ss;
675ss <<
"amoord" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
685 (uint64_t) 0x8000302f,
686 (uint64_t) 0xf800707f,
698rd += R_rd_0.
read(ba) << 0;
701rs1 += R_rs1_0.
read(ba) << 0;
704rs2 += R_rs2_0.
read(ba) << 0;
707rl += R_rl_0.
read(ba) << 0;
710aq += R_aq_0.
read(ba) << 0;
718 cp.
code() = std::string(
"//AMOMIND\n");
721cp.
code() +=
"etiss_coverage_count(1, 231);\n";
723cp.
code() +=
"etiss_coverage_count(1, 1189);\n";
724cp.
code() +=
"{ // block\n";
726cp.
code() +=
"etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
727cp.
code() +=
"} // block\n";
730cp.
code() +=
"etiss_coverage_count(1, 9174);\n";
731cp.
code() +=
"{ // block\n";
732cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
733cp.
code() +=
"etiss_coverage_count(4, 9125, 9124, 9123, 9121);\n";
734cp.
code() +=
"etiss_uint64 mem_val_0;\n";
735cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
736cp.
code() +=
"if (cpu->exception) { // conditional\n";
738cp.
code() +=
"{ // procedure\n";
739cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
741cp.
code() +=
"} // procedure\n";
743cp.
code() +=
"} // conditional\n";
744cp.
code() +=
"etiss_int64 res1 = mem_val_0;\n";
745cp.
code() +=
"etiss_coverage_count(5, 9133, 9132, 9130, 9128, 9129);\n";
746cp.
code() +=
"etiss_coverage_count(1, 9134);\n";
747if ((rd % 32ULL) != 0LL) {
748cp.
code() +=
"etiss_coverage_count(5, 9140, 9137, 9135, 9138, 9139);\n";
749cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = res1;\n";
750cp.
code() +=
"etiss_coverage_count(5, 9147, 9145, 9144, 9142, 9146);\n";
752cp.
code() +=
"etiss_uint64 res2 = (res1 > (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL]) : (res1);\n";
753cp.
code() +=
"etiss_coverage_count(12, 9165, 9164, 9157, 9149, 9156, 9154, 9153, 9151, 9162, 9161, 9159, 9163);\n";
754cp.
code() +=
"etiss_uint64 mem_val_1;\n";
755cp.
code() +=
"mem_val_1 = res2;\n";
756cp.
code() +=
"etiss_coverage_count(6, 9173, 9171, 9169, 9167, 9168, 9172);\n";
757cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
758cp.
code() +=
"if (cpu->exception) { // conditional\n";
760cp.
code() +=
"{ // procedure\n";
761cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
763cp.
code() +=
"} // procedure\n";
765cp.
code() +=
"} // conditional\n";
766cp.
code() +=
"} // block\n";
769cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
776 cp.
code() = std::string(
"//AMOMIND\n");
779cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
791rd += R_rd_0.read(ba) << 0;
794rs1 += R_rs1_0.read(ba) << 0;
797rs2 += R_rs2_0.read(ba) << 0;
800rl += R_rl_0.read(ba) << 0;
803aq += R_aq_0.read(ba) << 0;
807 std::stringstream ss;
809ss <<
"amomind" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
819 (uint64_t) 0xa000302f,
820 (uint64_t) 0xf800707f,
832rd += R_rd_0.
read(ba) << 0;
835rs1 += R_rs1_0.
read(ba) << 0;
838rs2 += R_rs2_0.
read(ba) << 0;
841rl += R_rl_0.
read(ba) << 0;
844aq += R_aq_0.
read(ba) << 0;
852 cp.
code() = std::string(
"//AMOMAXD\n");
855cp.
code() +=
"etiss_coverage_count(1, 232);\n";
857cp.
code() +=
"etiss_coverage_count(1, 1189);\n";
858cp.
code() +=
"{ // block\n";
860cp.
code() +=
"etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
861cp.
code() +=
"} // block\n";
864cp.
code() +=
"etiss_coverage_count(1, 9230);\n";
865cp.
code() +=
"{ // block\n";
866cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
867cp.
code() +=
"etiss_coverage_count(4, 9181, 9180, 9179, 9177);\n";
868cp.
code() +=
"etiss_uint64 mem_val_0;\n";
869cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
870cp.
code() +=
"if (cpu->exception) { // conditional\n";
872cp.
code() +=
"{ // procedure\n";
873cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
875cp.
code() +=
"} // procedure\n";
877cp.
code() +=
"} // conditional\n";
878cp.
code() +=
"etiss_int64 res = mem_val_0;\n";
879cp.
code() +=
"etiss_coverage_count(5, 9189, 9188, 9186, 9184, 9185);\n";
880cp.
code() +=
"etiss_coverage_count(1, 9190);\n";
881if ((rd % 32ULL) != 0LL) {
882cp.
code() +=
"etiss_coverage_count(5, 9196, 9193, 9191, 9194, 9195);\n";
883cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = res;\n";
884cp.
code() +=
"etiss_coverage_count(5, 9203, 9201, 9200, 9198, 9202);\n";
886cp.
code() +=
"etiss_uint64 res2 = (res < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL]) : (res);\n";
887cp.
code() +=
"etiss_coverage_count(12, 9221, 9220, 9213, 9205, 9212, 9210, 9209, 9207, 9218, 9217, 9215, 9219);\n";
888cp.
code() +=
"etiss_uint64 mem_val_1;\n";
889cp.
code() +=
"mem_val_1 = res2;\n";
890cp.
code() +=
"etiss_coverage_count(6, 9229, 9227, 9225, 9223, 9224, 9228);\n";
891cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
892cp.
code() +=
"if (cpu->exception) { // conditional\n";
894cp.
code() +=
"{ // procedure\n";
895cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
897cp.
code() +=
"} // procedure\n";
899cp.
code() +=
"} // conditional\n";
900cp.
code() +=
"} // block\n";
903cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
910 cp.
code() = std::string(
"//AMOMAXD\n");
913cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
925rd += R_rd_0.read(ba) << 0;
928rs1 += R_rs1_0.read(ba) << 0;
931rs2 += R_rs2_0.read(ba) << 0;
934rl += R_rl_0.read(ba) << 0;
937aq += R_aq_0.read(ba) << 0;
941 std::stringstream ss;
943ss <<
"amomaxd" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
953 (uint64_t) 0xc000302f,
954 (uint64_t) 0xf800707f,
966rd += R_rd_0.
read(ba) << 0;
969rs1 += R_rs1_0.
read(ba) << 0;
972rs2 += R_rs2_0.
read(ba) << 0;
975rl += R_rl_0.
read(ba) << 0;
978aq += R_aq_0.
read(ba) << 0;
986 cp.
code() = std::string(
"//AMOMINUD\n");
989cp.
code() +=
"etiss_coverage_count(1, 233);\n";
991cp.
code() +=
"etiss_coverage_count(1, 1189);\n";
992cp.
code() +=
"{ // block\n";
994cp.
code() +=
"etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
995cp.
code() +=
"} // block\n";
998cp.
code() +=
"etiss_coverage_count(1, 9286);\n";
999cp.
code() +=
"{ // block\n";
1000cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
1001cp.
code() +=
"etiss_coverage_count(4, 9237, 9236, 9235, 9233);\n";
1002cp.
code() +=
"etiss_uint64 mem_val_0;\n";
1003cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
1004cp.
code() +=
"if (cpu->exception) { // conditional\n";
1006cp.
code() +=
"{ // procedure\n";
1007cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1009cp.
code() +=
"} // procedure\n";
1011cp.
code() +=
"} // conditional\n";
1012cp.
code() +=
"etiss_uint64 res = mem_val_0;\n";
1013cp.
code() +=
"etiss_coverage_count(5, 9245, 9244, 9242, 9240, 9241);\n";
1014cp.
code() +=
"etiss_coverage_count(1, 9246);\n";
1015if ((rd % 32ULL) != 0LL) {
1016cp.
code() +=
"etiss_coverage_count(5, 9252, 9249, 9247, 9250, 9251);\n";
1017cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = (etiss_int64)(res);\n";
1018cp.
code() +=
"etiss_coverage_count(6, 9261, 9257, 9256, 9254, 9260, 9258);\n";
1020cp.
code() +=
"etiss_uint64 res2 = (res > *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL]) : (res);\n";
1021cp.
code() +=
"etiss_coverage_count(11, 9277, 9276, 9269, 9263, 9268, 9267, 9265, 9274, 9273, 9271, 9275);\n";
1022cp.
code() +=
"etiss_uint64 mem_val_1;\n";
1023cp.
code() +=
"mem_val_1 = res2;\n";
1024cp.
code() +=
"etiss_coverage_count(6, 9285, 9283, 9281, 9279, 9280, 9284);\n";
1025cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
1026cp.
code() +=
"if (cpu->exception) { // conditional\n";
1028cp.
code() +=
"{ // procedure\n";
1029cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1031cp.
code() +=
"} // procedure\n";
1033cp.
code() +=
"} // conditional\n";
1034cp.
code() +=
"} // block\n";
1037cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
1044 cp.
code() = std::string(
"//AMOMINUD\n");
1047cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1059rd += R_rd_0.read(ba) << 0;
1062rs1 += R_rs1_0.read(ba) << 0;
1065rs2 += R_rs2_0.read(ba) << 0;
1068rl += R_rl_0.read(ba) << 0;
1071aq += R_aq_0.read(ba) << 0;
1075 std::stringstream ss;
1077ss <<
"amominud" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
1087 (uint64_t) 0xe000302f,
1088 (uint64_t) 0xf800707f,
1100rd += R_rd_0.
read(ba) << 0;
1103rs1 += R_rs1_0.
read(ba) << 0;
1106rs2 += R_rs2_0.
read(ba) << 0;
1109rl += R_rl_0.
read(ba) << 0;
1112aq += R_aq_0.
read(ba) << 0;
1120 cp.
code() = std::string(
"//AMOMAXUD\n");
1123cp.
code() +=
"etiss_coverage_count(1, 234);\n";
1125cp.
code() +=
"etiss_coverage_count(1, 1189);\n";
1126cp.
code() +=
"{ // block\n";
1128cp.
code() +=
"etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
1129cp.
code() +=
"} // block\n";
1132cp.
code() +=
"etiss_coverage_count(1, 9342);\n";
1133cp.
code() +=
"{ // block\n";
1134cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
1135cp.
code() +=
"etiss_coverage_count(4, 9293, 9292, 9291, 9289);\n";
1136cp.
code() +=
"etiss_uint64 mem_val_0;\n";
1137cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
1138cp.
code() +=
"if (cpu->exception) { // conditional\n";
1140cp.
code() +=
"{ // procedure\n";
1141cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1143cp.
code() +=
"} // procedure\n";
1145cp.
code() +=
"} // conditional\n";
1146cp.
code() +=
"etiss_uint64 res1 = mem_val_0;\n";
1147cp.
code() +=
"etiss_coverage_count(5, 9301, 9300, 9298, 9296, 9297);\n";
1148cp.
code() +=
"etiss_coverage_count(1, 9302);\n";
1149if ((rd % 32ULL) != 0LL) {
1150cp.
code() +=
"etiss_coverage_count(5, 9308, 9305, 9303, 9306, 9307);\n";
1151cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = (etiss_int64)(res1);\n";
1152cp.
code() +=
"etiss_coverage_count(6, 9317, 9313, 9312, 9310, 9316, 9314);\n";
1154cp.
code() +=
"etiss_uint64 res2 = (res1 < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL]) : (res1);\n";
1155cp.
code() +=
"etiss_coverage_count(11, 9333, 9332, 9325, 9319, 9324, 9323, 9321, 9330, 9329, 9327, 9331);\n";
1156cp.
code() +=
"etiss_uint64 mem_val_1;\n";
1157cp.
code() +=
"mem_val_1 = res2;\n";
1158cp.
code() +=
"etiss_coverage_count(6, 9341, 9339, 9337, 9335, 9336, 9340);\n";
1159cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
1160cp.
code() +=
"if (cpu->exception) { // conditional\n";
1162cp.
code() +=
"{ // procedure\n";
1163cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1165cp.
code() +=
"} // procedure\n";
1167cp.
code() +=
"} // conditional\n";
1168cp.
code() +=
"} // block\n";
1171cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
1178 cp.
code() = std::string(
"//AMOMAXUD\n");
1181cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1193rd += R_rd_0.read(ba) << 0;
1196rs1 += R_rs1_0.read(ba) << 0;
1199rs2 += R_rs2_0.read(ba) << 0;
1202rl += R_rl_0.read(ba) << 0;
1205aq += R_aq_0.read(ba) << 0;
1209 std::stringstream ss;
1211ss <<
"amomaxud" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
static InstructionDefinition amomaxud_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amomaxud",(uint64_t) 0xe000302f,(uint64_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOMAXUD\n");cp.code()+="etiss_coverage_count(1, 234);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 9342);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 9293, 9292, 9291, 9289);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint64 res1 = mem_val_0;\n";cp.code()+="etiss_coverage_count(5, 9301, 9300, 9298, 9296, 9297);\n";cp.code()+="etiss_coverage_count(1, 9302);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 9308, 9305, 9303, 9306, 9307);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(res1);\n";cp.code()+="etiss_coverage_count(6, 9317, 9313, 9312, 9310, 9316, 9314);\n";} cp.code()+="etiss_uint64 res2 = (res1 < *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) ? (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) : (res1);\n";cp.code()+="etiss_coverage_count(11, 9333, 9332, 9325, 9319, 9324, 9323, 9321, 9330, 9329, 9327, 9331);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(6, 9341, 9339, 9337, 9335, 9336, 9340);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOMAXUD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amomaxud"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amoxord_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoxord",(uint64_t) 0x2000302f,(uint64_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOXORD\n");cp.code()+="etiss_coverage_count(1, 228);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 9024);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 8984, 8983, 8982, 8980);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res = mem_val_0;\n";cp.code()+="etiss_coverage_count(5, 8992, 8991, 8989, 8987, 8988);\n";cp.code()+="etiss_coverage_count(1, 8993);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8999, 8996, 8994, 8997, 8998);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 9006, 9004, 9003, 9001, 9005);\n";} cp.code()+="etiss_uint64 res2 = res ^ *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(6, 9015, 9014, 9008, 9013, 9012, 9010);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(6, 9023, 9021, 9019, 9017, 9018, 9022);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOXORD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoxord"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amomaxd_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amomaxd",(uint64_t) 0xa000302f,(uint64_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOMAXD\n");cp.code()+="etiss_coverage_count(1, 232);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 9230);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 9181, 9180, 9179, 9177);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res = mem_val_0;\n";cp.code()+="etiss_coverage_count(5, 9189, 9188, 9186, 9184, 9185);\n";cp.code()+="etiss_coverage_count(1, 9190);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 9196, 9193, 9191, 9194, 9195);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 9203, 9201, 9200, 9198, 9202);\n";} cp.code()+="etiss_uint64 res2 = (res < (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) ? (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) : (res);\n";cp.code()+="etiss_coverage_count(12, 9221, 9220, 9213, 9205, 9212, 9210, 9209, 9207, 9218, 9217, 9215, 9219);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(6, 9229, 9227, 9225, 9223, 9224, 9228);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOMAXD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amomaxd"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amoaddd_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoaddd",(uint64_t) 0x00302f,(uint64_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOADDD\n");cp.code()+="etiss_coverage_count(1, 227);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8977);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 8937, 8936, 8935, 8933);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res = mem_val_0;\n";cp.code()+="etiss_coverage_count(5, 8945, 8944, 8942, 8940, 8941);\n";cp.code()+="etiss_coverage_count(1, 8946);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8952, 8949, 8947, 8950, 8951);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 8959, 8957, 8956, 8954, 8958);\n";} cp.code()+="etiss_uint64 res2 = res + *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(6, 8968, 8967, 8961, 8966, 8965, 8963);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(6, 8976, 8974, 8972, 8970, 8971, 8975);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOADDD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoaddd"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amoandd_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoandd",(uint64_t) 0x6000302f,(uint64_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOANDD\n");cp.code()+="etiss_coverage_count(1, 229);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 9071);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 9031, 9030, 9029, 9027);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res = mem_val_0;\n";cp.code()+="etiss_coverage_count(5, 9039, 9038, 9036, 9034, 9035);\n";cp.code()+="etiss_coverage_count(1, 9040);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 9046, 9043, 9041, 9044, 9045);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 9053, 9051, 9050, 9048, 9052);\n";} cp.code()+="etiss_uint64 res2 = res & *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(6, 9062, 9061, 9055, 9060, 9059, 9057);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(6, 9070, 9068, 9066, 9064, 9065, 9069);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOANDD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoandd"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amoswapd_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoswapd",(uint64_t) 0x800302f,(uint64_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOSWAPD\n");cp.code()+="etiss_coverage_count(1, 226);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8930);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 8891, 8890, 8889, 8887);\n";cp.code()+="etiss_coverage_count(1, 8892);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8898, 8895, 8893, 8896, 8897);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(((etiss_int64)(mem_val_0)));\n";cp.code()+="etiss_coverage_count(11, 8915, 8903, 8902, 8900, 8914, 8911, 8909, 8907, 8905, 8906, 8912);\n";} cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(9, 8929, 8921, 8919, 8917, 8918, 8928, 8926, 8925, 8923);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOSWAPD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoswapd"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amoord_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoord",(uint64_t) 0x4000302f,(uint64_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOORD\n");cp.code()+="etiss_coverage_count(1, 230);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 9118);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 9078, 9077, 9076, 9074);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res = mem_val_0;\n";cp.code()+="etiss_coverage_count(5, 9086, 9085, 9083, 9081, 9082);\n";cp.code()+="etiss_coverage_count(1, 9087);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 9093, 9090, 9088, 9091, 9092);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 9100, 9098, 9097, 9095, 9099);\n";} cp.code()+="etiss_uint64 res2 = res | *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(6, 9109, 9108, 9102, 9107, 9106, 9104);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(6, 9117, 9115, 9113, 9111, 9112, 9116);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOORD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoord"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amomind_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amomind",(uint64_t) 0x8000302f,(uint64_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOMIND\n");cp.code()+="etiss_coverage_count(1, 231);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 9174);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 9125, 9124, 9123, 9121);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res1 = mem_val_0;\n";cp.code()+="etiss_coverage_count(5, 9133, 9132, 9130, 9128, 9129);\n";cp.code()+="etiss_coverage_count(1, 9134);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 9140, 9137, 9135, 9138, 9139);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res1;\n";cp.code()+="etiss_coverage_count(5, 9147, 9145, 9144, 9142, 9146);\n";} cp.code()+="etiss_uint64 res2 = (res1 > (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) ? (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) : (res1);\n";cp.code()+="etiss_coverage_count(12, 9165, 9164, 9157, 9149, 9156, 9154, 9153, 9151, 9162, 9161, 9159, 9163);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(6, 9173, 9171, 9169, 9167, 9168, 9172);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOMIND\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amomind"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amominud_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amominud",(uint64_t) 0xc000302f,(uint64_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOMINUD\n");cp.code()+="etiss_coverage_count(1, 233);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 9286);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 9237, 9236, 9235, 9233);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint64 res = mem_val_0;\n";cp.code()+="etiss_coverage_count(5, 9245, 9244, 9242, 9240, 9241);\n";cp.code()+="etiss_coverage_count(1, 9246);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 9252, 9249, 9247, 9250, 9251);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(res);\n";cp.code()+="etiss_coverage_count(6, 9261, 9257, 9256, 9254, 9260, 9258);\n";} cp.code()+="etiss_uint64 res2 = (res > *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) ? (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) : (res);\n";cp.code()+="etiss_coverage_count(11, 9277, 9276, 9269, 9263, 9268, 9267, 9265, 9274, 9273, 9271, 9275);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(6, 9285, 9283, 9281, 9279, 9280, 9284);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOMINUD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amominud"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
Contains a small code snipped.
@ APPENDEDRETURNINGREQUIRED
RegisterSet & getAffectedRegisters()
void append(const CodePart &part, CodePart::TYPE type)
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Reading through it will only return bits within the range.
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
this class contains parameters that persist in between instruction lookpus/translation within a trans...
uint64_t current_address_
start address of current instruction
holds information and translation callbacks for an instruction.