ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV64IMACFD_RV64AInstr.cpp
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1 
8 #include "RV64IMACFDArch.h"
9 #include "RV64IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // AMOSWAPD --------------------------------------------------------------------
16 static InstructionDefinition amoswapd_rd_rs1_rs2_rl_aq (
17  ISA32_RV64IMACFD,
18  "amoswapd",
19  (uint32_t) 0x800302f,
20  (uint32_t) 0xf800707f,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 etiss_uint8 rd = 0;
30 static BitArrayRange R_rd_0(11, 7);
31 rd += R_rd_0.read(ba) << 0;
32 etiss_uint8 rs1 = 0;
33 static BitArrayRange R_rs1_0(19, 15);
34 rs1 += R_rs1_0.read(ba) << 0;
35 etiss_uint8 rs2 = 0;
36 static BitArrayRange R_rs2_0(24, 20);
37 rs2 += R_rs2_0.read(ba) << 0;
38 etiss_uint8 rl = 0;
39 static BitArrayRange R_rl_0(25, 25);
40 rl += R_rl_0.read(ba) << 0;
41 etiss_uint8 aq = 0;
42 static BitArrayRange R_aq_0(26, 26);
43 aq += R_aq_0.read(ba) << 0;
44 
45 // -----------------------------------------------------------------------------
46 
47  {
48  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
49 
50  cp.code() = std::string("//AMOSWAPD\n");
51 
52 // -----------------------------------------------------------------------------
53 { // block
54 cp.code() += "{ // block\n";
55 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
56 cp.code() += "} // block\n";
57 } // block
58 { // block
59 cp.code() += "{ // block\n";
60 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
61 if ((rd % 32ULL) != 0LL) { // conditional
62 cp.code() += "etiss_uint64 mem_val_0;\n";
63 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
64 cp.code() += "if (cpu->exception) { // conditional\n";
65 { // procedure
66 cp.code() += "{ // procedure\n";
67 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
68 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
69 cp.code() += "} // procedure\n";
70 } // procedure
71 cp.code() += "} // conditional\n";
72 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(((etiss_int64)(mem_val_0)));\n";
73 } // conditional
74 cp.code() += "etiss_uint64 mem_val_1;\n";
75 cp.code() += "mem_val_1 = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
76 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
77 cp.code() += "if (cpu->exception) { // conditional\n";
78 { // procedure
79 cp.code() += "{ // procedure\n";
80 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
81 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
82 cp.code() += "} // procedure\n";
83 } // procedure
84 cp.code() += "} // conditional\n";
85 cp.code() += "} // block\n";
86 } // block
87 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
88 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
89 // -----------------------------------------------------------------------------
90  cp.getAffectedRegisters().add("instructionPointer", 32);
91  }
92  {
93  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
94 
95  cp.code() = std::string("//AMOSWAPD\n");
96 
97 // -----------------------------------------------------------------------------
98 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
99 // -----------------------------------------------------------------------------
100  }
101 
102  return true;
103  },
104  0,
105  [] (BitArray & ba, Instruction & instr)
106  {
107 // -----------------------------------------------------------------------------
108 etiss_uint8 rd = 0;
109 static BitArrayRange R_rd_0(11, 7);
110 rd += R_rd_0.read(ba) << 0;
111 etiss_uint8 rs1 = 0;
112 static BitArrayRange R_rs1_0(19, 15);
113 rs1 += R_rs1_0.read(ba) << 0;
114 etiss_uint8 rs2 = 0;
115 static BitArrayRange R_rs2_0(24, 20);
116 rs2 += R_rs2_0.read(ba) << 0;
117 etiss_uint8 rl = 0;
118 static BitArrayRange R_rl_0(25, 25);
119 rl += R_rl_0.read(ba) << 0;
120 etiss_uint8 aq = 0;
121 static BitArrayRange R_aq_0(26, 26);
122 aq += R_aq_0.read(ba) << 0;
123 
124 // -----------------------------------------------------------------------------
125 
126  std::stringstream ss;
127 // -----------------------------------------------------------------------------
128 ss << "amoswapd" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
129 // -----------------------------------------------------------------------------
130  return ss.str();
131  }
132 );
133 
134 // AMOADDD ---------------------------------------------------------------------
135 static InstructionDefinition amoaddd_rd_rs1_rs2_rl_aq (
136  ISA32_RV64IMACFD,
137  "amoaddd",
138  (uint32_t) 0x00302f,
139  (uint32_t) 0xf800707f,
140  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
141  {
142 
143 // -----------------------------------------------------------------------------
144 
145 // -----------------------------------------------------------------------------
146 
147 // -----------------------------------------------------------------------------
148 etiss_uint8 rd = 0;
149 static BitArrayRange R_rd_0(11, 7);
150 rd += R_rd_0.read(ba) << 0;
151 etiss_uint8 rs1 = 0;
152 static BitArrayRange R_rs1_0(19, 15);
153 rs1 += R_rs1_0.read(ba) << 0;
154 etiss_uint8 rs2 = 0;
155 static BitArrayRange R_rs2_0(24, 20);
156 rs2 += R_rs2_0.read(ba) << 0;
157 etiss_uint8 rl = 0;
158 static BitArrayRange R_rl_0(25, 25);
159 rl += R_rl_0.read(ba) << 0;
160 etiss_uint8 aq = 0;
161 static BitArrayRange R_aq_0(26, 26);
162 aq += R_aq_0.read(ba) << 0;
163 
164 // -----------------------------------------------------------------------------
165 
166  {
167  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
168 
169  cp.code() = std::string("//AMOADDD\n");
170 
171 // -----------------------------------------------------------------------------
172 { // block
173 cp.code() += "{ // block\n";
174 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
175 cp.code() += "} // block\n";
176 } // block
177 { // block
178 cp.code() += "{ // block\n";
179 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
180 cp.code() += "etiss_uint64 mem_val_0;\n";
181 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
182 cp.code() += "if (cpu->exception) { // conditional\n";
183 { // procedure
184 cp.code() += "{ // procedure\n";
185 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
186 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
187 cp.code() += "} // procedure\n";
188 } // procedure
189 cp.code() += "} // conditional\n";
190 cp.code() += "etiss_int64 res = mem_val_0;\n";
191 if ((rd % 32ULL) != 0LL) { // conditional
192 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
193 } // conditional
194 cp.code() += "etiss_uint64 res2 = res + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
195 cp.code() += "etiss_uint64 mem_val_1;\n";
196 cp.code() += "mem_val_1 = res2;\n";
197 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
198 cp.code() += "if (cpu->exception) { // conditional\n";
199 { // procedure
200 cp.code() += "{ // procedure\n";
201 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
202 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
203 cp.code() += "} // procedure\n";
204 } // procedure
205 cp.code() += "} // conditional\n";
206 cp.code() += "} // block\n";
207 } // block
208 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
209 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
210 // -----------------------------------------------------------------------------
211  cp.getAffectedRegisters().add("instructionPointer", 32);
212  }
213  {
214  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
215 
216  cp.code() = std::string("//AMOADDD\n");
217 
218 // -----------------------------------------------------------------------------
219 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
220 // -----------------------------------------------------------------------------
221  }
222 
223  return true;
224  },
225  0,
226  [] (BitArray & ba, Instruction & instr)
227  {
228 // -----------------------------------------------------------------------------
229 etiss_uint8 rd = 0;
230 static BitArrayRange R_rd_0(11, 7);
231 rd += R_rd_0.read(ba) << 0;
232 etiss_uint8 rs1 = 0;
233 static BitArrayRange R_rs1_0(19, 15);
234 rs1 += R_rs1_0.read(ba) << 0;
235 etiss_uint8 rs2 = 0;
236 static BitArrayRange R_rs2_0(24, 20);
237 rs2 += R_rs2_0.read(ba) << 0;
238 etiss_uint8 rl = 0;
239 static BitArrayRange R_rl_0(25, 25);
240 rl += R_rl_0.read(ba) << 0;
241 etiss_uint8 aq = 0;
242 static BitArrayRange R_aq_0(26, 26);
243 aq += R_aq_0.read(ba) << 0;
244 
245 // -----------------------------------------------------------------------------
246 
247  std::stringstream ss;
248 // -----------------------------------------------------------------------------
249 ss << "amoaddd" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
250 // -----------------------------------------------------------------------------
251  return ss.str();
252  }
253 );
254 
255 // AMOXORD ---------------------------------------------------------------------
256 static InstructionDefinition amoxord_rd_rs1_rs2_rl_aq (
257  ISA32_RV64IMACFD,
258  "amoxord",
259  (uint32_t) 0x2000302f,
260  (uint32_t) 0xf800707f,
261  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
262  {
263 
264 // -----------------------------------------------------------------------------
265 
266 // -----------------------------------------------------------------------------
267 
268 // -----------------------------------------------------------------------------
269 etiss_uint8 rd = 0;
270 static BitArrayRange R_rd_0(11, 7);
271 rd += R_rd_0.read(ba) << 0;
272 etiss_uint8 rs1 = 0;
273 static BitArrayRange R_rs1_0(19, 15);
274 rs1 += R_rs1_0.read(ba) << 0;
275 etiss_uint8 rs2 = 0;
276 static BitArrayRange R_rs2_0(24, 20);
277 rs2 += R_rs2_0.read(ba) << 0;
278 etiss_uint8 rl = 0;
279 static BitArrayRange R_rl_0(25, 25);
280 rl += R_rl_0.read(ba) << 0;
281 etiss_uint8 aq = 0;
282 static BitArrayRange R_aq_0(26, 26);
283 aq += R_aq_0.read(ba) << 0;
284 
285 // -----------------------------------------------------------------------------
286 
287  {
288  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
289 
290  cp.code() = std::string("//AMOXORD\n");
291 
292 // -----------------------------------------------------------------------------
293 { // block
294 cp.code() += "{ // block\n";
295 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
296 cp.code() += "} // block\n";
297 } // block
298 { // block
299 cp.code() += "{ // block\n";
300 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
301 cp.code() += "etiss_uint64 mem_val_0;\n";
302 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
303 cp.code() += "if (cpu->exception) { // conditional\n";
304 { // procedure
305 cp.code() += "{ // procedure\n";
306 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
307 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
308 cp.code() += "} // procedure\n";
309 } // procedure
310 cp.code() += "} // conditional\n";
311 cp.code() += "etiss_int64 res = mem_val_0;\n";
312 if ((rd % 32ULL) != 0LL) { // conditional
313 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
314 } // conditional
315 cp.code() += "etiss_uint64 res2 = res ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
316 cp.code() += "etiss_uint64 mem_val_1;\n";
317 cp.code() += "mem_val_1 = res2;\n";
318 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
319 cp.code() += "if (cpu->exception) { // conditional\n";
320 { // procedure
321 cp.code() += "{ // procedure\n";
322 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
323 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
324 cp.code() += "} // procedure\n";
325 } // procedure
326 cp.code() += "} // conditional\n";
327 cp.code() += "} // block\n";
328 } // block
329 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
330 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
331 // -----------------------------------------------------------------------------
332  cp.getAffectedRegisters().add("instructionPointer", 32);
333  }
334  {
335  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
336 
337  cp.code() = std::string("//AMOXORD\n");
338 
339 // -----------------------------------------------------------------------------
340 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
341 // -----------------------------------------------------------------------------
342  }
343 
344  return true;
345  },
346  0,
347  [] (BitArray & ba, Instruction & instr)
348  {
349 // -----------------------------------------------------------------------------
350 etiss_uint8 rd = 0;
351 static BitArrayRange R_rd_0(11, 7);
352 rd += R_rd_0.read(ba) << 0;
353 etiss_uint8 rs1 = 0;
354 static BitArrayRange R_rs1_0(19, 15);
355 rs1 += R_rs1_0.read(ba) << 0;
356 etiss_uint8 rs2 = 0;
357 static BitArrayRange R_rs2_0(24, 20);
358 rs2 += R_rs2_0.read(ba) << 0;
359 etiss_uint8 rl = 0;
360 static BitArrayRange R_rl_0(25, 25);
361 rl += R_rl_0.read(ba) << 0;
362 etiss_uint8 aq = 0;
363 static BitArrayRange R_aq_0(26, 26);
364 aq += R_aq_0.read(ba) << 0;
365 
366 // -----------------------------------------------------------------------------
367 
368  std::stringstream ss;
369 // -----------------------------------------------------------------------------
370 ss << "amoxord" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
371 // -----------------------------------------------------------------------------
372  return ss.str();
373  }
374 );
375 
376 // AMOANDD ---------------------------------------------------------------------
377 static InstructionDefinition amoandd_rd_rs1_rs2_rl_aq (
378  ISA32_RV64IMACFD,
379  "amoandd",
380  (uint32_t) 0x6000302f,
381  (uint32_t) 0xf800707f,
382  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
383  {
384 
385 // -----------------------------------------------------------------------------
386 
387 // -----------------------------------------------------------------------------
388 
389 // -----------------------------------------------------------------------------
390 etiss_uint8 rd = 0;
391 static BitArrayRange R_rd_0(11, 7);
392 rd += R_rd_0.read(ba) << 0;
393 etiss_uint8 rs1 = 0;
394 static BitArrayRange R_rs1_0(19, 15);
395 rs1 += R_rs1_0.read(ba) << 0;
396 etiss_uint8 rs2 = 0;
397 static BitArrayRange R_rs2_0(24, 20);
398 rs2 += R_rs2_0.read(ba) << 0;
399 etiss_uint8 rl = 0;
400 static BitArrayRange R_rl_0(25, 25);
401 rl += R_rl_0.read(ba) << 0;
402 etiss_uint8 aq = 0;
403 static BitArrayRange R_aq_0(26, 26);
404 aq += R_aq_0.read(ba) << 0;
405 
406 // -----------------------------------------------------------------------------
407 
408  {
409  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
410 
411  cp.code() = std::string("//AMOANDD\n");
412 
413 // -----------------------------------------------------------------------------
414 { // block
415 cp.code() += "{ // block\n";
416 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
417 cp.code() += "} // block\n";
418 } // block
419 { // block
420 cp.code() += "{ // block\n";
421 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
422 cp.code() += "etiss_uint64 mem_val_0;\n";
423 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
424 cp.code() += "if (cpu->exception) { // conditional\n";
425 { // procedure
426 cp.code() += "{ // procedure\n";
427 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
428 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
429 cp.code() += "} // procedure\n";
430 } // procedure
431 cp.code() += "} // conditional\n";
432 cp.code() += "etiss_int64 res = mem_val_0;\n";
433 if ((rd % 32ULL) != 0LL) { // conditional
434 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
435 } // conditional
436 cp.code() += "etiss_uint64 res2 = res & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
437 cp.code() += "etiss_uint64 mem_val_1;\n";
438 cp.code() += "mem_val_1 = res2;\n";
439 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
440 cp.code() += "if (cpu->exception) { // conditional\n";
441 { // procedure
442 cp.code() += "{ // procedure\n";
443 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
444 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
445 cp.code() += "} // procedure\n";
446 } // procedure
447 cp.code() += "} // conditional\n";
448 cp.code() += "} // block\n";
449 } // block
450 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
451 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
452 // -----------------------------------------------------------------------------
453  cp.getAffectedRegisters().add("instructionPointer", 32);
454  }
455  {
456  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
457 
458  cp.code() = std::string("//AMOANDD\n");
459 
460 // -----------------------------------------------------------------------------
461 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
462 // -----------------------------------------------------------------------------
463  }
464 
465  return true;
466  },
467  0,
468  [] (BitArray & ba, Instruction & instr)
469  {
470 // -----------------------------------------------------------------------------
471 etiss_uint8 rd = 0;
472 static BitArrayRange R_rd_0(11, 7);
473 rd += R_rd_0.read(ba) << 0;
474 etiss_uint8 rs1 = 0;
475 static BitArrayRange R_rs1_0(19, 15);
476 rs1 += R_rs1_0.read(ba) << 0;
477 etiss_uint8 rs2 = 0;
478 static BitArrayRange R_rs2_0(24, 20);
479 rs2 += R_rs2_0.read(ba) << 0;
480 etiss_uint8 rl = 0;
481 static BitArrayRange R_rl_0(25, 25);
482 rl += R_rl_0.read(ba) << 0;
483 etiss_uint8 aq = 0;
484 static BitArrayRange R_aq_0(26, 26);
485 aq += R_aq_0.read(ba) << 0;
486 
487 // -----------------------------------------------------------------------------
488 
489  std::stringstream ss;
490 // -----------------------------------------------------------------------------
491 ss << "amoandd" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
492 // -----------------------------------------------------------------------------
493  return ss.str();
494  }
495 );
496 
497 // AMOORD ----------------------------------------------------------------------
498 static InstructionDefinition amoord_rd_rs1_rs2_rl_aq (
499  ISA32_RV64IMACFD,
500  "amoord",
501  (uint32_t) 0x4000302f,
502  (uint32_t) 0xf800707f,
503  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
504  {
505 
506 // -----------------------------------------------------------------------------
507 
508 // -----------------------------------------------------------------------------
509 
510 // -----------------------------------------------------------------------------
511 etiss_uint8 rd = 0;
512 static BitArrayRange R_rd_0(11, 7);
513 rd += R_rd_0.read(ba) << 0;
514 etiss_uint8 rs1 = 0;
515 static BitArrayRange R_rs1_0(19, 15);
516 rs1 += R_rs1_0.read(ba) << 0;
517 etiss_uint8 rs2 = 0;
518 static BitArrayRange R_rs2_0(24, 20);
519 rs2 += R_rs2_0.read(ba) << 0;
520 etiss_uint8 rl = 0;
521 static BitArrayRange R_rl_0(25, 25);
522 rl += R_rl_0.read(ba) << 0;
523 etiss_uint8 aq = 0;
524 static BitArrayRange R_aq_0(26, 26);
525 aq += R_aq_0.read(ba) << 0;
526 
527 // -----------------------------------------------------------------------------
528 
529  {
530  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
531 
532  cp.code() = std::string("//AMOORD\n");
533 
534 // -----------------------------------------------------------------------------
535 { // block
536 cp.code() += "{ // block\n";
537 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
538 cp.code() += "} // block\n";
539 } // block
540 { // block
541 cp.code() += "{ // block\n";
542 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
543 cp.code() += "etiss_uint64 mem_val_0;\n";
544 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
545 cp.code() += "if (cpu->exception) { // conditional\n";
546 { // procedure
547 cp.code() += "{ // procedure\n";
548 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
549 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
550 cp.code() += "} // procedure\n";
551 } // procedure
552 cp.code() += "} // conditional\n";
553 cp.code() += "etiss_int64 res = mem_val_0;\n";
554 if ((rd % 32ULL) != 0LL) { // conditional
555 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
556 } // conditional
557 cp.code() += "etiss_uint64 res2 = res | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
558 cp.code() += "etiss_uint64 mem_val_1;\n";
559 cp.code() += "mem_val_1 = res2;\n";
560 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
561 cp.code() += "if (cpu->exception) { // conditional\n";
562 { // procedure
563 cp.code() += "{ // procedure\n";
564 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
565 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
566 cp.code() += "} // procedure\n";
567 } // procedure
568 cp.code() += "} // conditional\n";
569 cp.code() += "} // block\n";
570 } // block
571 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
572 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
573 // -----------------------------------------------------------------------------
574  cp.getAffectedRegisters().add("instructionPointer", 32);
575  }
576  {
577  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
578 
579  cp.code() = std::string("//AMOORD\n");
580 
581 // -----------------------------------------------------------------------------
582 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
583 // -----------------------------------------------------------------------------
584  }
585 
586  return true;
587  },
588  0,
589  [] (BitArray & ba, Instruction & instr)
590  {
591 // -----------------------------------------------------------------------------
592 etiss_uint8 rd = 0;
593 static BitArrayRange R_rd_0(11, 7);
594 rd += R_rd_0.read(ba) << 0;
595 etiss_uint8 rs1 = 0;
596 static BitArrayRange R_rs1_0(19, 15);
597 rs1 += R_rs1_0.read(ba) << 0;
598 etiss_uint8 rs2 = 0;
599 static BitArrayRange R_rs2_0(24, 20);
600 rs2 += R_rs2_0.read(ba) << 0;
601 etiss_uint8 rl = 0;
602 static BitArrayRange R_rl_0(25, 25);
603 rl += R_rl_0.read(ba) << 0;
604 etiss_uint8 aq = 0;
605 static BitArrayRange R_aq_0(26, 26);
606 aq += R_aq_0.read(ba) << 0;
607 
608 // -----------------------------------------------------------------------------
609 
610  std::stringstream ss;
611 // -----------------------------------------------------------------------------
612 ss << "amoord" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
613 // -----------------------------------------------------------------------------
614  return ss.str();
615  }
616 );
617 
618 // AMOMIND ---------------------------------------------------------------------
619 static InstructionDefinition amomind_rd_rs1_rs2_rl_aq (
620  ISA32_RV64IMACFD,
621  "amomind",
622  (uint32_t) 0x8000302f,
623  (uint32_t) 0xf800707f,
624  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
625  {
626 
627 // -----------------------------------------------------------------------------
628 
629 // -----------------------------------------------------------------------------
630 
631 // -----------------------------------------------------------------------------
632 etiss_uint8 rd = 0;
633 static BitArrayRange R_rd_0(11, 7);
634 rd += R_rd_0.read(ba) << 0;
635 etiss_uint8 rs1 = 0;
636 static BitArrayRange R_rs1_0(19, 15);
637 rs1 += R_rs1_0.read(ba) << 0;
638 etiss_uint8 rs2 = 0;
639 static BitArrayRange R_rs2_0(24, 20);
640 rs2 += R_rs2_0.read(ba) << 0;
641 etiss_uint8 rl = 0;
642 static BitArrayRange R_rl_0(25, 25);
643 rl += R_rl_0.read(ba) << 0;
644 etiss_uint8 aq = 0;
645 static BitArrayRange R_aq_0(26, 26);
646 aq += R_aq_0.read(ba) << 0;
647 
648 // -----------------------------------------------------------------------------
649 
650  {
651  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
652 
653  cp.code() = std::string("//AMOMIND\n");
654 
655 // -----------------------------------------------------------------------------
656 { // block
657 cp.code() += "{ // block\n";
658 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
659 cp.code() += "} // block\n";
660 } // block
661 { // block
662 cp.code() += "{ // block\n";
663 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
664 cp.code() += "etiss_uint64 mem_val_0;\n";
665 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
666 cp.code() += "if (cpu->exception) { // conditional\n";
667 { // procedure
668 cp.code() += "{ // procedure\n";
669 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
670 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
671 cp.code() += "} // procedure\n";
672 } // procedure
673 cp.code() += "} // conditional\n";
674 cp.code() += "etiss_int64 res1 = mem_val_0;\n";
675 if ((rd % 32ULL) != 0LL) { // conditional
676 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res1;\n";
677 } // conditional
678 cp.code() += "etiss_uint64 res2 = (res1 > (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res1);\n";
679 cp.code() += "etiss_uint64 mem_val_1;\n";
680 cp.code() += "mem_val_1 = res2;\n";
681 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
682 cp.code() += "if (cpu->exception) { // conditional\n";
683 { // procedure
684 cp.code() += "{ // procedure\n";
685 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
686 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
687 cp.code() += "} // procedure\n";
688 } // procedure
689 cp.code() += "} // conditional\n";
690 cp.code() += "} // block\n";
691 } // block
692 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
693 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
694 // -----------------------------------------------------------------------------
695  cp.getAffectedRegisters().add("instructionPointer", 32);
696  }
697  {
698  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
699 
700  cp.code() = std::string("//AMOMIND\n");
701 
702 // -----------------------------------------------------------------------------
703 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
704 // -----------------------------------------------------------------------------
705  }
706 
707  return true;
708  },
709  0,
710  [] (BitArray & ba, Instruction & instr)
711  {
712 // -----------------------------------------------------------------------------
713 etiss_uint8 rd = 0;
714 static BitArrayRange R_rd_0(11, 7);
715 rd += R_rd_0.read(ba) << 0;
716 etiss_uint8 rs1 = 0;
717 static BitArrayRange R_rs1_0(19, 15);
718 rs1 += R_rs1_0.read(ba) << 0;
719 etiss_uint8 rs2 = 0;
720 static BitArrayRange R_rs2_0(24, 20);
721 rs2 += R_rs2_0.read(ba) << 0;
722 etiss_uint8 rl = 0;
723 static BitArrayRange R_rl_0(25, 25);
724 rl += R_rl_0.read(ba) << 0;
725 etiss_uint8 aq = 0;
726 static BitArrayRange R_aq_0(26, 26);
727 aq += R_aq_0.read(ba) << 0;
728 
729 // -----------------------------------------------------------------------------
730 
731  std::stringstream ss;
732 // -----------------------------------------------------------------------------
733 ss << "amomind" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
734 // -----------------------------------------------------------------------------
735  return ss.str();
736  }
737 );
738 
739 // AMOMAXD ---------------------------------------------------------------------
740 static InstructionDefinition amomaxd_rd_rs1_rs2_rl_aq (
741  ISA32_RV64IMACFD,
742  "amomaxd",
743  (uint32_t) 0xa000302f,
744  (uint32_t) 0xf800707f,
745  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
746  {
747 
748 // -----------------------------------------------------------------------------
749 
750 // -----------------------------------------------------------------------------
751 
752 // -----------------------------------------------------------------------------
753 etiss_uint8 rd = 0;
754 static BitArrayRange R_rd_0(11, 7);
755 rd += R_rd_0.read(ba) << 0;
756 etiss_uint8 rs1 = 0;
757 static BitArrayRange R_rs1_0(19, 15);
758 rs1 += R_rs1_0.read(ba) << 0;
759 etiss_uint8 rs2 = 0;
760 static BitArrayRange R_rs2_0(24, 20);
761 rs2 += R_rs2_0.read(ba) << 0;
762 etiss_uint8 rl = 0;
763 static BitArrayRange R_rl_0(25, 25);
764 rl += R_rl_0.read(ba) << 0;
765 etiss_uint8 aq = 0;
766 static BitArrayRange R_aq_0(26, 26);
767 aq += R_aq_0.read(ba) << 0;
768 
769 // -----------------------------------------------------------------------------
770 
771  {
772  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
773 
774  cp.code() = std::string("//AMOMAXD\n");
775 
776 // -----------------------------------------------------------------------------
777 { // block
778 cp.code() += "{ // block\n";
779 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
780 cp.code() += "} // block\n";
781 } // block
782 { // block
783 cp.code() += "{ // block\n";
784 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
785 cp.code() += "etiss_uint64 mem_val_0;\n";
786 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
787 cp.code() += "if (cpu->exception) { // conditional\n";
788 { // procedure
789 cp.code() += "{ // procedure\n";
790 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
791 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
792 cp.code() += "} // procedure\n";
793 } // procedure
794 cp.code() += "} // conditional\n";
795 cp.code() += "etiss_int64 res = mem_val_0;\n";
796 if ((rd % 32ULL) != 0LL) { // conditional
797 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
798 } // conditional
799 cp.code() += "etiss_uint64 res2 = (res < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res);\n";
800 cp.code() += "etiss_uint64 mem_val_1;\n";
801 cp.code() += "mem_val_1 = res2;\n";
802 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
803 cp.code() += "if (cpu->exception) { // conditional\n";
804 { // procedure
805 cp.code() += "{ // procedure\n";
806 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
807 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
808 cp.code() += "} // procedure\n";
809 } // procedure
810 cp.code() += "} // conditional\n";
811 cp.code() += "} // block\n";
812 } // block
813 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
814 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
815 // -----------------------------------------------------------------------------
816  cp.getAffectedRegisters().add("instructionPointer", 32);
817  }
818  {
819  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
820 
821  cp.code() = std::string("//AMOMAXD\n");
822 
823 // -----------------------------------------------------------------------------
824 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
825 // -----------------------------------------------------------------------------
826  }
827 
828  return true;
829  },
830  0,
831  [] (BitArray & ba, Instruction & instr)
832  {
833 // -----------------------------------------------------------------------------
834 etiss_uint8 rd = 0;
835 static BitArrayRange R_rd_0(11, 7);
836 rd += R_rd_0.read(ba) << 0;
837 etiss_uint8 rs1 = 0;
838 static BitArrayRange R_rs1_0(19, 15);
839 rs1 += R_rs1_0.read(ba) << 0;
840 etiss_uint8 rs2 = 0;
841 static BitArrayRange R_rs2_0(24, 20);
842 rs2 += R_rs2_0.read(ba) << 0;
843 etiss_uint8 rl = 0;
844 static BitArrayRange R_rl_0(25, 25);
845 rl += R_rl_0.read(ba) << 0;
846 etiss_uint8 aq = 0;
847 static BitArrayRange R_aq_0(26, 26);
848 aq += R_aq_0.read(ba) << 0;
849 
850 // -----------------------------------------------------------------------------
851 
852  std::stringstream ss;
853 // -----------------------------------------------------------------------------
854 ss << "amomaxd" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
855 // -----------------------------------------------------------------------------
856  return ss.str();
857  }
858 );
859 
860 // AMOMINUD --------------------------------------------------------------------
861 static InstructionDefinition amominud_rd_rs1_rs2_rl_aq (
862  ISA32_RV64IMACFD,
863  "amominud",
864  (uint32_t) 0xc000302f,
865  (uint32_t) 0xf800707f,
866  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
867  {
868 
869 // -----------------------------------------------------------------------------
870 
871 // -----------------------------------------------------------------------------
872 
873 // -----------------------------------------------------------------------------
874 etiss_uint8 rd = 0;
875 static BitArrayRange R_rd_0(11, 7);
876 rd += R_rd_0.read(ba) << 0;
877 etiss_uint8 rs1 = 0;
878 static BitArrayRange R_rs1_0(19, 15);
879 rs1 += R_rs1_0.read(ba) << 0;
880 etiss_uint8 rs2 = 0;
881 static BitArrayRange R_rs2_0(24, 20);
882 rs2 += R_rs2_0.read(ba) << 0;
883 etiss_uint8 rl = 0;
884 static BitArrayRange R_rl_0(25, 25);
885 rl += R_rl_0.read(ba) << 0;
886 etiss_uint8 aq = 0;
887 static BitArrayRange R_aq_0(26, 26);
888 aq += R_aq_0.read(ba) << 0;
889 
890 // -----------------------------------------------------------------------------
891 
892  {
893  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
894 
895  cp.code() = std::string("//AMOMINUD\n");
896 
897 // -----------------------------------------------------------------------------
898 { // block
899 cp.code() += "{ // block\n";
900 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
901 cp.code() += "} // block\n";
902 } // block
903 { // block
904 cp.code() += "{ // block\n";
905 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
906 cp.code() += "etiss_uint64 mem_val_0;\n";
907 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
908 cp.code() += "if (cpu->exception) { // conditional\n";
909 { // procedure
910 cp.code() += "{ // procedure\n";
911 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
912 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
913 cp.code() += "} // procedure\n";
914 } // procedure
915 cp.code() += "} // conditional\n";
916 cp.code() += "etiss_uint64 res = mem_val_0;\n";
917 if ((rd % 32ULL) != 0LL) { // conditional
918 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res);\n";
919 } // conditional
920 cp.code() += "etiss_uint64 res2 = (res > *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res);\n";
921 cp.code() += "etiss_uint64 mem_val_1;\n";
922 cp.code() += "mem_val_1 = res2;\n";
923 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
924 cp.code() += "if (cpu->exception) { // conditional\n";
925 { // procedure
926 cp.code() += "{ // procedure\n";
927 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
928 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
929 cp.code() += "} // procedure\n";
930 } // procedure
931 cp.code() += "} // conditional\n";
932 cp.code() += "} // block\n";
933 } // block
934 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
935 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
936 // -----------------------------------------------------------------------------
937  cp.getAffectedRegisters().add("instructionPointer", 32);
938  }
939  {
940  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
941 
942  cp.code() = std::string("//AMOMINUD\n");
943 
944 // -----------------------------------------------------------------------------
945 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
946 // -----------------------------------------------------------------------------
947  }
948 
949  return true;
950  },
951  0,
952  [] (BitArray & ba, Instruction & instr)
953  {
954 // -----------------------------------------------------------------------------
955 etiss_uint8 rd = 0;
956 static BitArrayRange R_rd_0(11, 7);
957 rd += R_rd_0.read(ba) << 0;
958 etiss_uint8 rs1 = 0;
959 static BitArrayRange R_rs1_0(19, 15);
960 rs1 += R_rs1_0.read(ba) << 0;
961 etiss_uint8 rs2 = 0;
962 static BitArrayRange R_rs2_0(24, 20);
963 rs2 += R_rs2_0.read(ba) << 0;
964 etiss_uint8 rl = 0;
965 static BitArrayRange R_rl_0(25, 25);
966 rl += R_rl_0.read(ba) << 0;
967 etiss_uint8 aq = 0;
968 static BitArrayRange R_aq_0(26, 26);
969 aq += R_aq_0.read(ba) << 0;
970 
971 // -----------------------------------------------------------------------------
972 
973  std::stringstream ss;
974 // -----------------------------------------------------------------------------
975 ss << "amominud" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
976 // -----------------------------------------------------------------------------
977  return ss.str();
978  }
979 );
980 
981 // AMOMAXUD --------------------------------------------------------------------
982 static InstructionDefinition amomaxud_rd_rs1_rs2_rl_aq (
983  ISA32_RV64IMACFD,
984  "amomaxud",
985  (uint32_t) 0xe000302f,
986  (uint32_t) 0xf800707f,
987  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
988  {
989 
990 // -----------------------------------------------------------------------------
991 
992 // -----------------------------------------------------------------------------
993 
994 // -----------------------------------------------------------------------------
995 etiss_uint8 rd = 0;
996 static BitArrayRange R_rd_0(11, 7);
997 rd += R_rd_0.read(ba) << 0;
998 etiss_uint8 rs1 = 0;
999 static BitArrayRange R_rs1_0(19, 15);
1000 rs1 += R_rs1_0.read(ba) << 0;
1001 etiss_uint8 rs2 = 0;
1002 static BitArrayRange R_rs2_0(24, 20);
1003 rs2 += R_rs2_0.read(ba) << 0;
1004 etiss_uint8 rl = 0;
1005 static BitArrayRange R_rl_0(25, 25);
1006 rl += R_rl_0.read(ba) << 0;
1007 etiss_uint8 aq = 0;
1008 static BitArrayRange R_aq_0(26, 26);
1009 aq += R_aq_0.read(ba) << 0;
1010 
1011 // -----------------------------------------------------------------------------
1012 
1013  {
1014  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1015 
1016  cp.code() = std::string("//AMOMAXUD\n");
1017 
1018 // -----------------------------------------------------------------------------
1019 { // block
1020 cp.code() += "{ // block\n";
1021 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1022 cp.code() += "} // block\n";
1023 } // block
1024 { // block
1025 cp.code() += "{ // block\n";
1026 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
1027 cp.code() += "etiss_uint64 mem_val_0;\n";
1028 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
1029 cp.code() += "if (cpu->exception) { // conditional\n";
1030 { // procedure
1031 cp.code() += "{ // procedure\n";
1032 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1033 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1034 cp.code() += "} // procedure\n";
1035 } // procedure
1036 cp.code() += "} // conditional\n";
1037 cp.code() += "etiss_uint64 res1 = mem_val_0;\n";
1038 if ((rd % 32ULL) != 0LL) { // conditional
1039 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res1);\n";
1040 } // conditional
1041 cp.code() += "etiss_uint64 res2 = (res1 < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res1);\n";
1042 cp.code() += "etiss_uint64 mem_val_1;\n";
1043 cp.code() += "mem_val_1 = res2;\n";
1044 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
1045 cp.code() += "if (cpu->exception) { // conditional\n";
1046 { // procedure
1047 cp.code() += "{ // procedure\n";
1048 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1049 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1050 cp.code() += "} // procedure\n";
1051 } // procedure
1052 cp.code() += "} // conditional\n";
1053 cp.code() += "} // block\n";
1054 } // block
1055 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1056 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1057 // -----------------------------------------------------------------------------
1058  cp.getAffectedRegisters().add("instructionPointer", 32);
1059  }
1060  {
1061  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1062 
1063  cp.code() = std::string("//AMOMAXUD\n");
1064 
1065 // -----------------------------------------------------------------------------
1066 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1067 // -----------------------------------------------------------------------------
1068  }
1069 
1070  return true;
1071  },
1072  0,
1073  [] (BitArray & ba, Instruction & instr)
1074  {
1075 // -----------------------------------------------------------------------------
1076 etiss_uint8 rd = 0;
1077 static BitArrayRange R_rd_0(11, 7);
1078 rd += R_rd_0.read(ba) << 0;
1079 etiss_uint8 rs1 = 0;
1080 static BitArrayRange R_rs1_0(19, 15);
1081 rs1 += R_rs1_0.read(ba) << 0;
1082 etiss_uint8 rs2 = 0;
1083 static BitArrayRange R_rs2_0(24, 20);
1084 rs2 += R_rs2_0.read(ba) << 0;
1085 etiss_uint8 rl = 0;
1086 static BitArrayRange R_rl_0(25, 25);
1087 rl += R_rl_0.read(ba) << 0;
1088 etiss_uint8 aq = 0;
1089 static BitArrayRange R_aq_0(26, 26);
1090 aq += R_aq_0.read(ba) << 0;
1091 
1092 // -----------------------------------------------------------------------------
1093 
1094  std::stringstream ss;
1095 // -----------------------------------------------------------------------------
1096 ss << "amomaxud" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
1097 // -----------------------------------------------------------------------------
1098  return ss.str();
1099  }
1100 );
ISA32_RV64IMACFD
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
amoxord_rd_rs1_rs2_rl_aq
static InstructionDefinition amoxord_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoxord",(uint32_t) 0x2000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOXORD\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res = mem_val_0;\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";} cp.code()+="etiss_uint64 res2 = res ^ *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOXORD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoxord"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
amominud_rd_rs1_rs2_rl_aq
static InstructionDefinition amominud_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amominud",(uint32_t) 0xc000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOMINUD\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint64 res = mem_val_0;\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(res);\n";} cp.code()+="etiss_uint64 res2 = (res > *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) ? (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) : (res);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOMINUD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amominud"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
amoswapd_rd_rs1_rs2_rl_aq
static InstructionDefinition amoswapd_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoswapd",(uint32_t) 0x800302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOSWAPD\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(((etiss_int64)(mem_val_0)));\n";} cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOSWAPD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoswapd"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
amoandd_rd_rs1_rs2_rl_aq
static InstructionDefinition amoandd_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoandd",(uint32_t) 0x6000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOANDD\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res = mem_val_0;\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";} cp.code()+="etiss_uint64 res2 = res & *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOANDD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoandd"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
amoaddd_rd_rs1_rs2_rl_aq
static InstructionDefinition amoaddd_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoaddd",(uint32_t) 0x00302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOADDD\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res = mem_val_0;\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";} cp.code()+="etiss_uint64 res2 = res + *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOADDD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoaddd"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
amoord_rd_rs1_rs2_rl_aq
static InstructionDefinition amoord_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoord",(uint32_t) 0x4000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOORD\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res = mem_val_0;\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";} cp.code()+="etiss_uint64 res2 = res | *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOORD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoord"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
amomaxud_rd_rs1_rs2_rl_aq
static InstructionDefinition amomaxud_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amomaxud",(uint32_t) 0xe000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOMAXUD\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint64 res1 = mem_val_0;\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(res1);\n";} cp.code()+="etiss_uint64 res2 = (res1 < *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) ? (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) : (res1);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOMAXUD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amomaxud"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
amomaxd_rd_rs1_rs2_rl_aq
static InstructionDefinition amomaxd_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amomaxd",(uint32_t) 0xa000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOMAXD\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res = mem_val_0;\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";} cp.code()+="etiss_uint64 res2 = (res < (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) ? (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) : (res);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOMAXD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amomaxd"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
amomind_rd_rs1_rs2_rl_aq
static InstructionDefinition amomind_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amomind",(uint32_t) 0x8000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOMIND\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res1 = mem_val_0;\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res1;\n";} cp.code()+="etiss_uint64 res2 = (res1 > (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) ? (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) : (res1);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOMIND\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amomind"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
uint32_t
static __inline__ uint32_t
Definition: arm_cde.h:25
etiss_uint8
uint8_t etiss_uint8
Definition: types.h:87
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:386
etiss::CodePart::APPENDEDRETURNINGREQUIRED
@ APPENDEDRETURNINGREQUIRED
Definition: CodePart.h:402
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition: Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition: Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
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