ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
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RV64IMACFD_RV64AInstr.cpp
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1
8#include "RV64IMACFDArch.h"
9#include "RV64IMACFDFuncs.h"
10
11using namespace etiss;
12using namespace etiss::instr;
13
14
15// AMOSWAPD --------------------------------------------------------------------
16static InstructionDefinition amoswapd_rd_rs1_rs2_rl_aq (
17 ISA32_RV64IMACFD,
18 "amoswapd",
19 (uint32_t) 0x800302f,
20 (uint32_t) 0xf800707f,
21 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22 {
23
24// -----------------------------------------------------------------------------
25
26// -----------------------------------------------------------------------------
27
28// -----------------------------------------------------------------------------
29etiss_uint8 rd = 0;
30static BitArrayRange R_rd_0(11, 7);
31rd += R_rd_0.read(ba) << 0;
32etiss_uint8 rs1 = 0;
33static BitArrayRange R_rs1_0(19, 15);
34rs1 += R_rs1_0.read(ba) << 0;
35etiss_uint8 rs2 = 0;
36static BitArrayRange R_rs2_0(24, 20);
37rs2 += R_rs2_0.read(ba) << 0;
38etiss_uint8 rl = 0;
39static BitArrayRange R_rl_0(25, 25);
40rl += R_rl_0.read(ba) << 0;
41etiss_uint8 aq = 0;
42static BitArrayRange R_aq_0(26, 26);
43aq += R_aq_0.read(ba) << 0;
44
45// -----------------------------------------------------------------------------
46
47 {
48 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
49
50 cp.code() = std::string("//AMOSWAPD\n");
51
52// -----------------------------------------------------------------------------
53cp.code() += "etiss_coverage_count(1, 226);\n";
54{ // block
55cp.code() += "etiss_coverage_count(1, 1169);\n";
56cp.code() += "{ // block\n";
57cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
58cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
59cp.code() += "} // block\n";
60} // block
61{ // block
62cp.code() += "etiss_coverage_count(1, 8465);\n";
63cp.code() += "{ // block\n";
64cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
65cp.code() += "etiss_coverage_count(4, 8432, 8431, 8430, 8428);\n";
66cp.code() += "etiss_coverage_count(1, 8433);\n";
67if ((rd % 32ULL) != 0LL) { // conditional
68cp.code() += "etiss_coverage_count(5, 8439, 8436, 8434, 8437, 8438);\n";
69cp.code() += "etiss_uint64 mem_val_0;\n";
70cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
71cp.code() += "if (cpu->exception) { // conditional\n";
72{ // procedure
73cp.code() += "{ // procedure\n";
74cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
75cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
76cp.code() += "} // procedure\n";
77} // procedure
78cp.code() += "} // conditional\n";
79cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(((etiss_int64)(mem_val_0)));\n";
80cp.code() += "etiss_coverage_count(9, 8453, 8444, 8443, 8441, 8452, 8449, 8447, 8446, 8450);\n";
81} // conditional
82cp.code() += "etiss_uint64 mem_val_1;\n";
83cp.code() += "mem_val_1 = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
84cp.code() += "etiss_coverage_count(7, 8464, 8456, 8455, 8463, 8461, 8460, 8458);\n";
85cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
86cp.code() += "if (cpu->exception) { // conditional\n";
87{ // procedure
88cp.code() += "{ // procedure\n";
89cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
90cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
91cp.code() += "} // procedure\n";
92} // procedure
93cp.code() += "} // conditional\n";
94cp.code() += "} // block\n";
95} // block
96cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
97cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
98// -----------------------------------------------------------------------------
99 cp.getAffectedRegisters().add("instructionPointer", 32);
100 }
101 {
102 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
103
104 cp.code() = std::string("//AMOSWAPD\n");
105
106// -----------------------------------------------------------------------------
107cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
108// -----------------------------------------------------------------------------
109 }
110
111 return true;
112 },
113 0,
114 [] (BitArray & ba, Instruction & instr)
115 {
116// -----------------------------------------------------------------------------
117etiss_uint8 rd = 0;
118static BitArrayRange R_rd_0(11, 7);
119rd += R_rd_0.read(ba) << 0;
120etiss_uint8 rs1 = 0;
121static BitArrayRange R_rs1_0(19, 15);
122rs1 += R_rs1_0.read(ba) << 0;
123etiss_uint8 rs2 = 0;
124static BitArrayRange R_rs2_0(24, 20);
125rs2 += R_rs2_0.read(ba) << 0;
126etiss_uint8 rl = 0;
127static BitArrayRange R_rl_0(25, 25);
128rl += R_rl_0.read(ba) << 0;
129etiss_uint8 aq = 0;
130static BitArrayRange R_aq_0(26, 26);
131aq += R_aq_0.read(ba) << 0;
132
133// -----------------------------------------------------------------------------
134
135 std::stringstream ss;
136// -----------------------------------------------------------------------------
137ss << "amoswapd" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
138// -----------------------------------------------------------------------------
139 return ss.str();
140 }
141);
142
143// AMOADDD ---------------------------------------------------------------------
144static InstructionDefinition amoaddd_rd_rs1_rs2_rl_aq (
145 ISA32_RV64IMACFD,
146 "amoaddd",
147 (uint32_t) 0x00302f,
148 (uint32_t) 0xf800707f,
149 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
150 {
151
152// -----------------------------------------------------------------------------
153
154// -----------------------------------------------------------------------------
155
156// -----------------------------------------------------------------------------
157etiss_uint8 rd = 0;
158static BitArrayRange R_rd_0(11, 7);
159rd += R_rd_0.read(ba) << 0;
160etiss_uint8 rs1 = 0;
161static BitArrayRange R_rs1_0(19, 15);
162rs1 += R_rs1_0.read(ba) << 0;
163etiss_uint8 rs2 = 0;
164static BitArrayRange R_rs2_0(24, 20);
165rs2 += R_rs2_0.read(ba) << 0;
166etiss_uint8 rl = 0;
167static BitArrayRange R_rl_0(25, 25);
168rl += R_rl_0.read(ba) << 0;
169etiss_uint8 aq = 0;
170static BitArrayRange R_aq_0(26, 26);
171aq += R_aq_0.read(ba) << 0;
172
173// -----------------------------------------------------------------------------
174
175 {
176 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
177
178 cp.code() = std::string("//AMOADDD\n");
179
180// -----------------------------------------------------------------------------
181cp.code() += "etiss_coverage_count(1, 227);\n";
182{ // block
183cp.code() += "etiss_coverage_count(1, 1169);\n";
184cp.code() += "{ // block\n";
185cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
186cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
187cp.code() += "} // block\n";
188} // block
189{ // block
190cp.code() += "etiss_coverage_count(1, 8506);\n";
191cp.code() += "{ // block\n";
192cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
193cp.code() += "etiss_coverage_count(4, 8472, 8471, 8470, 8468);\n";
194cp.code() += "etiss_uint64 mem_val_0;\n";
195cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
196cp.code() += "if (cpu->exception) { // conditional\n";
197{ // procedure
198cp.code() += "{ // procedure\n";
199cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
200cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
201cp.code() += "} // procedure\n";
202} // procedure
203cp.code() += "} // conditional\n";
204cp.code() += "etiss_int64 res = mem_val_0;\n";
205cp.code() += "etiss_coverage_count(3, 8477, 8476, 8475);\n";
206cp.code() += "etiss_coverage_count(1, 8478);\n";
207if ((rd % 32ULL) != 0LL) { // conditional
208cp.code() += "etiss_coverage_count(5, 8484, 8481, 8479, 8482, 8483);\n";
209cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
210cp.code() += "etiss_coverage_count(5, 8491, 8489, 8488, 8486, 8490);\n";
211} // conditional
212cp.code() += "etiss_uint64 res2 = res + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
213cp.code() += "etiss_coverage_count(6, 8500, 8499, 8493, 8498, 8497, 8495);\n";
214cp.code() += "etiss_uint64 mem_val_1;\n";
215cp.code() += "mem_val_1 = res2;\n";
216cp.code() += "etiss_coverage_count(4, 8505, 8503, 8502, 8504);\n";
217cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
218cp.code() += "if (cpu->exception) { // conditional\n";
219{ // procedure
220cp.code() += "{ // procedure\n";
221cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
222cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
223cp.code() += "} // procedure\n";
224} // procedure
225cp.code() += "} // conditional\n";
226cp.code() += "} // block\n";
227} // block
228cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
229cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
230// -----------------------------------------------------------------------------
231 cp.getAffectedRegisters().add("instructionPointer", 32);
232 }
233 {
234 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
235
236 cp.code() = std::string("//AMOADDD\n");
237
238// -----------------------------------------------------------------------------
239cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
240// -----------------------------------------------------------------------------
241 }
242
243 return true;
244 },
245 0,
246 [] (BitArray & ba, Instruction & instr)
247 {
248// -----------------------------------------------------------------------------
249etiss_uint8 rd = 0;
250static BitArrayRange R_rd_0(11, 7);
251rd += R_rd_0.read(ba) << 0;
252etiss_uint8 rs1 = 0;
253static BitArrayRange R_rs1_0(19, 15);
254rs1 += R_rs1_0.read(ba) << 0;
255etiss_uint8 rs2 = 0;
256static BitArrayRange R_rs2_0(24, 20);
257rs2 += R_rs2_0.read(ba) << 0;
258etiss_uint8 rl = 0;
259static BitArrayRange R_rl_0(25, 25);
260rl += R_rl_0.read(ba) << 0;
261etiss_uint8 aq = 0;
262static BitArrayRange R_aq_0(26, 26);
263aq += R_aq_0.read(ba) << 0;
264
265// -----------------------------------------------------------------------------
266
267 std::stringstream ss;
268// -----------------------------------------------------------------------------
269ss << "amoaddd" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
270// -----------------------------------------------------------------------------
271 return ss.str();
272 }
273);
274
275// AMOXORD ---------------------------------------------------------------------
276static InstructionDefinition amoxord_rd_rs1_rs2_rl_aq (
277 ISA32_RV64IMACFD,
278 "amoxord",
279 (uint32_t) 0x2000302f,
280 (uint32_t) 0xf800707f,
281 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
282 {
283
284// -----------------------------------------------------------------------------
285
286// -----------------------------------------------------------------------------
287
288// -----------------------------------------------------------------------------
289etiss_uint8 rd = 0;
290static BitArrayRange R_rd_0(11, 7);
291rd += R_rd_0.read(ba) << 0;
292etiss_uint8 rs1 = 0;
293static BitArrayRange R_rs1_0(19, 15);
294rs1 += R_rs1_0.read(ba) << 0;
295etiss_uint8 rs2 = 0;
296static BitArrayRange R_rs2_0(24, 20);
297rs2 += R_rs2_0.read(ba) << 0;
298etiss_uint8 rl = 0;
299static BitArrayRange R_rl_0(25, 25);
300rl += R_rl_0.read(ba) << 0;
301etiss_uint8 aq = 0;
302static BitArrayRange R_aq_0(26, 26);
303aq += R_aq_0.read(ba) << 0;
304
305// -----------------------------------------------------------------------------
306
307 {
308 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
309
310 cp.code() = std::string("//AMOXORD\n");
311
312// -----------------------------------------------------------------------------
313cp.code() += "etiss_coverage_count(1, 228);\n";
314{ // block
315cp.code() += "etiss_coverage_count(1, 1169);\n";
316cp.code() += "{ // block\n";
317cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
318cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
319cp.code() += "} // block\n";
320} // block
321{ // block
322cp.code() += "etiss_coverage_count(1, 8547);\n";
323cp.code() += "{ // block\n";
324cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
325cp.code() += "etiss_coverage_count(4, 8513, 8512, 8511, 8509);\n";
326cp.code() += "etiss_uint64 mem_val_0;\n";
327cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
328cp.code() += "if (cpu->exception) { // conditional\n";
329{ // procedure
330cp.code() += "{ // procedure\n";
331cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
332cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
333cp.code() += "} // procedure\n";
334} // procedure
335cp.code() += "} // conditional\n";
336cp.code() += "etiss_int64 res = mem_val_0;\n";
337cp.code() += "etiss_coverage_count(3, 8518, 8517, 8516);\n";
338cp.code() += "etiss_coverage_count(1, 8519);\n";
339if ((rd % 32ULL) != 0LL) { // conditional
340cp.code() += "etiss_coverage_count(5, 8525, 8522, 8520, 8523, 8524);\n";
341cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
342cp.code() += "etiss_coverage_count(5, 8532, 8530, 8529, 8527, 8531);\n";
343} // conditional
344cp.code() += "etiss_uint64 res2 = res ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
345cp.code() += "etiss_coverage_count(6, 8541, 8540, 8534, 8539, 8538, 8536);\n";
346cp.code() += "etiss_uint64 mem_val_1;\n";
347cp.code() += "mem_val_1 = res2;\n";
348cp.code() += "etiss_coverage_count(4, 8546, 8544, 8543, 8545);\n";
349cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
350cp.code() += "if (cpu->exception) { // conditional\n";
351{ // procedure
352cp.code() += "{ // procedure\n";
353cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
354cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
355cp.code() += "} // procedure\n";
356} // procedure
357cp.code() += "} // conditional\n";
358cp.code() += "} // block\n";
359} // block
360cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
361cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
362// -----------------------------------------------------------------------------
363 cp.getAffectedRegisters().add("instructionPointer", 32);
364 }
365 {
366 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
367
368 cp.code() = std::string("//AMOXORD\n");
369
370// -----------------------------------------------------------------------------
371cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
372// -----------------------------------------------------------------------------
373 }
374
375 return true;
376 },
377 0,
378 [] (BitArray & ba, Instruction & instr)
379 {
380// -----------------------------------------------------------------------------
381etiss_uint8 rd = 0;
382static BitArrayRange R_rd_0(11, 7);
383rd += R_rd_0.read(ba) << 0;
384etiss_uint8 rs1 = 0;
385static BitArrayRange R_rs1_0(19, 15);
386rs1 += R_rs1_0.read(ba) << 0;
387etiss_uint8 rs2 = 0;
388static BitArrayRange R_rs2_0(24, 20);
389rs2 += R_rs2_0.read(ba) << 0;
390etiss_uint8 rl = 0;
391static BitArrayRange R_rl_0(25, 25);
392rl += R_rl_0.read(ba) << 0;
393etiss_uint8 aq = 0;
394static BitArrayRange R_aq_0(26, 26);
395aq += R_aq_0.read(ba) << 0;
396
397// -----------------------------------------------------------------------------
398
399 std::stringstream ss;
400// -----------------------------------------------------------------------------
401ss << "amoxord" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
402// -----------------------------------------------------------------------------
403 return ss.str();
404 }
405);
406
407// AMOANDD ---------------------------------------------------------------------
408static InstructionDefinition amoandd_rd_rs1_rs2_rl_aq (
409 ISA32_RV64IMACFD,
410 "amoandd",
411 (uint32_t) 0x6000302f,
412 (uint32_t) 0xf800707f,
413 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
414 {
415
416// -----------------------------------------------------------------------------
417
418// -----------------------------------------------------------------------------
419
420// -----------------------------------------------------------------------------
421etiss_uint8 rd = 0;
422static BitArrayRange R_rd_0(11, 7);
423rd += R_rd_0.read(ba) << 0;
424etiss_uint8 rs1 = 0;
425static BitArrayRange R_rs1_0(19, 15);
426rs1 += R_rs1_0.read(ba) << 0;
427etiss_uint8 rs2 = 0;
428static BitArrayRange R_rs2_0(24, 20);
429rs2 += R_rs2_0.read(ba) << 0;
430etiss_uint8 rl = 0;
431static BitArrayRange R_rl_0(25, 25);
432rl += R_rl_0.read(ba) << 0;
433etiss_uint8 aq = 0;
434static BitArrayRange R_aq_0(26, 26);
435aq += R_aq_0.read(ba) << 0;
436
437// -----------------------------------------------------------------------------
438
439 {
440 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
441
442 cp.code() = std::string("//AMOANDD\n");
443
444// -----------------------------------------------------------------------------
445cp.code() += "etiss_coverage_count(1, 229);\n";
446{ // block
447cp.code() += "etiss_coverage_count(1, 1169);\n";
448cp.code() += "{ // block\n";
449cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
450cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
451cp.code() += "} // block\n";
452} // block
453{ // block
454cp.code() += "etiss_coverage_count(1, 8588);\n";
455cp.code() += "{ // block\n";
456cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
457cp.code() += "etiss_coverage_count(4, 8554, 8553, 8552, 8550);\n";
458cp.code() += "etiss_uint64 mem_val_0;\n";
459cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
460cp.code() += "if (cpu->exception) { // conditional\n";
461{ // procedure
462cp.code() += "{ // procedure\n";
463cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
464cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
465cp.code() += "} // procedure\n";
466} // procedure
467cp.code() += "} // conditional\n";
468cp.code() += "etiss_int64 res = mem_val_0;\n";
469cp.code() += "etiss_coverage_count(3, 8559, 8558, 8557);\n";
470cp.code() += "etiss_coverage_count(1, 8560);\n";
471if ((rd % 32ULL) != 0LL) { // conditional
472cp.code() += "etiss_coverage_count(5, 8566, 8563, 8561, 8564, 8565);\n";
473cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
474cp.code() += "etiss_coverage_count(5, 8573, 8571, 8570, 8568, 8572);\n";
475} // conditional
476cp.code() += "etiss_uint64 res2 = res & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
477cp.code() += "etiss_coverage_count(6, 8582, 8581, 8575, 8580, 8579, 8577);\n";
478cp.code() += "etiss_uint64 mem_val_1;\n";
479cp.code() += "mem_val_1 = res2;\n";
480cp.code() += "etiss_coverage_count(4, 8587, 8585, 8584, 8586);\n";
481cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
482cp.code() += "if (cpu->exception) { // conditional\n";
483{ // procedure
484cp.code() += "{ // procedure\n";
485cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
486cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
487cp.code() += "} // procedure\n";
488} // procedure
489cp.code() += "} // conditional\n";
490cp.code() += "} // block\n";
491} // block
492cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
493cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
494// -----------------------------------------------------------------------------
495 cp.getAffectedRegisters().add("instructionPointer", 32);
496 }
497 {
498 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
499
500 cp.code() = std::string("//AMOANDD\n");
501
502// -----------------------------------------------------------------------------
503cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
504// -----------------------------------------------------------------------------
505 }
506
507 return true;
508 },
509 0,
510 [] (BitArray & ba, Instruction & instr)
511 {
512// -----------------------------------------------------------------------------
513etiss_uint8 rd = 0;
514static BitArrayRange R_rd_0(11, 7);
515rd += R_rd_0.read(ba) << 0;
516etiss_uint8 rs1 = 0;
517static BitArrayRange R_rs1_0(19, 15);
518rs1 += R_rs1_0.read(ba) << 0;
519etiss_uint8 rs2 = 0;
520static BitArrayRange R_rs2_0(24, 20);
521rs2 += R_rs2_0.read(ba) << 0;
522etiss_uint8 rl = 0;
523static BitArrayRange R_rl_0(25, 25);
524rl += R_rl_0.read(ba) << 0;
525etiss_uint8 aq = 0;
526static BitArrayRange R_aq_0(26, 26);
527aq += R_aq_0.read(ba) << 0;
528
529// -----------------------------------------------------------------------------
530
531 std::stringstream ss;
532// -----------------------------------------------------------------------------
533ss << "amoandd" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
534// -----------------------------------------------------------------------------
535 return ss.str();
536 }
537);
538
539// AMOORD ----------------------------------------------------------------------
540static InstructionDefinition amoord_rd_rs1_rs2_rl_aq (
541 ISA32_RV64IMACFD,
542 "amoord",
543 (uint32_t) 0x4000302f,
544 (uint32_t) 0xf800707f,
545 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
546 {
547
548// -----------------------------------------------------------------------------
549
550// -----------------------------------------------------------------------------
551
552// -----------------------------------------------------------------------------
553etiss_uint8 rd = 0;
554static BitArrayRange R_rd_0(11, 7);
555rd += R_rd_0.read(ba) << 0;
556etiss_uint8 rs1 = 0;
557static BitArrayRange R_rs1_0(19, 15);
558rs1 += R_rs1_0.read(ba) << 0;
559etiss_uint8 rs2 = 0;
560static BitArrayRange R_rs2_0(24, 20);
561rs2 += R_rs2_0.read(ba) << 0;
562etiss_uint8 rl = 0;
563static BitArrayRange R_rl_0(25, 25);
564rl += R_rl_0.read(ba) << 0;
565etiss_uint8 aq = 0;
566static BitArrayRange R_aq_0(26, 26);
567aq += R_aq_0.read(ba) << 0;
568
569// -----------------------------------------------------------------------------
570
571 {
572 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
573
574 cp.code() = std::string("//AMOORD\n");
575
576// -----------------------------------------------------------------------------
577cp.code() += "etiss_coverage_count(1, 230);\n";
578{ // block
579cp.code() += "etiss_coverage_count(1, 1169);\n";
580cp.code() += "{ // block\n";
581cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
582cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
583cp.code() += "} // block\n";
584} // block
585{ // block
586cp.code() += "etiss_coverage_count(1, 8629);\n";
587cp.code() += "{ // block\n";
588cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
589cp.code() += "etiss_coverage_count(4, 8595, 8594, 8593, 8591);\n";
590cp.code() += "etiss_uint64 mem_val_0;\n";
591cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
592cp.code() += "if (cpu->exception) { // conditional\n";
593{ // procedure
594cp.code() += "{ // procedure\n";
595cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
596cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
597cp.code() += "} // procedure\n";
598} // procedure
599cp.code() += "} // conditional\n";
600cp.code() += "etiss_int64 res = mem_val_0;\n";
601cp.code() += "etiss_coverage_count(3, 8600, 8599, 8598);\n";
602cp.code() += "etiss_coverage_count(1, 8601);\n";
603if ((rd % 32ULL) != 0LL) { // conditional
604cp.code() += "etiss_coverage_count(5, 8607, 8604, 8602, 8605, 8606);\n";
605cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
606cp.code() += "etiss_coverage_count(5, 8614, 8612, 8611, 8609, 8613);\n";
607} // conditional
608cp.code() += "etiss_uint64 res2 = res | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
609cp.code() += "etiss_coverage_count(6, 8623, 8622, 8616, 8621, 8620, 8618);\n";
610cp.code() += "etiss_uint64 mem_val_1;\n";
611cp.code() += "mem_val_1 = res2;\n";
612cp.code() += "etiss_coverage_count(4, 8628, 8626, 8625, 8627);\n";
613cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
614cp.code() += "if (cpu->exception) { // conditional\n";
615{ // procedure
616cp.code() += "{ // procedure\n";
617cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
618cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
619cp.code() += "} // procedure\n";
620} // procedure
621cp.code() += "} // conditional\n";
622cp.code() += "} // block\n";
623} // block
624cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
625cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
626// -----------------------------------------------------------------------------
627 cp.getAffectedRegisters().add("instructionPointer", 32);
628 }
629 {
630 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
631
632 cp.code() = std::string("//AMOORD\n");
633
634// -----------------------------------------------------------------------------
635cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
636// -----------------------------------------------------------------------------
637 }
638
639 return true;
640 },
641 0,
642 [] (BitArray & ba, Instruction & instr)
643 {
644// -----------------------------------------------------------------------------
645etiss_uint8 rd = 0;
646static BitArrayRange R_rd_0(11, 7);
647rd += R_rd_0.read(ba) << 0;
648etiss_uint8 rs1 = 0;
649static BitArrayRange R_rs1_0(19, 15);
650rs1 += R_rs1_0.read(ba) << 0;
651etiss_uint8 rs2 = 0;
652static BitArrayRange R_rs2_0(24, 20);
653rs2 += R_rs2_0.read(ba) << 0;
654etiss_uint8 rl = 0;
655static BitArrayRange R_rl_0(25, 25);
656rl += R_rl_0.read(ba) << 0;
657etiss_uint8 aq = 0;
658static BitArrayRange R_aq_0(26, 26);
659aq += R_aq_0.read(ba) << 0;
660
661// -----------------------------------------------------------------------------
662
663 std::stringstream ss;
664// -----------------------------------------------------------------------------
665ss << "amoord" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
666// -----------------------------------------------------------------------------
667 return ss.str();
668 }
669);
670
671// AMOMIND ---------------------------------------------------------------------
672static InstructionDefinition amomind_rd_rs1_rs2_rl_aq (
673 ISA32_RV64IMACFD,
674 "amomind",
675 (uint32_t) 0x8000302f,
676 (uint32_t) 0xf800707f,
677 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
678 {
679
680// -----------------------------------------------------------------------------
681
682// -----------------------------------------------------------------------------
683
684// -----------------------------------------------------------------------------
685etiss_uint8 rd = 0;
686static BitArrayRange R_rd_0(11, 7);
687rd += R_rd_0.read(ba) << 0;
688etiss_uint8 rs1 = 0;
689static BitArrayRange R_rs1_0(19, 15);
690rs1 += R_rs1_0.read(ba) << 0;
691etiss_uint8 rs2 = 0;
692static BitArrayRange R_rs2_0(24, 20);
693rs2 += R_rs2_0.read(ba) << 0;
694etiss_uint8 rl = 0;
695static BitArrayRange R_rl_0(25, 25);
696rl += R_rl_0.read(ba) << 0;
697etiss_uint8 aq = 0;
698static BitArrayRange R_aq_0(26, 26);
699aq += R_aq_0.read(ba) << 0;
700
701// -----------------------------------------------------------------------------
702
703 {
704 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
705
706 cp.code() = std::string("//AMOMIND\n");
707
708// -----------------------------------------------------------------------------
709cp.code() += "etiss_coverage_count(1, 231);\n";
710{ // block
711cp.code() += "etiss_coverage_count(1, 1169);\n";
712cp.code() += "{ // block\n";
713cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
714cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
715cp.code() += "} // block\n";
716} // block
717{ // block
718cp.code() += "etiss_coverage_count(1, 8679);\n";
719cp.code() += "{ // block\n";
720cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
721cp.code() += "etiss_coverage_count(4, 8636, 8635, 8634, 8632);\n";
722cp.code() += "etiss_uint64 mem_val_0;\n";
723cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
724cp.code() += "if (cpu->exception) { // conditional\n";
725{ // procedure
726cp.code() += "{ // procedure\n";
727cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
728cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
729cp.code() += "} // procedure\n";
730} // procedure
731cp.code() += "} // conditional\n";
732cp.code() += "etiss_int64 res1 = mem_val_0;\n";
733cp.code() += "etiss_coverage_count(3, 8641, 8640, 8639);\n";
734cp.code() += "etiss_coverage_count(1, 8642);\n";
735if ((rd % 32ULL) != 0LL) { // conditional
736cp.code() += "etiss_coverage_count(5, 8648, 8645, 8643, 8646, 8647);\n";
737cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res1;\n";
738cp.code() += "etiss_coverage_count(5, 8655, 8653, 8652, 8650, 8654);\n";
739} // conditional
740cp.code() += "etiss_uint64 res2 = (res1 > (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res1);\n";
741cp.code() += "etiss_coverage_count(12, 8673, 8672, 8665, 8657, 8664, 8662, 8661, 8659, 8670, 8669, 8667, 8671);\n";
742cp.code() += "etiss_uint64 mem_val_1;\n";
743cp.code() += "mem_val_1 = res2;\n";
744cp.code() += "etiss_coverage_count(4, 8678, 8676, 8675, 8677);\n";
745cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
746cp.code() += "if (cpu->exception) { // conditional\n";
747{ // procedure
748cp.code() += "{ // procedure\n";
749cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
750cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
751cp.code() += "} // procedure\n";
752} // procedure
753cp.code() += "} // conditional\n";
754cp.code() += "} // block\n";
755} // block
756cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
757cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
758// -----------------------------------------------------------------------------
759 cp.getAffectedRegisters().add("instructionPointer", 32);
760 }
761 {
762 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
763
764 cp.code() = std::string("//AMOMIND\n");
765
766// -----------------------------------------------------------------------------
767cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
768// -----------------------------------------------------------------------------
769 }
770
771 return true;
772 },
773 0,
774 [] (BitArray & ba, Instruction & instr)
775 {
776// -----------------------------------------------------------------------------
777etiss_uint8 rd = 0;
778static BitArrayRange R_rd_0(11, 7);
779rd += R_rd_0.read(ba) << 0;
780etiss_uint8 rs1 = 0;
781static BitArrayRange R_rs1_0(19, 15);
782rs1 += R_rs1_0.read(ba) << 0;
783etiss_uint8 rs2 = 0;
784static BitArrayRange R_rs2_0(24, 20);
785rs2 += R_rs2_0.read(ba) << 0;
786etiss_uint8 rl = 0;
787static BitArrayRange R_rl_0(25, 25);
788rl += R_rl_0.read(ba) << 0;
789etiss_uint8 aq = 0;
790static BitArrayRange R_aq_0(26, 26);
791aq += R_aq_0.read(ba) << 0;
792
793// -----------------------------------------------------------------------------
794
795 std::stringstream ss;
796// -----------------------------------------------------------------------------
797ss << "amomind" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
798// -----------------------------------------------------------------------------
799 return ss.str();
800 }
801);
802
803// AMOMAXD ---------------------------------------------------------------------
804static InstructionDefinition amomaxd_rd_rs1_rs2_rl_aq (
805 ISA32_RV64IMACFD,
806 "amomaxd",
807 (uint32_t) 0xa000302f,
808 (uint32_t) 0xf800707f,
809 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
810 {
811
812// -----------------------------------------------------------------------------
813
814// -----------------------------------------------------------------------------
815
816// -----------------------------------------------------------------------------
817etiss_uint8 rd = 0;
818static BitArrayRange R_rd_0(11, 7);
819rd += R_rd_0.read(ba) << 0;
820etiss_uint8 rs1 = 0;
821static BitArrayRange R_rs1_0(19, 15);
822rs1 += R_rs1_0.read(ba) << 0;
823etiss_uint8 rs2 = 0;
824static BitArrayRange R_rs2_0(24, 20);
825rs2 += R_rs2_0.read(ba) << 0;
826etiss_uint8 rl = 0;
827static BitArrayRange R_rl_0(25, 25);
828rl += R_rl_0.read(ba) << 0;
829etiss_uint8 aq = 0;
830static BitArrayRange R_aq_0(26, 26);
831aq += R_aq_0.read(ba) << 0;
832
833// -----------------------------------------------------------------------------
834
835 {
836 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
837
838 cp.code() = std::string("//AMOMAXD\n");
839
840// -----------------------------------------------------------------------------
841cp.code() += "etiss_coverage_count(1, 232);\n";
842{ // block
843cp.code() += "etiss_coverage_count(1, 1169);\n";
844cp.code() += "{ // block\n";
845cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
846cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
847cp.code() += "} // block\n";
848} // block
849{ // block
850cp.code() += "etiss_coverage_count(1, 8729);\n";
851cp.code() += "{ // block\n";
852cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
853cp.code() += "etiss_coverage_count(4, 8686, 8685, 8684, 8682);\n";
854cp.code() += "etiss_uint64 mem_val_0;\n";
855cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
856cp.code() += "if (cpu->exception) { // conditional\n";
857{ // procedure
858cp.code() += "{ // procedure\n";
859cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
860cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
861cp.code() += "} // procedure\n";
862} // procedure
863cp.code() += "} // conditional\n";
864cp.code() += "etiss_int64 res = mem_val_0;\n";
865cp.code() += "etiss_coverage_count(3, 8691, 8690, 8689);\n";
866cp.code() += "etiss_coverage_count(1, 8692);\n";
867if ((rd % 32ULL) != 0LL) { // conditional
868cp.code() += "etiss_coverage_count(5, 8698, 8695, 8693, 8696, 8697);\n";
869cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
870cp.code() += "etiss_coverage_count(5, 8705, 8703, 8702, 8700, 8704);\n";
871} // conditional
872cp.code() += "etiss_uint64 res2 = (res < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res);\n";
873cp.code() += "etiss_coverage_count(12, 8723, 8722, 8715, 8707, 8714, 8712, 8711, 8709, 8720, 8719, 8717, 8721);\n";
874cp.code() += "etiss_uint64 mem_val_1;\n";
875cp.code() += "mem_val_1 = res2;\n";
876cp.code() += "etiss_coverage_count(4, 8728, 8726, 8725, 8727);\n";
877cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
878cp.code() += "if (cpu->exception) { // conditional\n";
879{ // procedure
880cp.code() += "{ // procedure\n";
881cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
882cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
883cp.code() += "} // procedure\n";
884} // procedure
885cp.code() += "} // conditional\n";
886cp.code() += "} // block\n";
887} // block
888cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
889cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
890// -----------------------------------------------------------------------------
891 cp.getAffectedRegisters().add("instructionPointer", 32);
892 }
893 {
894 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
895
896 cp.code() = std::string("//AMOMAXD\n");
897
898// -----------------------------------------------------------------------------
899cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
900// -----------------------------------------------------------------------------
901 }
902
903 return true;
904 },
905 0,
906 [] (BitArray & ba, Instruction & instr)
907 {
908// -----------------------------------------------------------------------------
909etiss_uint8 rd = 0;
910static BitArrayRange R_rd_0(11, 7);
911rd += R_rd_0.read(ba) << 0;
912etiss_uint8 rs1 = 0;
913static BitArrayRange R_rs1_0(19, 15);
914rs1 += R_rs1_0.read(ba) << 0;
915etiss_uint8 rs2 = 0;
916static BitArrayRange R_rs2_0(24, 20);
917rs2 += R_rs2_0.read(ba) << 0;
918etiss_uint8 rl = 0;
919static BitArrayRange R_rl_0(25, 25);
920rl += R_rl_0.read(ba) << 0;
921etiss_uint8 aq = 0;
922static BitArrayRange R_aq_0(26, 26);
923aq += R_aq_0.read(ba) << 0;
924
925// -----------------------------------------------------------------------------
926
927 std::stringstream ss;
928// -----------------------------------------------------------------------------
929ss << "amomaxd" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
930// -----------------------------------------------------------------------------
931 return ss.str();
932 }
933);
934
935// AMOMINUD --------------------------------------------------------------------
936static InstructionDefinition amominud_rd_rs1_rs2_rl_aq (
937 ISA32_RV64IMACFD,
938 "amominud",
939 (uint32_t) 0xc000302f,
940 (uint32_t) 0xf800707f,
941 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
942 {
943
944// -----------------------------------------------------------------------------
945
946// -----------------------------------------------------------------------------
947
948// -----------------------------------------------------------------------------
949etiss_uint8 rd = 0;
950static BitArrayRange R_rd_0(11, 7);
951rd += R_rd_0.read(ba) << 0;
952etiss_uint8 rs1 = 0;
953static BitArrayRange R_rs1_0(19, 15);
954rs1 += R_rs1_0.read(ba) << 0;
955etiss_uint8 rs2 = 0;
956static BitArrayRange R_rs2_0(24, 20);
957rs2 += R_rs2_0.read(ba) << 0;
958etiss_uint8 rl = 0;
959static BitArrayRange R_rl_0(25, 25);
960rl += R_rl_0.read(ba) << 0;
961etiss_uint8 aq = 0;
962static BitArrayRange R_aq_0(26, 26);
963aq += R_aq_0.read(ba) << 0;
964
965// -----------------------------------------------------------------------------
966
967 {
968 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
969
970 cp.code() = std::string("//AMOMINUD\n");
971
972// -----------------------------------------------------------------------------
973cp.code() += "etiss_coverage_count(1, 233);\n";
974{ // block
975cp.code() += "etiss_coverage_count(1, 1169);\n";
976cp.code() += "{ // block\n";
977cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
978cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
979cp.code() += "} // block\n";
980} // block
981{ // block
982cp.code() += "etiss_coverage_count(1, 8779);\n";
983cp.code() += "{ // block\n";
984cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
985cp.code() += "etiss_coverage_count(4, 8736, 8735, 8734, 8732);\n";
986cp.code() += "etiss_uint64 mem_val_0;\n";
987cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
988cp.code() += "if (cpu->exception) { // conditional\n";
989{ // procedure
990cp.code() += "{ // procedure\n";
991cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
992cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
993cp.code() += "} // procedure\n";
994} // procedure
995cp.code() += "} // conditional\n";
996cp.code() += "etiss_uint64 res = mem_val_0;\n";
997cp.code() += "etiss_coverage_count(3, 8741, 8740, 8739);\n";
998cp.code() += "etiss_coverage_count(1, 8742);\n";
999if ((rd % 32ULL) != 0LL) { // conditional
1000cp.code() += "etiss_coverage_count(5, 8748, 8745, 8743, 8746, 8747);\n";
1001cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res);\n";
1002cp.code() += "etiss_coverage_count(6, 8757, 8753, 8752, 8750, 8756, 8754);\n";
1003} // conditional
1004cp.code() += "etiss_uint64 res2 = (res > *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res);\n";
1005cp.code() += "etiss_coverage_count(11, 8773, 8772, 8765, 8759, 8764, 8763, 8761, 8770, 8769, 8767, 8771);\n";
1006cp.code() += "etiss_uint64 mem_val_1;\n";
1007cp.code() += "mem_val_1 = res2;\n";
1008cp.code() += "etiss_coverage_count(4, 8778, 8776, 8775, 8777);\n";
1009cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
1010cp.code() += "if (cpu->exception) { // conditional\n";
1011{ // procedure
1012cp.code() += "{ // procedure\n";
1013cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1014cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1015cp.code() += "} // procedure\n";
1016} // procedure
1017cp.code() += "} // conditional\n";
1018cp.code() += "} // block\n";
1019} // block
1020cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1021cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1022// -----------------------------------------------------------------------------
1023 cp.getAffectedRegisters().add("instructionPointer", 32);
1024 }
1025 {
1026 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1027
1028 cp.code() = std::string("//AMOMINUD\n");
1029
1030// -----------------------------------------------------------------------------
1031cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1032// -----------------------------------------------------------------------------
1033 }
1034
1035 return true;
1036 },
1037 0,
1038 [] (BitArray & ba, Instruction & instr)
1039 {
1040// -----------------------------------------------------------------------------
1041etiss_uint8 rd = 0;
1042static BitArrayRange R_rd_0(11, 7);
1043rd += R_rd_0.read(ba) << 0;
1044etiss_uint8 rs1 = 0;
1045static BitArrayRange R_rs1_0(19, 15);
1046rs1 += R_rs1_0.read(ba) << 0;
1047etiss_uint8 rs2 = 0;
1048static BitArrayRange R_rs2_0(24, 20);
1049rs2 += R_rs2_0.read(ba) << 0;
1050etiss_uint8 rl = 0;
1051static BitArrayRange R_rl_0(25, 25);
1052rl += R_rl_0.read(ba) << 0;
1053etiss_uint8 aq = 0;
1054static BitArrayRange R_aq_0(26, 26);
1055aq += R_aq_0.read(ba) << 0;
1056
1057// -----------------------------------------------------------------------------
1058
1059 std::stringstream ss;
1060// -----------------------------------------------------------------------------
1061ss << "amominud" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
1062// -----------------------------------------------------------------------------
1063 return ss.str();
1064 }
1065);
1066
1067// AMOMAXUD --------------------------------------------------------------------
1068static InstructionDefinition amomaxud_rd_rs1_rs2_rl_aq (
1069 ISA32_RV64IMACFD,
1070 "amomaxud",
1071 (uint32_t) 0xe000302f,
1072 (uint32_t) 0xf800707f,
1073 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1074 {
1075
1076// -----------------------------------------------------------------------------
1077
1078// -----------------------------------------------------------------------------
1079
1080// -----------------------------------------------------------------------------
1081etiss_uint8 rd = 0;
1082static BitArrayRange R_rd_0(11, 7);
1083rd += R_rd_0.read(ba) << 0;
1084etiss_uint8 rs1 = 0;
1085static BitArrayRange R_rs1_0(19, 15);
1086rs1 += R_rs1_0.read(ba) << 0;
1087etiss_uint8 rs2 = 0;
1088static BitArrayRange R_rs2_0(24, 20);
1089rs2 += R_rs2_0.read(ba) << 0;
1090etiss_uint8 rl = 0;
1091static BitArrayRange R_rl_0(25, 25);
1092rl += R_rl_0.read(ba) << 0;
1093etiss_uint8 aq = 0;
1094static BitArrayRange R_aq_0(26, 26);
1095aq += R_aq_0.read(ba) << 0;
1096
1097// -----------------------------------------------------------------------------
1098
1099 {
1100 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1101
1102 cp.code() = std::string("//AMOMAXUD\n");
1103
1104// -----------------------------------------------------------------------------
1105cp.code() += "etiss_coverage_count(1, 234);\n";
1106{ // block
1107cp.code() += "etiss_coverage_count(1, 1169);\n";
1108cp.code() += "{ // block\n";
1109cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1110cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1111cp.code() += "} // block\n";
1112} // block
1113{ // block
1114cp.code() += "etiss_coverage_count(1, 8829);\n";
1115cp.code() += "{ // block\n";
1116cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
1117cp.code() += "etiss_coverage_count(4, 8786, 8785, 8784, 8782);\n";
1118cp.code() += "etiss_uint64 mem_val_0;\n";
1119cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
1120cp.code() += "if (cpu->exception) { // conditional\n";
1121{ // procedure
1122cp.code() += "{ // procedure\n";
1123cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1124cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1125cp.code() += "} // procedure\n";
1126} // procedure
1127cp.code() += "} // conditional\n";
1128cp.code() += "etiss_uint64 res1 = mem_val_0;\n";
1129cp.code() += "etiss_coverage_count(3, 8791, 8790, 8789);\n";
1130cp.code() += "etiss_coverage_count(1, 8792);\n";
1131if ((rd % 32ULL) != 0LL) { // conditional
1132cp.code() += "etiss_coverage_count(5, 8798, 8795, 8793, 8796, 8797);\n";
1133cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res1);\n";
1134cp.code() += "etiss_coverage_count(6, 8807, 8803, 8802, 8800, 8806, 8804);\n";
1135} // conditional
1136cp.code() += "etiss_uint64 res2 = (res1 < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res1);\n";
1137cp.code() += "etiss_coverage_count(11, 8823, 8822, 8815, 8809, 8814, 8813, 8811, 8820, 8819, 8817, 8821);\n";
1138cp.code() += "etiss_uint64 mem_val_1;\n";
1139cp.code() += "mem_val_1 = res2;\n";
1140cp.code() += "etiss_coverage_count(4, 8828, 8826, 8825, 8827);\n";
1141cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
1142cp.code() += "if (cpu->exception) { // conditional\n";
1143{ // procedure
1144cp.code() += "{ // procedure\n";
1145cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1146cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1147cp.code() += "} // procedure\n";
1148} // procedure
1149cp.code() += "} // conditional\n";
1150cp.code() += "} // block\n";
1151} // block
1152cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1153cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1154// -----------------------------------------------------------------------------
1155 cp.getAffectedRegisters().add("instructionPointer", 32);
1156 }
1157 {
1158 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1159
1160 cp.code() = std::string("//AMOMAXUD\n");
1161
1162// -----------------------------------------------------------------------------
1163cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1164// -----------------------------------------------------------------------------
1165 }
1166
1167 return true;
1168 },
1169 0,
1170 [] (BitArray & ba, Instruction & instr)
1171 {
1172// -----------------------------------------------------------------------------
1173etiss_uint8 rd = 0;
1174static BitArrayRange R_rd_0(11, 7);
1175rd += R_rd_0.read(ba) << 0;
1176etiss_uint8 rs1 = 0;
1177static BitArrayRange R_rs1_0(19, 15);
1178rs1 += R_rs1_0.read(ba) << 0;
1179etiss_uint8 rs2 = 0;
1180static BitArrayRange R_rs2_0(24, 20);
1181rs2 += R_rs2_0.read(ba) << 0;
1182etiss_uint8 rl = 0;
1183static BitArrayRange R_rl_0(25, 25);
1184rl += R_rl_0.read(ba) << 0;
1185etiss_uint8 aq = 0;
1186static BitArrayRange R_aq_0(26, 26);
1187aq += R_aq_0.read(ba) << 0;
1188
1189// -----------------------------------------------------------------------------
1190
1191 std::stringstream ss;
1192// -----------------------------------------------------------------------------
1193ss << "amomaxud" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
1194// -----------------------------------------------------------------------------
1195 return ss.str();
1196 }
1197);
ISA32_RV64IMACFD
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
amoord_rd_rs1_rs2_rl_aq
static InstructionDefinition amoord_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoord",(uint32_t) 0x4000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOORD\n");cp.code()+="etiss_coverage_count(1, 230);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8629);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 8595, 8594, 8593, 8591);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 8600, 8599, 8598);\n";cp.code()+="etiss_coverage_count(1, 8601);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8607, 8604, 8602, 8605, 8606);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 8614, 8612, 8611, 8609, 8613);\n";} cp.code()+="etiss_uint64 res2 = res | *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(6, 8623, 8622, 8616, 8621, 8620, 8618);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(4, 8628, 8626, 8625, 8627);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOORD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoord"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
amomaxud_rd_rs1_rs2_rl_aq
static InstructionDefinition amomaxud_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amomaxud",(uint32_t) 0xe000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOMAXUD\n");cp.code()+="etiss_coverage_count(1, 234);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8829);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 8786, 8785, 8784, 8782);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint64 res1 = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 8791, 8790, 8789);\n";cp.code()+="etiss_coverage_count(1, 8792);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8798, 8795, 8793, 8796, 8797);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(res1);\n";cp.code()+="etiss_coverage_count(6, 8807, 8803, 8802, 8800, 8806, 8804);\n";} cp.code()+="etiss_uint64 res2 = (res1 < *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) ? (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) : (res1);\n";cp.code()+="etiss_coverage_count(11, 8823, 8822, 8815, 8809, 8814, 8813, 8811, 8820, 8819, 8817, 8821);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(4, 8828, 8826, 8825, 8827);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOMAXUD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amomaxud"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
amoswapd_rd_rs1_rs2_rl_aq
static InstructionDefinition amoswapd_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoswapd",(uint32_t) 0x800302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOSWAPD\n");cp.code()+="etiss_coverage_count(1, 226);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8465);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 8432, 8431, 8430, 8428);\n";cp.code()+="etiss_coverage_count(1, 8433);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8439, 8436, 8434, 8437, 8438);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(((etiss_int64)(mem_val_0)));\n";cp.code()+="etiss_coverage_count(9, 8453, 8444, 8443, 8441, 8452, 8449, 8447, 8446, 8450);\n";} cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(7, 8464, 8456, 8455, 8463, 8461, 8460, 8458);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOSWAPD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoswapd"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
amoxord_rd_rs1_rs2_rl_aq
static InstructionDefinition amoxord_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoxord",(uint32_t) 0x2000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOXORD\n");cp.code()+="etiss_coverage_count(1, 228);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8547);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 8513, 8512, 8511, 8509);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 8518, 8517, 8516);\n";cp.code()+="etiss_coverage_count(1, 8519);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8525, 8522, 8520, 8523, 8524);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 8532, 8530, 8529, 8527, 8531);\n";} cp.code()+="etiss_uint64 res2 = res ^ *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(6, 8541, 8540, 8534, 8539, 8538, 8536);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(4, 8546, 8544, 8543, 8545);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOXORD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoxord"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
amoandd_rd_rs1_rs2_rl_aq
static InstructionDefinition amoandd_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoandd",(uint32_t) 0x6000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOANDD\n");cp.code()+="etiss_coverage_count(1, 229);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8588);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 8554, 8553, 8552, 8550);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 8559, 8558, 8557);\n";cp.code()+="etiss_coverage_count(1, 8560);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8566, 8563, 8561, 8564, 8565);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 8573, 8571, 8570, 8568, 8572);\n";} cp.code()+="etiss_uint64 res2 = res & *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(6, 8582, 8581, 8575, 8580, 8579, 8577);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(4, 8587, 8585, 8584, 8586);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOANDD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoandd"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
amomaxd_rd_rs1_rs2_rl_aq
static InstructionDefinition amomaxd_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amomaxd",(uint32_t) 0xa000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOMAXD\n");cp.code()+="etiss_coverage_count(1, 232);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8729);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 8686, 8685, 8684, 8682);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 8691, 8690, 8689);\n";cp.code()+="etiss_coverage_count(1, 8692);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8698, 8695, 8693, 8696, 8697);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 8705, 8703, 8702, 8700, 8704);\n";} cp.code()+="etiss_uint64 res2 = (res < (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) ? (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) : (res);\n";cp.code()+="etiss_coverage_count(12, 8723, 8722, 8715, 8707, 8714, 8712, 8711, 8709, 8720, 8719, 8717, 8721);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(4, 8728, 8726, 8725, 8727);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOMAXD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amomaxd"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
amoaddd_rd_rs1_rs2_rl_aq
static InstructionDefinition amoaddd_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoaddd",(uint32_t) 0x00302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOADDD\n");cp.code()+="etiss_coverage_count(1, 227);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8506);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 8472, 8471, 8470, 8468);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 8477, 8476, 8475);\n";cp.code()+="etiss_coverage_count(1, 8478);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8484, 8481, 8479, 8482, 8483);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 8491, 8489, 8488, 8486, 8490);\n";} cp.code()+="etiss_uint64 res2 = res + *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(6, 8500, 8499, 8493, 8498, 8497, 8495);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(4, 8505, 8503, 8502, 8504);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOADDD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoaddd"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
amominud_rd_rs1_rs2_rl_aq
static InstructionDefinition amominud_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amominud",(uint32_t) 0xc000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOMINUD\n");cp.code()+="etiss_coverage_count(1, 233);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8779);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 8736, 8735, 8734, 8732);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint64 res = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 8741, 8740, 8739);\n";cp.code()+="etiss_coverage_count(1, 8742);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8748, 8745, 8743, 8746, 8747);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(res);\n";cp.code()+="etiss_coverage_count(6, 8757, 8753, 8752, 8750, 8756, 8754);\n";} cp.code()+="etiss_uint64 res2 = (res > *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) ? (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) : (res);\n";cp.code()+="etiss_coverage_count(11, 8773, 8772, 8765, 8759, 8764, 8763, 8761, 8770, 8769, 8767, 8771);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(4, 8778, 8776, 8775, 8777);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOMINUD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amominud"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
amomind_rd_rs1_rs2_rl_aq
static InstructionDefinition amomind_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amomind",(uint32_t) 0x8000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOMIND\n");cp.code()+="etiss_coverage_count(1, 231);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8679);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 8636, 8635, 8634, 8632);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res1 = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 8641, 8640, 8639);\n";cp.code()+="etiss_coverage_count(1, 8642);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8648, 8645, 8643, 8646, 8647);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res1;\n";cp.code()+="etiss_coverage_count(5, 8655, 8653, 8652, 8650, 8654);\n";} cp.code()+="etiss_uint64 res2 = (res1 > (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) ? (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) : (res1);\n";cp.code()+="etiss_coverage_count(12, 8673, 8672, 8665, 8657, 8664, 8662, 8661, 8659, 8670, 8669, 8667, 8671);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(4, 8678, 8676, 8675, 8677);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOMIND\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amomind"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
etiss_uint8
uint8_t etiss_uint8
Definition types.h:87
etiss::CodePart
Contains a small code snipped.
Definition CodePart.h:386
etiss::CodePart::APPENDEDRETURNINGREQUIRED
@ APPENDEDRETURNINGREQUIRED
Definition CodePart.h:402
etiss::CodePart::code
std::string & code()
Definition CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition Benchmark.h:53
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