20 (uint32_t) 0xf800707f,
32rd += R_rd_0.
read(ba) << 0;
35rs1 += R_rs1_0.
read(ba) << 0;
38rs2 += R_rs2_0.
read(ba) << 0;
41rl += R_rl_0.
read(ba) << 0;
44aq += R_aq_0.
read(ba) << 0;
52 cp.
code() = std::string(
"//AMOSWAPD\n");
55cp.
code() +=
"etiss_coverage_count(1, 226);\n";
57cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
58cp.
code() +=
"{ // block\n";
60cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
61cp.
code() +=
"} // block\n";
64cp.
code() +=
"etiss_coverage_count(1, 8465);\n";
65cp.
code() +=
"{ // block\n";
66cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
67cp.
code() +=
"etiss_coverage_count(4, 8432, 8431, 8430, 8428);\n";
68cp.
code() +=
"etiss_coverage_count(1, 8433);\n";
69if ((rd % 32ULL) != 0LL) {
70cp.
code() +=
"etiss_coverage_count(5, 8439, 8436, 8434, 8437, 8438);\n";
71cp.
code() +=
"etiss_uint64 mem_val_0;\n";
72cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
73cp.
code() +=
"if (cpu->exception) { // conditional\n";
75cp.
code() +=
"{ // procedure\n";
76cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
78cp.
code() +=
"} // procedure\n";
80cp.
code() +=
"} // conditional\n";
81cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = (etiss_int64)(((etiss_int64)(mem_val_0)));\n";
82cp.
code() +=
"etiss_coverage_count(9, 8453, 8444, 8443, 8441, 8452, 8449, 8447, 8446, 8450);\n";
84cp.
code() +=
"etiss_uint64 mem_val_1;\n";
85cp.
code() +=
"mem_val_1 = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL]);\n";
86cp.
code() +=
"etiss_coverage_count(7, 8464, 8456, 8455, 8463, 8461, 8460, 8458);\n";
87cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
88cp.
code() +=
"if (cpu->exception) { // conditional\n";
90cp.
code() +=
"{ // procedure\n";
91cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
93cp.
code() +=
"} // procedure\n";
95cp.
code() +=
"} // conditional\n";
96cp.
code() +=
"} // block\n";
99cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
106 cp.
code() = std::string(
"//AMOSWAPD\n");
109cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
121rd += R_rd_0.read(ba) << 0;
124rs1 += R_rs1_0.read(ba) << 0;
127rs2 += R_rs2_0.read(ba) << 0;
130rl += R_rl_0.read(ba) << 0;
133aq += R_aq_0.read(ba) << 0;
137 std::stringstream ss;
139ss <<
"amoswapd" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
150 (uint32_t) 0xf800707f,
162rd += R_rd_0.
read(ba) << 0;
165rs1 += R_rs1_0.
read(ba) << 0;
168rs2 += R_rs2_0.
read(ba) << 0;
171rl += R_rl_0.
read(ba) << 0;
174aq += R_aq_0.
read(ba) << 0;
182 cp.
code() = std::string(
"//AMOADDD\n");
185cp.
code() +=
"etiss_coverage_count(1, 227);\n";
187cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
188cp.
code() +=
"{ // block\n";
190cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
191cp.
code() +=
"} // block\n";
194cp.
code() +=
"etiss_coverage_count(1, 8506);\n";
195cp.
code() +=
"{ // block\n";
196cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
197cp.
code() +=
"etiss_coverage_count(4, 8472, 8471, 8470, 8468);\n";
198cp.
code() +=
"etiss_uint64 mem_val_0;\n";
199cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
200cp.
code() +=
"if (cpu->exception) { // conditional\n";
202cp.
code() +=
"{ // procedure\n";
203cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
205cp.
code() +=
"} // procedure\n";
207cp.
code() +=
"} // conditional\n";
208cp.
code() +=
"etiss_int64 res = mem_val_0;\n";
209cp.
code() +=
"etiss_coverage_count(3, 8477, 8476, 8475);\n";
210cp.
code() +=
"etiss_coverage_count(1, 8478);\n";
211if ((rd % 32ULL) != 0LL) {
212cp.
code() +=
"etiss_coverage_count(5, 8484, 8481, 8479, 8482, 8483);\n";
213cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = res;\n";
214cp.
code() +=
"etiss_coverage_count(5, 8491, 8489, 8488, 8486, 8490);\n";
216cp.
code() +=
"etiss_uint64 res2 = res + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL];\n";
217cp.
code() +=
"etiss_coverage_count(6, 8500, 8499, 8493, 8498, 8497, 8495);\n";
218cp.
code() +=
"etiss_uint64 mem_val_1;\n";
219cp.
code() +=
"mem_val_1 = res2;\n";
220cp.
code() +=
"etiss_coverage_count(4, 8505, 8503, 8502, 8504);\n";
221cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
222cp.
code() +=
"if (cpu->exception) { // conditional\n";
224cp.
code() +=
"{ // procedure\n";
225cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
227cp.
code() +=
"} // procedure\n";
229cp.
code() +=
"} // conditional\n";
230cp.
code() +=
"} // block\n";
233cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
240 cp.
code() = std::string(
"//AMOADDD\n");
243cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
255rd += R_rd_0.read(ba) << 0;
258rs1 += R_rs1_0.read(ba) << 0;
261rs2 += R_rs2_0.read(ba) << 0;
264rl += R_rl_0.read(ba) << 0;
267aq += R_aq_0.read(ba) << 0;
271 std::stringstream ss;
273ss <<
"amoaddd" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
283 (uint32_t) 0x2000302f,
284 (uint32_t) 0xf800707f,
296rd += R_rd_0.
read(ba) << 0;
299rs1 += R_rs1_0.
read(ba) << 0;
302rs2 += R_rs2_0.
read(ba) << 0;
305rl += R_rl_0.
read(ba) << 0;
308aq += R_aq_0.
read(ba) << 0;
316 cp.
code() = std::string(
"//AMOXORD\n");
319cp.
code() +=
"etiss_coverage_count(1, 228);\n";
321cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
322cp.
code() +=
"{ // block\n";
324cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
325cp.
code() +=
"} // block\n";
328cp.
code() +=
"etiss_coverage_count(1, 8547);\n";
329cp.
code() +=
"{ // block\n";
330cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
331cp.
code() +=
"etiss_coverage_count(4, 8513, 8512, 8511, 8509);\n";
332cp.
code() +=
"etiss_uint64 mem_val_0;\n";
333cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
334cp.
code() +=
"if (cpu->exception) { // conditional\n";
336cp.
code() +=
"{ // procedure\n";
337cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
339cp.
code() +=
"} // procedure\n";
341cp.
code() +=
"} // conditional\n";
342cp.
code() +=
"etiss_int64 res = mem_val_0;\n";
343cp.
code() +=
"etiss_coverage_count(3, 8518, 8517, 8516);\n";
344cp.
code() +=
"etiss_coverage_count(1, 8519);\n";
345if ((rd % 32ULL) != 0LL) {
346cp.
code() +=
"etiss_coverage_count(5, 8525, 8522, 8520, 8523, 8524);\n";
347cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = res;\n";
348cp.
code() +=
"etiss_coverage_count(5, 8532, 8530, 8529, 8527, 8531);\n";
350cp.
code() +=
"etiss_uint64 res2 = res ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL];\n";
351cp.
code() +=
"etiss_coverage_count(6, 8541, 8540, 8534, 8539, 8538, 8536);\n";
352cp.
code() +=
"etiss_uint64 mem_val_1;\n";
353cp.
code() +=
"mem_val_1 = res2;\n";
354cp.
code() +=
"etiss_coverage_count(4, 8546, 8544, 8543, 8545);\n";
355cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
356cp.
code() +=
"if (cpu->exception) { // conditional\n";
358cp.
code() +=
"{ // procedure\n";
359cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
361cp.
code() +=
"} // procedure\n";
363cp.
code() +=
"} // conditional\n";
364cp.
code() +=
"} // block\n";
367cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
374 cp.
code() = std::string(
"//AMOXORD\n");
377cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
389rd += R_rd_0.read(ba) << 0;
392rs1 += R_rs1_0.read(ba) << 0;
395rs2 += R_rs2_0.read(ba) << 0;
398rl += R_rl_0.read(ba) << 0;
401aq += R_aq_0.read(ba) << 0;
405 std::stringstream ss;
407ss <<
"amoxord" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
417 (uint32_t) 0x6000302f,
418 (uint32_t) 0xf800707f,
430rd += R_rd_0.
read(ba) << 0;
433rs1 += R_rs1_0.
read(ba) << 0;
436rs2 += R_rs2_0.
read(ba) << 0;
439rl += R_rl_0.
read(ba) << 0;
442aq += R_aq_0.
read(ba) << 0;
450 cp.
code() = std::string(
"//AMOANDD\n");
453cp.
code() +=
"etiss_coverage_count(1, 229);\n";
455cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
456cp.
code() +=
"{ // block\n";
458cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
459cp.
code() +=
"} // block\n";
462cp.
code() +=
"etiss_coverage_count(1, 8588);\n";
463cp.
code() +=
"{ // block\n";
464cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
465cp.
code() +=
"etiss_coverage_count(4, 8554, 8553, 8552, 8550);\n";
466cp.
code() +=
"etiss_uint64 mem_val_0;\n";
467cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
468cp.
code() +=
"if (cpu->exception) { // conditional\n";
470cp.
code() +=
"{ // procedure\n";
471cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
473cp.
code() +=
"} // procedure\n";
475cp.
code() +=
"} // conditional\n";
476cp.
code() +=
"etiss_int64 res = mem_val_0;\n";
477cp.
code() +=
"etiss_coverage_count(3, 8559, 8558, 8557);\n";
478cp.
code() +=
"etiss_coverage_count(1, 8560);\n";
479if ((rd % 32ULL) != 0LL) {
480cp.
code() +=
"etiss_coverage_count(5, 8566, 8563, 8561, 8564, 8565);\n";
481cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = res;\n";
482cp.
code() +=
"etiss_coverage_count(5, 8573, 8571, 8570, 8568, 8572);\n";
484cp.
code() +=
"etiss_uint64 res2 = res & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL];\n";
485cp.
code() +=
"etiss_coverage_count(6, 8582, 8581, 8575, 8580, 8579, 8577);\n";
486cp.
code() +=
"etiss_uint64 mem_val_1;\n";
487cp.
code() +=
"mem_val_1 = res2;\n";
488cp.
code() +=
"etiss_coverage_count(4, 8587, 8585, 8584, 8586);\n";
489cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
490cp.
code() +=
"if (cpu->exception) { // conditional\n";
492cp.
code() +=
"{ // procedure\n";
493cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
495cp.
code() +=
"} // procedure\n";
497cp.
code() +=
"} // conditional\n";
498cp.
code() +=
"} // block\n";
501cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
508 cp.
code() = std::string(
"//AMOANDD\n");
511cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
523rd += R_rd_0.read(ba) << 0;
526rs1 += R_rs1_0.read(ba) << 0;
529rs2 += R_rs2_0.read(ba) << 0;
532rl += R_rl_0.read(ba) << 0;
535aq += R_aq_0.read(ba) << 0;
539 std::stringstream ss;
541ss <<
"amoandd" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
551 (uint32_t) 0x4000302f,
552 (uint32_t) 0xf800707f,
564rd += R_rd_0.
read(ba) << 0;
567rs1 += R_rs1_0.
read(ba) << 0;
570rs2 += R_rs2_0.
read(ba) << 0;
573rl += R_rl_0.
read(ba) << 0;
576aq += R_aq_0.
read(ba) << 0;
584 cp.
code() = std::string(
"//AMOORD\n");
587cp.
code() +=
"etiss_coverage_count(1, 230);\n";
589cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
590cp.
code() +=
"{ // block\n";
592cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
593cp.
code() +=
"} // block\n";
596cp.
code() +=
"etiss_coverage_count(1, 8629);\n";
597cp.
code() +=
"{ // block\n";
598cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
599cp.
code() +=
"etiss_coverage_count(4, 8595, 8594, 8593, 8591);\n";
600cp.
code() +=
"etiss_uint64 mem_val_0;\n";
601cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
602cp.
code() +=
"if (cpu->exception) { // conditional\n";
604cp.
code() +=
"{ // procedure\n";
605cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
607cp.
code() +=
"} // procedure\n";
609cp.
code() +=
"} // conditional\n";
610cp.
code() +=
"etiss_int64 res = mem_val_0;\n";
611cp.
code() +=
"etiss_coverage_count(3, 8600, 8599, 8598);\n";
612cp.
code() +=
"etiss_coverage_count(1, 8601);\n";
613if ((rd % 32ULL) != 0LL) {
614cp.
code() +=
"etiss_coverage_count(5, 8607, 8604, 8602, 8605, 8606);\n";
615cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = res;\n";
616cp.
code() +=
"etiss_coverage_count(5, 8614, 8612, 8611, 8609, 8613);\n";
618cp.
code() +=
"etiss_uint64 res2 = res | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL];\n";
619cp.
code() +=
"etiss_coverage_count(6, 8623, 8622, 8616, 8621, 8620, 8618);\n";
620cp.
code() +=
"etiss_uint64 mem_val_1;\n";
621cp.
code() +=
"mem_val_1 = res2;\n";
622cp.
code() +=
"etiss_coverage_count(4, 8628, 8626, 8625, 8627);\n";
623cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
624cp.
code() +=
"if (cpu->exception) { // conditional\n";
626cp.
code() +=
"{ // procedure\n";
627cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
629cp.
code() +=
"} // procedure\n";
631cp.
code() +=
"} // conditional\n";
632cp.
code() +=
"} // block\n";
635cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
642 cp.
code() = std::string(
"//AMOORD\n");
645cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
657rd += R_rd_0.read(ba) << 0;
660rs1 += R_rs1_0.read(ba) << 0;
663rs2 += R_rs2_0.read(ba) << 0;
666rl += R_rl_0.read(ba) << 0;
669aq += R_aq_0.read(ba) << 0;
673 std::stringstream ss;
675ss <<
"amoord" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
685 (uint32_t) 0x8000302f,
686 (uint32_t) 0xf800707f,
698rd += R_rd_0.
read(ba) << 0;
701rs1 += R_rs1_0.
read(ba) << 0;
704rs2 += R_rs2_0.
read(ba) << 0;
707rl += R_rl_0.
read(ba) << 0;
710aq += R_aq_0.
read(ba) << 0;
718 cp.
code() = std::string(
"//AMOMIND\n");
721cp.
code() +=
"etiss_coverage_count(1, 231);\n";
723cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
724cp.
code() +=
"{ // block\n";
726cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
727cp.
code() +=
"} // block\n";
730cp.
code() +=
"etiss_coverage_count(1, 8679);\n";
731cp.
code() +=
"{ // block\n";
732cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
733cp.
code() +=
"etiss_coverage_count(4, 8636, 8635, 8634, 8632);\n";
734cp.
code() +=
"etiss_uint64 mem_val_0;\n";
735cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
736cp.
code() +=
"if (cpu->exception) { // conditional\n";
738cp.
code() +=
"{ // procedure\n";
739cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
741cp.
code() +=
"} // procedure\n";
743cp.
code() +=
"} // conditional\n";
744cp.
code() +=
"etiss_int64 res1 = mem_val_0;\n";
745cp.
code() +=
"etiss_coverage_count(3, 8641, 8640, 8639);\n";
746cp.
code() +=
"etiss_coverage_count(1, 8642);\n";
747if ((rd % 32ULL) != 0LL) {
748cp.
code() +=
"etiss_coverage_count(5, 8648, 8645, 8643, 8646, 8647);\n";
749cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = res1;\n";
750cp.
code() +=
"etiss_coverage_count(5, 8655, 8653, 8652, 8650, 8654);\n";
752cp.
code() +=
"etiss_uint64 res2 = (res1 > (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL]) : (res1);\n";
753cp.
code() +=
"etiss_coverage_count(12, 8673, 8672, 8665, 8657, 8664, 8662, 8661, 8659, 8670, 8669, 8667, 8671);\n";
754cp.
code() +=
"etiss_uint64 mem_val_1;\n";
755cp.
code() +=
"mem_val_1 = res2;\n";
756cp.
code() +=
"etiss_coverage_count(4, 8678, 8676, 8675, 8677);\n";
757cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
758cp.
code() +=
"if (cpu->exception) { // conditional\n";
760cp.
code() +=
"{ // procedure\n";
761cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
763cp.
code() +=
"} // procedure\n";
765cp.
code() +=
"} // conditional\n";
766cp.
code() +=
"} // block\n";
769cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
776 cp.
code() = std::string(
"//AMOMIND\n");
779cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
791rd += R_rd_0.read(ba) << 0;
794rs1 += R_rs1_0.read(ba) << 0;
797rs2 += R_rs2_0.read(ba) << 0;
800rl += R_rl_0.read(ba) << 0;
803aq += R_aq_0.read(ba) << 0;
807 std::stringstream ss;
809ss <<
"amomind" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
819 (uint32_t) 0xa000302f,
820 (uint32_t) 0xf800707f,
832rd += R_rd_0.
read(ba) << 0;
835rs1 += R_rs1_0.
read(ba) << 0;
838rs2 += R_rs2_0.
read(ba) << 0;
841rl += R_rl_0.
read(ba) << 0;
844aq += R_aq_0.
read(ba) << 0;
852 cp.
code() = std::string(
"//AMOMAXD\n");
855cp.
code() +=
"etiss_coverage_count(1, 232);\n";
857cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
858cp.
code() +=
"{ // block\n";
860cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
861cp.
code() +=
"} // block\n";
864cp.
code() +=
"etiss_coverage_count(1, 8729);\n";
865cp.
code() +=
"{ // block\n";
866cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
867cp.
code() +=
"etiss_coverage_count(4, 8686, 8685, 8684, 8682);\n";
868cp.
code() +=
"etiss_uint64 mem_val_0;\n";
869cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
870cp.
code() +=
"if (cpu->exception) { // conditional\n";
872cp.
code() +=
"{ // procedure\n";
873cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
875cp.
code() +=
"} // procedure\n";
877cp.
code() +=
"} // conditional\n";
878cp.
code() +=
"etiss_int64 res = mem_val_0;\n";
879cp.
code() +=
"etiss_coverage_count(3, 8691, 8690, 8689);\n";
880cp.
code() +=
"etiss_coverage_count(1, 8692);\n";
881if ((rd % 32ULL) != 0LL) {
882cp.
code() +=
"etiss_coverage_count(5, 8698, 8695, 8693, 8696, 8697);\n";
883cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = res;\n";
884cp.
code() +=
"etiss_coverage_count(5, 8705, 8703, 8702, 8700, 8704);\n";
886cp.
code() +=
"etiss_uint64 res2 = (res < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL]) : (res);\n";
887cp.
code() +=
"etiss_coverage_count(12, 8723, 8722, 8715, 8707, 8714, 8712, 8711, 8709, 8720, 8719, 8717, 8721);\n";
888cp.
code() +=
"etiss_uint64 mem_val_1;\n";
889cp.
code() +=
"mem_val_1 = res2;\n";
890cp.
code() +=
"etiss_coverage_count(4, 8728, 8726, 8725, 8727);\n";
891cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
892cp.
code() +=
"if (cpu->exception) { // conditional\n";
894cp.
code() +=
"{ // procedure\n";
895cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
897cp.
code() +=
"} // procedure\n";
899cp.
code() +=
"} // conditional\n";
900cp.
code() +=
"} // block\n";
903cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
910 cp.
code() = std::string(
"//AMOMAXD\n");
913cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
925rd += R_rd_0.read(ba) << 0;
928rs1 += R_rs1_0.read(ba) << 0;
931rs2 += R_rs2_0.read(ba) << 0;
934rl += R_rl_0.read(ba) << 0;
937aq += R_aq_0.read(ba) << 0;
941 std::stringstream ss;
943ss <<
"amomaxd" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
953 (uint32_t) 0xc000302f,
954 (uint32_t) 0xf800707f,
966rd += R_rd_0.
read(ba) << 0;
969rs1 += R_rs1_0.
read(ba) << 0;
972rs2 += R_rs2_0.
read(ba) << 0;
975rl += R_rl_0.
read(ba) << 0;
978aq += R_aq_0.
read(ba) << 0;
986 cp.
code() = std::string(
"//AMOMINUD\n");
989cp.
code() +=
"etiss_coverage_count(1, 233);\n";
991cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
992cp.
code() +=
"{ // block\n";
994cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
995cp.
code() +=
"} // block\n";
998cp.
code() +=
"etiss_coverage_count(1, 8779);\n";
999cp.
code() +=
"{ // block\n";
1000cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
1001cp.
code() +=
"etiss_coverage_count(4, 8736, 8735, 8734, 8732);\n";
1002cp.
code() +=
"etiss_uint64 mem_val_0;\n";
1003cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
1004cp.
code() +=
"if (cpu->exception) { // conditional\n";
1006cp.
code() +=
"{ // procedure\n";
1007cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1009cp.
code() +=
"} // procedure\n";
1011cp.
code() +=
"} // conditional\n";
1012cp.
code() +=
"etiss_uint64 res = mem_val_0;\n";
1013cp.
code() +=
"etiss_coverage_count(3, 8741, 8740, 8739);\n";
1014cp.
code() +=
"etiss_coverage_count(1, 8742);\n";
1015if ((rd % 32ULL) != 0LL) {
1016cp.
code() +=
"etiss_coverage_count(5, 8748, 8745, 8743, 8746, 8747);\n";
1017cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = (etiss_int64)(res);\n";
1018cp.
code() +=
"etiss_coverage_count(6, 8757, 8753, 8752, 8750, 8756, 8754);\n";
1020cp.
code() +=
"etiss_uint64 res2 = (res > *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL]) : (res);\n";
1021cp.
code() +=
"etiss_coverage_count(11, 8773, 8772, 8765, 8759, 8764, 8763, 8761, 8770, 8769, 8767, 8771);\n";
1022cp.
code() +=
"etiss_uint64 mem_val_1;\n";
1023cp.
code() +=
"mem_val_1 = res2;\n";
1024cp.
code() +=
"etiss_coverage_count(4, 8778, 8776, 8775, 8777);\n";
1025cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
1026cp.
code() +=
"if (cpu->exception) { // conditional\n";
1028cp.
code() +=
"{ // procedure\n";
1029cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1031cp.
code() +=
"} // procedure\n";
1033cp.
code() +=
"} // conditional\n";
1034cp.
code() +=
"} // block\n";
1037cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
1044 cp.
code() = std::string(
"//AMOMINUD\n");
1047cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1059rd += R_rd_0.read(ba) << 0;
1062rs1 += R_rs1_0.read(ba) << 0;
1065rs2 += R_rs2_0.read(ba) << 0;
1068rl += R_rl_0.read(ba) << 0;
1071aq += R_aq_0.read(ba) << 0;
1075 std::stringstream ss;
1077ss <<
"amominud" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
1087 (uint32_t) 0xe000302f,
1088 (uint32_t) 0xf800707f,
1100rd += R_rd_0.
read(ba) << 0;
1103rs1 += R_rs1_0.
read(ba) << 0;
1106rs2 += R_rs2_0.
read(ba) << 0;
1109rl += R_rl_0.
read(ba) << 0;
1112aq += R_aq_0.
read(ba) << 0;
1120 cp.
code() = std::string(
"//AMOMAXUD\n");
1123cp.
code() +=
"etiss_coverage_count(1, 234);\n";
1125cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
1126cp.
code() +=
"{ // block\n";
1128cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1129cp.
code() +=
"} // block\n";
1132cp.
code() +=
"etiss_coverage_count(1, 8829);\n";
1133cp.
code() +=
"{ // block\n";
1134cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
1135cp.
code() +=
"etiss_coverage_count(4, 8786, 8785, 8784, 8782);\n";
1136cp.
code() +=
"etiss_uint64 mem_val_0;\n";
1137cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
1138cp.
code() +=
"if (cpu->exception) { // conditional\n";
1140cp.
code() +=
"{ // procedure\n";
1141cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1143cp.
code() +=
"} // procedure\n";
1145cp.
code() +=
"} // conditional\n";
1146cp.
code() +=
"etiss_uint64 res1 = mem_val_0;\n";
1147cp.
code() +=
"etiss_coverage_count(3, 8791, 8790, 8789);\n";
1148cp.
code() +=
"etiss_coverage_count(1, 8792);\n";
1149if ((rd % 32ULL) != 0LL) {
1150cp.
code() +=
"etiss_coverage_count(5, 8798, 8795, 8793, 8796, 8797);\n";
1151cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = (etiss_int64)(res1);\n";
1152cp.
code() +=
"etiss_coverage_count(6, 8807, 8803, 8802, 8800, 8806, 8804);\n";
1154cp.
code() +=
"etiss_uint64 res2 = (res1 < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL]) : (res1);\n";
1155cp.
code() +=
"etiss_coverage_count(11, 8823, 8822, 8815, 8809, 8814, 8813, 8811, 8820, 8819, 8817, 8821);\n";
1156cp.
code() +=
"etiss_uint64 mem_val_1;\n";
1157cp.
code() +=
"mem_val_1 = res2;\n";
1158cp.
code() +=
"etiss_coverage_count(4, 8828, 8826, 8825, 8827);\n";
1159cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
1160cp.
code() +=
"if (cpu->exception) { // conditional\n";
1162cp.
code() +=
"{ // procedure\n";
1163cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1165cp.
code() +=
"} // procedure\n";
1167cp.
code() +=
"} // conditional\n";
1168cp.
code() +=
"} // block\n";
1171cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
1178 cp.
code() = std::string(
"//AMOMAXUD\n");
1181cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1193rd += R_rd_0.read(ba) << 0;
1196rs1 += R_rs1_0.read(ba) << 0;
1199rs2 += R_rs2_0.read(ba) << 0;
1202rl += R_rl_0.read(ba) << 0;
1205aq += R_aq_0.read(ba) << 0;
1209 std::stringstream ss;
1211ss <<
"amomaxud" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
static InstructionDefinition amoord_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoord",(uint32_t) 0x4000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOORD\n");cp.code()+="etiss_coverage_count(1, 230);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8629);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 8595, 8594, 8593, 8591);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 8600, 8599, 8598);\n";cp.code()+="etiss_coverage_count(1, 8601);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8607, 8604, 8602, 8605, 8606);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 8614, 8612, 8611, 8609, 8613);\n";} cp.code()+="etiss_uint64 res2 = res | *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(6, 8623, 8622, 8616, 8621, 8620, 8618);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(4, 8628, 8626, 8625, 8627);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOORD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoord"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amomaxud_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amomaxud",(uint32_t) 0xe000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOMAXUD\n");cp.code()+="etiss_coverage_count(1, 234);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8829);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 8786, 8785, 8784, 8782);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint64 res1 = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 8791, 8790, 8789);\n";cp.code()+="etiss_coverage_count(1, 8792);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8798, 8795, 8793, 8796, 8797);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(res1);\n";cp.code()+="etiss_coverage_count(6, 8807, 8803, 8802, 8800, 8806, 8804);\n";} cp.code()+="etiss_uint64 res2 = (res1 < *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) ? (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) : (res1);\n";cp.code()+="etiss_coverage_count(11, 8823, 8822, 8815, 8809, 8814, 8813, 8811, 8820, 8819, 8817, 8821);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(4, 8828, 8826, 8825, 8827);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOMAXUD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amomaxud"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amoswapd_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoswapd",(uint32_t) 0x800302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOSWAPD\n");cp.code()+="etiss_coverage_count(1, 226);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8465);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 8432, 8431, 8430, 8428);\n";cp.code()+="etiss_coverage_count(1, 8433);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8439, 8436, 8434, 8437, 8438);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(((etiss_int64)(mem_val_0)));\n";cp.code()+="etiss_coverage_count(9, 8453, 8444, 8443, 8441, 8452, 8449, 8447, 8446, 8450);\n";} cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(7, 8464, 8456, 8455, 8463, 8461, 8460, 8458);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOSWAPD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoswapd"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amoxord_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoxord",(uint32_t) 0x2000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOXORD\n");cp.code()+="etiss_coverage_count(1, 228);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8547);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 8513, 8512, 8511, 8509);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 8518, 8517, 8516);\n";cp.code()+="etiss_coverage_count(1, 8519);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8525, 8522, 8520, 8523, 8524);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 8532, 8530, 8529, 8527, 8531);\n";} cp.code()+="etiss_uint64 res2 = res ^ *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(6, 8541, 8540, 8534, 8539, 8538, 8536);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(4, 8546, 8544, 8543, 8545);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOXORD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoxord"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amoandd_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoandd",(uint32_t) 0x6000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOANDD\n");cp.code()+="etiss_coverage_count(1, 229);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8588);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 8554, 8553, 8552, 8550);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 8559, 8558, 8557);\n";cp.code()+="etiss_coverage_count(1, 8560);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8566, 8563, 8561, 8564, 8565);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 8573, 8571, 8570, 8568, 8572);\n";} cp.code()+="etiss_uint64 res2 = res & *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(6, 8582, 8581, 8575, 8580, 8579, 8577);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(4, 8587, 8585, 8584, 8586);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOANDD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoandd"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amomaxd_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amomaxd",(uint32_t) 0xa000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOMAXD\n");cp.code()+="etiss_coverage_count(1, 232);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8729);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 8686, 8685, 8684, 8682);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 8691, 8690, 8689);\n";cp.code()+="etiss_coverage_count(1, 8692);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8698, 8695, 8693, 8696, 8697);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 8705, 8703, 8702, 8700, 8704);\n";} cp.code()+="etiss_uint64 res2 = (res < (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) ? (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) : (res);\n";cp.code()+="etiss_coverage_count(12, 8723, 8722, 8715, 8707, 8714, 8712, 8711, 8709, 8720, 8719, 8717, 8721);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(4, 8728, 8726, 8725, 8727);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOMAXD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amomaxd"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amoaddd_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoaddd",(uint32_t) 0x00302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOADDD\n");cp.code()+="etiss_coverage_count(1, 227);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8506);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 8472, 8471, 8470, 8468);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 8477, 8476, 8475);\n";cp.code()+="etiss_coverage_count(1, 8478);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8484, 8481, 8479, 8482, 8483);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 8491, 8489, 8488, 8486, 8490);\n";} cp.code()+="etiss_uint64 res2 = res + *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(6, 8500, 8499, 8493, 8498, 8497, 8495);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(4, 8505, 8503, 8502, 8504);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOADDD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoaddd"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amominud_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amominud",(uint32_t) 0xc000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOMINUD\n");cp.code()+="etiss_coverage_count(1, 233);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8779);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 8736, 8735, 8734, 8732);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint64 res = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 8741, 8740, 8739);\n";cp.code()+="etiss_coverage_count(1, 8742);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8748, 8745, 8743, 8746, 8747);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(res);\n";cp.code()+="etiss_coverage_count(6, 8757, 8753, 8752, 8750, 8756, 8754);\n";} cp.code()+="etiss_uint64 res2 = (res > *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) ? (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) : (res);\n";cp.code()+="etiss_coverage_count(11, 8773, 8772, 8765, 8759, 8764, 8763, 8761, 8770, 8769, 8767, 8771);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(4, 8778, 8776, 8775, 8777);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOMINUD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amominud"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amomind_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amomind",(uint32_t) 0x8000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOMIND\n");cp.code()+="etiss_coverage_count(1, 231);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8679);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 8636, 8635, 8634, 8632);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res1 = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 8641, 8640, 8639);\n";cp.code()+="etiss_coverage_count(1, 8642);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8648, 8645, 8643, 8646, 8647);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res1;\n";cp.code()+="etiss_coverage_count(5, 8655, 8653, 8652, 8650, 8654);\n";} cp.code()+="etiss_uint64 res2 = (res1 > (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) ? (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) : (res1);\n";cp.code()+="etiss_coverage_count(12, 8673, 8672, 8665, 8657, 8664, 8662, 8661, 8659, 8670, 8669, 8667, 8671);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(4, 8678, 8676, 8675, 8677);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOMIND\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amomind"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
Contains a small code snipped.
@ APPENDEDRETURNINGREQUIRED
RegisterSet & getAffectedRegisters()
void append(const CodePart &part, CodePart::TYPE type)
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Reading through it will only return bits within the range.
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
this class contains parameters that persist in between instruction lookpus/translation within a trans...
uint64_t current_address_
start address of current instruction
holds information and translation callbacks for an instruction.