ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV64IMACFD_RV64AInstr.cpp
Go to the documentation of this file.
1 
8 #include "RV64IMACFDArch.h"
9 #include "RV64IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // AMOSWAPD --------------------------------------------------------------------
16 static InstructionDefinition amoswapd_rd_rs1_rs2_rl_aq (
17  ISA32_RV64IMACFD,
18  "amoswapd",
19  (uint32_t) 0x800302f,
20  (uint32_t) 0xf800707f,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 etiss_uint8 rd = 0;
30 static BitArrayRange R_rd_0(11, 7);
31 rd += R_rd_0.read(ba) << 0;
32 etiss_uint8 rs1 = 0;
33 static BitArrayRange R_rs1_0(19, 15);
34 rs1 += R_rs1_0.read(ba) << 0;
35 etiss_uint8 rs2 = 0;
36 static BitArrayRange R_rs2_0(24, 20);
37 rs2 += R_rs2_0.read(ba) << 0;
38 etiss_uint8 rl = 0;
39 static BitArrayRange R_rl_0(25, 25);
40 rl += R_rl_0.read(ba) << 0;
41 etiss_uint8 aq = 0;
42 static BitArrayRange R_aq_0(26, 26);
43 aq += R_aq_0.read(ba) << 0;
44 
45 // -----------------------------------------------------------------------------
46 
47  {
48  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
49 
50  cp.code() = std::string("//AMOSWAPD\n");
51 
52 // -----------------------------------------------------------------------------
53 cp.code() += "etiss_coverage_count(1, 226);\n";
54 { // block
55 cp.code() += "etiss_coverage_count(1, 1169);\n";
56 cp.code() += "{ // block\n";
57 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
58 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
59 cp.code() += "} // block\n";
60 } // block
61 { // block
62 cp.code() += "etiss_coverage_count(1, 8465);\n";
63 cp.code() += "{ // block\n";
64 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
65 cp.code() += "etiss_coverage_count(4, 8432, 8431, 8430, 8428);\n";
66 cp.code() += "etiss_coverage_count(1, 8433);\n";
67 if ((rd % 32ULL) != 0LL) { // conditional
68 cp.code() += "etiss_coverage_count(5, 8439, 8436, 8434, 8437, 8438);\n";
69 cp.code() += "etiss_uint64 mem_val_0;\n";
70 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
71 cp.code() += "if (cpu->exception) { // conditional\n";
72 { // procedure
73 cp.code() += "{ // procedure\n";
74 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
75 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
76 cp.code() += "} // procedure\n";
77 } // procedure
78 cp.code() += "} // conditional\n";
79 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(((etiss_int64)(mem_val_0)));\n";
80 cp.code() += "etiss_coverage_count(9, 8453, 8444, 8443, 8441, 8452, 8449, 8447, 8446, 8450);\n";
81 } // conditional
82 cp.code() += "etiss_uint64 mem_val_1;\n";
83 cp.code() += "mem_val_1 = (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
84 cp.code() += "etiss_coverage_count(7, 8464, 8456, 8455, 8463, 8461, 8460, 8458);\n";
85 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
86 cp.code() += "if (cpu->exception) { // conditional\n";
87 { // procedure
88 cp.code() += "{ // procedure\n";
89 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
90 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
91 cp.code() += "} // procedure\n";
92 } // procedure
93 cp.code() += "} // conditional\n";
94 cp.code() += "} // block\n";
95 } // block
96 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
97 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
98 // -----------------------------------------------------------------------------
99  cp.getAffectedRegisters().add("instructionPointer", 32);
100  }
101  {
102  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
103 
104  cp.code() = std::string("//AMOSWAPD\n");
105 
106 // -----------------------------------------------------------------------------
107 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
108 // -----------------------------------------------------------------------------
109  }
110 
111  return true;
112  },
113  0,
114  [] (BitArray & ba, Instruction & instr)
115  {
116 // -----------------------------------------------------------------------------
117 etiss_uint8 rd = 0;
118 static BitArrayRange R_rd_0(11, 7);
119 rd += R_rd_0.read(ba) << 0;
120 etiss_uint8 rs1 = 0;
121 static BitArrayRange R_rs1_0(19, 15);
122 rs1 += R_rs1_0.read(ba) << 0;
123 etiss_uint8 rs2 = 0;
124 static BitArrayRange R_rs2_0(24, 20);
125 rs2 += R_rs2_0.read(ba) << 0;
126 etiss_uint8 rl = 0;
127 static BitArrayRange R_rl_0(25, 25);
128 rl += R_rl_0.read(ba) << 0;
129 etiss_uint8 aq = 0;
130 static BitArrayRange R_aq_0(26, 26);
131 aq += R_aq_0.read(ba) << 0;
132 
133 // -----------------------------------------------------------------------------
134 
135  std::stringstream ss;
136 // -----------------------------------------------------------------------------
137 ss << "amoswapd" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
138 // -----------------------------------------------------------------------------
139  return ss.str();
140  }
141 );
142 
143 // AMOADDD ---------------------------------------------------------------------
144 static InstructionDefinition amoaddd_rd_rs1_rs2_rl_aq (
145  ISA32_RV64IMACFD,
146  "amoaddd",
147  (uint32_t) 0x00302f,
148  (uint32_t) 0xf800707f,
149  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
150  {
151 
152 // -----------------------------------------------------------------------------
153 
154 // -----------------------------------------------------------------------------
155 
156 // -----------------------------------------------------------------------------
157 etiss_uint8 rd = 0;
158 static BitArrayRange R_rd_0(11, 7);
159 rd += R_rd_0.read(ba) << 0;
160 etiss_uint8 rs1 = 0;
161 static BitArrayRange R_rs1_0(19, 15);
162 rs1 += R_rs1_0.read(ba) << 0;
163 etiss_uint8 rs2 = 0;
164 static BitArrayRange R_rs2_0(24, 20);
165 rs2 += R_rs2_0.read(ba) << 0;
166 etiss_uint8 rl = 0;
167 static BitArrayRange R_rl_0(25, 25);
168 rl += R_rl_0.read(ba) << 0;
169 etiss_uint8 aq = 0;
170 static BitArrayRange R_aq_0(26, 26);
171 aq += R_aq_0.read(ba) << 0;
172 
173 // -----------------------------------------------------------------------------
174 
175  {
176  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
177 
178  cp.code() = std::string("//AMOADDD\n");
179 
180 // -----------------------------------------------------------------------------
181 cp.code() += "etiss_coverage_count(1, 227);\n";
182 { // block
183 cp.code() += "etiss_coverage_count(1, 1169);\n";
184 cp.code() += "{ // block\n";
185 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
186 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
187 cp.code() += "} // block\n";
188 } // block
189 { // block
190 cp.code() += "etiss_coverage_count(1, 8506);\n";
191 cp.code() += "{ // block\n";
192 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
193 cp.code() += "etiss_coverage_count(4, 8472, 8471, 8470, 8468);\n";
194 cp.code() += "etiss_uint64 mem_val_0;\n";
195 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
196 cp.code() += "if (cpu->exception) { // conditional\n";
197 { // procedure
198 cp.code() += "{ // procedure\n";
199 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
200 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
201 cp.code() += "} // procedure\n";
202 } // procedure
203 cp.code() += "} // conditional\n";
204 cp.code() += "etiss_int64 res = mem_val_0;\n";
205 cp.code() += "etiss_coverage_count(3, 8477, 8476, 8475);\n";
206 cp.code() += "etiss_coverage_count(1, 8478);\n";
207 if ((rd % 32ULL) != 0LL) { // conditional
208 cp.code() += "etiss_coverage_count(5, 8484, 8481, 8479, 8482, 8483);\n";
209 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
210 cp.code() += "etiss_coverage_count(5, 8491, 8489, 8488, 8486, 8490);\n";
211 } // conditional
212 cp.code() += "etiss_uint64 res2 = res + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
213 cp.code() += "etiss_coverage_count(6, 8500, 8499, 8493, 8498, 8497, 8495);\n";
214 cp.code() += "etiss_uint64 mem_val_1;\n";
215 cp.code() += "mem_val_1 = res2;\n";
216 cp.code() += "etiss_coverage_count(4, 8505, 8503, 8502, 8504);\n";
217 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
218 cp.code() += "if (cpu->exception) { // conditional\n";
219 { // procedure
220 cp.code() += "{ // procedure\n";
221 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
222 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
223 cp.code() += "} // procedure\n";
224 } // procedure
225 cp.code() += "} // conditional\n";
226 cp.code() += "} // block\n";
227 } // block
228 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
229 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
230 // -----------------------------------------------------------------------------
231  cp.getAffectedRegisters().add("instructionPointer", 32);
232  }
233  {
234  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
235 
236  cp.code() = std::string("//AMOADDD\n");
237 
238 // -----------------------------------------------------------------------------
239 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
240 // -----------------------------------------------------------------------------
241  }
242 
243  return true;
244  },
245  0,
246  [] (BitArray & ba, Instruction & instr)
247  {
248 // -----------------------------------------------------------------------------
249 etiss_uint8 rd = 0;
250 static BitArrayRange R_rd_0(11, 7);
251 rd += R_rd_0.read(ba) << 0;
252 etiss_uint8 rs1 = 0;
253 static BitArrayRange R_rs1_0(19, 15);
254 rs1 += R_rs1_0.read(ba) << 0;
255 etiss_uint8 rs2 = 0;
256 static BitArrayRange R_rs2_0(24, 20);
257 rs2 += R_rs2_0.read(ba) << 0;
258 etiss_uint8 rl = 0;
259 static BitArrayRange R_rl_0(25, 25);
260 rl += R_rl_0.read(ba) << 0;
261 etiss_uint8 aq = 0;
262 static BitArrayRange R_aq_0(26, 26);
263 aq += R_aq_0.read(ba) << 0;
264 
265 // -----------------------------------------------------------------------------
266 
267  std::stringstream ss;
268 // -----------------------------------------------------------------------------
269 ss << "amoaddd" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
270 // -----------------------------------------------------------------------------
271  return ss.str();
272  }
273 );
274 
275 // AMOXORD ---------------------------------------------------------------------
276 static InstructionDefinition amoxord_rd_rs1_rs2_rl_aq (
277  ISA32_RV64IMACFD,
278  "amoxord",
279  (uint32_t) 0x2000302f,
280  (uint32_t) 0xf800707f,
281  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
282  {
283 
284 // -----------------------------------------------------------------------------
285 
286 // -----------------------------------------------------------------------------
287 
288 // -----------------------------------------------------------------------------
289 etiss_uint8 rd = 0;
290 static BitArrayRange R_rd_0(11, 7);
291 rd += R_rd_0.read(ba) << 0;
292 etiss_uint8 rs1 = 0;
293 static BitArrayRange R_rs1_0(19, 15);
294 rs1 += R_rs1_0.read(ba) << 0;
295 etiss_uint8 rs2 = 0;
296 static BitArrayRange R_rs2_0(24, 20);
297 rs2 += R_rs2_0.read(ba) << 0;
298 etiss_uint8 rl = 0;
299 static BitArrayRange R_rl_0(25, 25);
300 rl += R_rl_0.read(ba) << 0;
301 etiss_uint8 aq = 0;
302 static BitArrayRange R_aq_0(26, 26);
303 aq += R_aq_0.read(ba) << 0;
304 
305 // -----------------------------------------------------------------------------
306 
307  {
308  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
309 
310  cp.code() = std::string("//AMOXORD\n");
311 
312 // -----------------------------------------------------------------------------
313 cp.code() += "etiss_coverage_count(1, 228);\n";
314 { // block
315 cp.code() += "etiss_coverage_count(1, 1169);\n";
316 cp.code() += "{ // block\n";
317 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
318 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
319 cp.code() += "} // block\n";
320 } // block
321 { // block
322 cp.code() += "etiss_coverage_count(1, 8547);\n";
323 cp.code() += "{ // block\n";
324 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
325 cp.code() += "etiss_coverage_count(4, 8513, 8512, 8511, 8509);\n";
326 cp.code() += "etiss_uint64 mem_val_0;\n";
327 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
328 cp.code() += "if (cpu->exception) { // conditional\n";
329 { // procedure
330 cp.code() += "{ // procedure\n";
331 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
332 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
333 cp.code() += "} // procedure\n";
334 } // procedure
335 cp.code() += "} // conditional\n";
336 cp.code() += "etiss_int64 res = mem_val_0;\n";
337 cp.code() += "etiss_coverage_count(3, 8518, 8517, 8516);\n";
338 cp.code() += "etiss_coverage_count(1, 8519);\n";
339 if ((rd % 32ULL) != 0LL) { // conditional
340 cp.code() += "etiss_coverage_count(5, 8525, 8522, 8520, 8523, 8524);\n";
341 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
342 cp.code() += "etiss_coverage_count(5, 8532, 8530, 8529, 8527, 8531);\n";
343 } // conditional
344 cp.code() += "etiss_uint64 res2 = res ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
345 cp.code() += "etiss_coverage_count(6, 8541, 8540, 8534, 8539, 8538, 8536);\n";
346 cp.code() += "etiss_uint64 mem_val_1;\n";
347 cp.code() += "mem_val_1 = res2;\n";
348 cp.code() += "etiss_coverage_count(4, 8546, 8544, 8543, 8545);\n";
349 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
350 cp.code() += "if (cpu->exception) { // conditional\n";
351 { // procedure
352 cp.code() += "{ // procedure\n";
353 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
354 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
355 cp.code() += "} // procedure\n";
356 } // procedure
357 cp.code() += "} // conditional\n";
358 cp.code() += "} // block\n";
359 } // block
360 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
361 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
362 // -----------------------------------------------------------------------------
363  cp.getAffectedRegisters().add("instructionPointer", 32);
364  }
365  {
366  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
367 
368  cp.code() = std::string("//AMOXORD\n");
369 
370 // -----------------------------------------------------------------------------
371 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
372 // -----------------------------------------------------------------------------
373  }
374 
375  return true;
376  },
377  0,
378  [] (BitArray & ba, Instruction & instr)
379  {
380 // -----------------------------------------------------------------------------
381 etiss_uint8 rd = 0;
382 static BitArrayRange R_rd_0(11, 7);
383 rd += R_rd_0.read(ba) << 0;
384 etiss_uint8 rs1 = 0;
385 static BitArrayRange R_rs1_0(19, 15);
386 rs1 += R_rs1_0.read(ba) << 0;
387 etiss_uint8 rs2 = 0;
388 static BitArrayRange R_rs2_0(24, 20);
389 rs2 += R_rs2_0.read(ba) << 0;
390 etiss_uint8 rl = 0;
391 static BitArrayRange R_rl_0(25, 25);
392 rl += R_rl_0.read(ba) << 0;
393 etiss_uint8 aq = 0;
394 static BitArrayRange R_aq_0(26, 26);
395 aq += R_aq_0.read(ba) << 0;
396 
397 // -----------------------------------------------------------------------------
398 
399  std::stringstream ss;
400 // -----------------------------------------------------------------------------
401 ss << "amoxord" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
402 // -----------------------------------------------------------------------------
403  return ss.str();
404  }
405 );
406 
407 // AMOANDD ---------------------------------------------------------------------
408 static InstructionDefinition amoandd_rd_rs1_rs2_rl_aq (
409  ISA32_RV64IMACFD,
410  "amoandd",
411  (uint32_t) 0x6000302f,
412  (uint32_t) 0xf800707f,
413  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
414  {
415 
416 // -----------------------------------------------------------------------------
417 
418 // -----------------------------------------------------------------------------
419 
420 // -----------------------------------------------------------------------------
421 etiss_uint8 rd = 0;
422 static BitArrayRange R_rd_0(11, 7);
423 rd += R_rd_0.read(ba) << 0;
424 etiss_uint8 rs1 = 0;
425 static BitArrayRange R_rs1_0(19, 15);
426 rs1 += R_rs1_0.read(ba) << 0;
427 etiss_uint8 rs2 = 0;
428 static BitArrayRange R_rs2_0(24, 20);
429 rs2 += R_rs2_0.read(ba) << 0;
430 etiss_uint8 rl = 0;
431 static BitArrayRange R_rl_0(25, 25);
432 rl += R_rl_0.read(ba) << 0;
433 etiss_uint8 aq = 0;
434 static BitArrayRange R_aq_0(26, 26);
435 aq += R_aq_0.read(ba) << 0;
436 
437 // -----------------------------------------------------------------------------
438 
439  {
440  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
441 
442  cp.code() = std::string("//AMOANDD\n");
443 
444 // -----------------------------------------------------------------------------
445 cp.code() += "etiss_coverage_count(1, 229);\n";
446 { // block
447 cp.code() += "etiss_coverage_count(1, 1169);\n";
448 cp.code() += "{ // block\n";
449 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
450 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
451 cp.code() += "} // block\n";
452 } // block
453 { // block
454 cp.code() += "etiss_coverage_count(1, 8588);\n";
455 cp.code() += "{ // block\n";
456 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
457 cp.code() += "etiss_coverage_count(4, 8554, 8553, 8552, 8550);\n";
458 cp.code() += "etiss_uint64 mem_val_0;\n";
459 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
460 cp.code() += "if (cpu->exception) { // conditional\n";
461 { // procedure
462 cp.code() += "{ // procedure\n";
463 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
464 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
465 cp.code() += "} // procedure\n";
466 } // procedure
467 cp.code() += "} // conditional\n";
468 cp.code() += "etiss_int64 res = mem_val_0;\n";
469 cp.code() += "etiss_coverage_count(3, 8559, 8558, 8557);\n";
470 cp.code() += "etiss_coverage_count(1, 8560);\n";
471 if ((rd % 32ULL) != 0LL) { // conditional
472 cp.code() += "etiss_coverage_count(5, 8566, 8563, 8561, 8564, 8565);\n";
473 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
474 cp.code() += "etiss_coverage_count(5, 8573, 8571, 8570, 8568, 8572);\n";
475 } // conditional
476 cp.code() += "etiss_uint64 res2 = res & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
477 cp.code() += "etiss_coverage_count(6, 8582, 8581, 8575, 8580, 8579, 8577);\n";
478 cp.code() += "etiss_uint64 mem_val_1;\n";
479 cp.code() += "mem_val_1 = res2;\n";
480 cp.code() += "etiss_coverage_count(4, 8587, 8585, 8584, 8586);\n";
481 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
482 cp.code() += "if (cpu->exception) { // conditional\n";
483 { // procedure
484 cp.code() += "{ // procedure\n";
485 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
486 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
487 cp.code() += "} // procedure\n";
488 } // procedure
489 cp.code() += "} // conditional\n";
490 cp.code() += "} // block\n";
491 } // block
492 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
493 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
494 // -----------------------------------------------------------------------------
495  cp.getAffectedRegisters().add("instructionPointer", 32);
496  }
497  {
498  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
499 
500  cp.code() = std::string("//AMOANDD\n");
501 
502 // -----------------------------------------------------------------------------
503 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
504 // -----------------------------------------------------------------------------
505  }
506 
507  return true;
508  },
509  0,
510  [] (BitArray & ba, Instruction & instr)
511  {
512 // -----------------------------------------------------------------------------
513 etiss_uint8 rd = 0;
514 static BitArrayRange R_rd_0(11, 7);
515 rd += R_rd_0.read(ba) << 0;
516 etiss_uint8 rs1 = 0;
517 static BitArrayRange R_rs1_0(19, 15);
518 rs1 += R_rs1_0.read(ba) << 0;
519 etiss_uint8 rs2 = 0;
520 static BitArrayRange R_rs2_0(24, 20);
521 rs2 += R_rs2_0.read(ba) << 0;
522 etiss_uint8 rl = 0;
523 static BitArrayRange R_rl_0(25, 25);
524 rl += R_rl_0.read(ba) << 0;
525 etiss_uint8 aq = 0;
526 static BitArrayRange R_aq_0(26, 26);
527 aq += R_aq_0.read(ba) << 0;
528 
529 // -----------------------------------------------------------------------------
530 
531  std::stringstream ss;
532 // -----------------------------------------------------------------------------
533 ss << "amoandd" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
534 // -----------------------------------------------------------------------------
535  return ss.str();
536  }
537 );
538 
539 // AMOORD ----------------------------------------------------------------------
540 static InstructionDefinition amoord_rd_rs1_rs2_rl_aq (
541  ISA32_RV64IMACFD,
542  "amoord",
543  (uint32_t) 0x4000302f,
544  (uint32_t) 0xf800707f,
545  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
546  {
547 
548 // -----------------------------------------------------------------------------
549 
550 // -----------------------------------------------------------------------------
551 
552 // -----------------------------------------------------------------------------
553 etiss_uint8 rd = 0;
554 static BitArrayRange R_rd_0(11, 7);
555 rd += R_rd_0.read(ba) << 0;
556 etiss_uint8 rs1 = 0;
557 static BitArrayRange R_rs1_0(19, 15);
558 rs1 += R_rs1_0.read(ba) << 0;
559 etiss_uint8 rs2 = 0;
560 static BitArrayRange R_rs2_0(24, 20);
561 rs2 += R_rs2_0.read(ba) << 0;
562 etiss_uint8 rl = 0;
563 static BitArrayRange R_rl_0(25, 25);
564 rl += R_rl_0.read(ba) << 0;
565 etiss_uint8 aq = 0;
566 static BitArrayRange R_aq_0(26, 26);
567 aq += R_aq_0.read(ba) << 0;
568 
569 // -----------------------------------------------------------------------------
570 
571  {
572  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
573 
574  cp.code() = std::string("//AMOORD\n");
575 
576 // -----------------------------------------------------------------------------
577 cp.code() += "etiss_coverage_count(1, 230);\n";
578 { // block
579 cp.code() += "etiss_coverage_count(1, 1169);\n";
580 cp.code() += "{ // block\n";
581 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
582 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
583 cp.code() += "} // block\n";
584 } // block
585 { // block
586 cp.code() += "etiss_coverage_count(1, 8629);\n";
587 cp.code() += "{ // block\n";
588 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
589 cp.code() += "etiss_coverage_count(4, 8595, 8594, 8593, 8591);\n";
590 cp.code() += "etiss_uint64 mem_val_0;\n";
591 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
592 cp.code() += "if (cpu->exception) { // conditional\n";
593 { // procedure
594 cp.code() += "{ // procedure\n";
595 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
596 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
597 cp.code() += "} // procedure\n";
598 } // procedure
599 cp.code() += "} // conditional\n";
600 cp.code() += "etiss_int64 res = mem_val_0;\n";
601 cp.code() += "etiss_coverage_count(3, 8600, 8599, 8598);\n";
602 cp.code() += "etiss_coverage_count(1, 8601);\n";
603 if ((rd % 32ULL) != 0LL) { // conditional
604 cp.code() += "etiss_coverage_count(5, 8607, 8604, 8602, 8605, 8606);\n";
605 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
606 cp.code() += "etiss_coverage_count(5, 8614, 8612, 8611, 8609, 8613);\n";
607 } // conditional
608 cp.code() += "etiss_uint64 res2 = res | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
609 cp.code() += "etiss_coverage_count(6, 8623, 8622, 8616, 8621, 8620, 8618);\n";
610 cp.code() += "etiss_uint64 mem_val_1;\n";
611 cp.code() += "mem_val_1 = res2;\n";
612 cp.code() += "etiss_coverage_count(4, 8628, 8626, 8625, 8627);\n";
613 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
614 cp.code() += "if (cpu->exception) { // conditional\n";
615 { // procedure
616 cp.code() += "{ // procedure\n";
617 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
618 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
619 cp.code() += "} // procedure\n";
620 } // procedure
621 cp.code() += "} // conditional\n";
622 cp.code() += "} // block\n";
623 } // block
624 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
625 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
626 // -----------------------------------------------------------------------------
627  cp.getAffectedRegisters().add("instructionPointer", 32);
628  }
629  {
630  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
631 
632  cp.code() = std::string("//AMOORD\n");
633 
634 // -----------------------------------------------------------------------------
635 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
636 // -----------------------------------------------------------------------------
637  }
638 
639  return true;
640  },
641  0,
642  [] (BitArray & ba, Instruction & instr)
643  {
644 // -----------------------------------------------------------------------------
645 etiss_uint8 rd = 0;
646 static BitArrayRange R_rd_0(11, 7);
647 rd += R_rd_0.read(ba) << 0;
648 etiss_uint8 rs1 = 0;
649 static BitArrayRange R_rs1_0(19, 15);
650 rs1 += R_rs1_0.read(ba) << 0;
651 etiss_uint8 rs2 = 0;
652 static BitArrayRange R_rs2_0(24, 20);
653 rs2 += R_rs2_0.read(ba) << 0;
654 etiss_uint8 rl = 0;
655 static BitArrayRange R_rl_0(25, 25);
656 rl += R_rl_0.read(ba) << 0;
657 etiss_uint8 aq = 0;
658 static BitArrayRange R_aq_0(26, 26);
659 aq += R_aq_0.read(ba) << 0;
660 
661 // -----------------------------------------------------------------------------
662 
663  std::stringstream ss;
664 // -----------------------------------------------------------------------------
665 ss << "amoord" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
666 // -----------------------------------------------------------------------------
667  return ss.str();
668  }
669 );
670 
671 // AMOMIND ---------------------------------------------------------------------
672 static InstructionDefinition amomind_rd_rs1_rs2_rl_aq (
673  ISA32_RV64IMACFD,
674  "amomind",
675  (uint32_t) 0x8000302f,
676  (uint32_t) 0xf800707f,
677  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
678  {
679 
680 // -----------------------------------------------------------------------------
681 
682 // -----------------------------------------------------------------------------
683 
684 // -----------------------------------------------------------------------------
685 etiss_uint8 rd = 0;
686 static BitArrayRange R_rd_0(11, 7);
687 rd += R_rd_0.read(ba) << 0;
688 etiss_uint8 rs1 = 0;
689 static BitArrayRange R_rs1_0(19, 15);
690 rs1 += R_rs1_0.read(ba) << 0;
691 etiss_uint8 rs2 = 0;
692 static BitArrayRange R_rs2_0(24, 20);
693 rs2 += R_rs2_0.read(ba) << 0;
694 etiss_uint8 rl = 0;
695 static BitArrayRange R_rl_0(25, 25);
696 rl += R_rl_0.read(ba) << 0;
697 etiss_uint8 aq = 0;
698 static BitArrayRange R_aq_0(26, 26);
699 aq += R_aq_0.read(ba) << 0;
700 
701 // -----------------------------------------------------------------------------
702 
703  {
704  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
705 
706  cp.code() = std::string("//AMOMIND\n");
707 
708 // -----------------------------------------------------------------------------
709 cp.code() += "etiss_coverage_count(1, 231);\n";
710 { // block
711 cp.code() += "etiss_coverage_count(1, 1169);\n";
712 cp.code() += "{ // block\n";
713 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
714 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
715 cp.code() += "} // block\n";
716 } // block
717 { // block
718 cp.code() += "etiss_coverage_count(1, 8679);\n";
719 cp.code() += "{ // block\n";
720 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
721 cp.code() += "etiss_coverage_count(4, 8636, 8635, 8634, 8632);\n";
722 cp.code() += "etiss_uint64 mem_val_0;\n";
723 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
724 cp.code() += "if (cpu->exception) { // conditional\n";
725 { // procedure
726 cp.code() += "{ // procedure\n";
727 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
728 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
729 cp.code() += "} // procedure\n";
730 } // procedure
731 cp.code() += "} // conditional\n";
732 cp.code() += "etiss_int64 res1 = mem_val_0;\n";
733 cp.code() += "etiss_coverage_count(3, 8641, 8640, 8639);\n";
734 cp.code() += "etiss_coverage_count(1, 8642);\n";
735 if ((rd % 32ULL) != 0LL) { // conditional
736 cp.code() += "etiss_coverage_count(5, 8648, 8645, 8643, 8646, 8647);\n";
737 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res1;\n";
738 cp.code() += "etiss_coverage_count(5, 8655, 8653, 8652, 8650, 8654);\n";
739 } // conditional
740 cp.code() += "etiss_uint64 res2 = (res1 > (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res1);\n";
741 cp.code() += "etiss_coverage_count(12, 8673, 8672, 8665, 8657, 8664, 8662, 8661, 8659, 8670, 8669, 8667, 8671);\n";
742 cp.code() += "etiss_uint64 mem_val_1;\n";
743 cp.code() += "mem_val_1 = res2;\n";
744 cp.code() += "etiss_coverage_count(4, 8678, 8676, 8675, 8677);\n";
745 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
746 cp.code() += "if (cpu->exception) { // conditional\n";
747 { // procedure
748 cp.code() += "{ // procedure\n";
749 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
750 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
751 cp.code() += "} // procedure\n";
752 } // procedure
753 cp.code() += "} // conditional\n";
754 cp.code() += "} // block\n";
755 } // block
756 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
757 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
758 // -----------------------------------------------------------------------------
759  cp.getAffectedRegisters().add("instructionPointer", 32);
760  }
761  {
762  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
763 
764  cp.code() = std::string("//AMOMIND\n");
765 
766 // -----------------------------------------------------------------------------
767 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
768 // -----------------------------------------------------------------------------
769  }
770 
771  return true;
772  },
773  0,
774  [] (BitArray & ba, Instruction & instr)
775  {
776 // -----------------------------------------------------------------------------
777 etiss_uint8 rd = 0;
778 static BitArrayRange R_rd_0(11, 7);
779 rd += R_rd_0.read(ba) << 0;
780 etiss_uint8 rs1 = 0;
781 static BitArrayRange R_rs1_0(19, 15);
782 rs1 += R_rs1_0.read(ba) << 0;
783 etiss_uint8 rs2 = 0;
784 static BitArrayRange R_rs2_0(24, 20);
785 rs2 += R_rs2_0.read(ba) << 0;
786 etiss_uint8 rl = 0;
787 static BitArrayRange R_rl_0(25, 25);
788 rl += R_rl_0.read(ba) << 0;
789 etiss_uint8 aq = 0;
790 static BitArrayRange R_aq_0(26, 26);
791 aq += R_aq_0.read(ba) << 0;
792 
793 // -----------------------------------------------------------------------------
794 
795  std::stringstream ss;
796 // -----------------------------------------------------------------------------
797 ss << "amomind" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
798 // -----------------------------------------------------------------------------
799  return ss.str();
800  }
801 );
802 
803 // AMOMAXD ---------------------------------------------------------------------
804 static InstructionDefinition amomaxd_rd_rs1_rs2_rl_aq (
805  ISA32_RV64IMACFD,
806  "amomaxd",
807  (uint32_t) 0xa000302f,
808  (uint32_t) 0xf800707f,
809  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
810  {
811 
812 // -----------------------------------------------------------------------------
813 
814 // -----------------------------------------------------------------------------
815 
816 // -----------------------------------------------------------------------------
817 etiss_uint8 rd = 0;
818 static BitArrayRange R_rd_0(11, 7);
819 rd += R_rd_0.read(ba) << 0;
820 etiss_uint8 rs1 = 0;
821 static BitArrayRange R_rs1_0(19, 15);
822 rs1 += R_rs1_0.read(ba) << 0;
823 etiss_uint8 rs2 = 0;
824 static BitArrayRange R_rs2_0(24, 20);
825 rs2 += R_rs2_0.read(ba) << 0;
826 etiss_uint8 rl = 0;
827 static BitArrayRange R_rl_0(25, 25);
828 rl += R_rl_0.read(ba) << 0;
829 etiss_uint8 aq = 0;
830 static BitArrayRange R_aq_0(26, 26);
831 aq += R_aq_0.read(ba) << 0;
832 
833 // -----------------------------------------------------------------------------
834 
835  {
836  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
837 
838  cp.code() = std::string("//AMOMAXD\n");
839 
840 // -----------------------------------------------------------------------------
841 cp.code() += "etiss_coverage_count(1, 232);\n";
842 { // block
843 cp.code() += "etiss_coverage_count(1, 1169);\n";
844 cp.code() += "{ // block\n";
845 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
846 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
847 cp.code() += "} // block\n";
848 } // block
849 { // block
850 cp.code() += "etiss_coverage_count(1, 8729);\n";
851 cp.code() += "{ // block\n";
852 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
853 cp.code() += "etiss_coverage_count(4, 8686, 8685, 8684, 8682);\n";
854 cp.code() += "etiss_uint64 mem_val_0;\n";
855 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
856 cp.code() += "if (cpu->exception) { // conditional\n";
857 { // procedure
858 cp.code() += "{ // procedure\n";
859 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
860 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
861 cp.code() += "} // procedure\n";
862 } // procedure
863 cp.code() += "} // conditional\n";
864 cp.code() += "etiss_int64 res = mem_val_0;\n";
865 cp.code() += "etiss_coverage_count(3, 8691, 8690, 8689);\n";
866 cp.code() += "etiss_coverage_count(1, 8692);\n";
867 if ((rd % 32ULL) != 0LL) { // conditional
868 cp.code() += "etiss_coverage_count(5, 8698, 8695, 8693, 8696, 8697);\n";
869 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
870 cp.code() += "etiss_coverage_count(5, 8705, 8703, 8702, 8700, 8704);\n";
871 } // conditional
872 cp.code() += "etiss_uint64 res2 = (res < (etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res);\n";
873 cp.code() += "etiss_coverage_count(12, 8723, 8722, 8715, 8707, 8714, 8712, 8711, 8709, 8720, 8719, 8717, 8721);\n";
874 cp.code() += "etiss_uint64 mem_val_1;\n";
875 cp.code() += "mem_val_1 = res2;\n";
876 cp.code() += "etiss_coverage_count(4, 8728, 8726, 8725, 8727);\n";
877 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
878 cp.code() += "if (cpu->exception) { // conditional\n";
879 { // procedure
880 cp.code() += "{ // procedure\n";
881 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
882 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
883 cp.code() += "} // procedure\n";
884 } // procedure
885 cp.code() += "} // conditional\n";
886 cp.code() += "} // block\n";
887 } // block
888 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
889 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
890 // -----------------------------------------------------------------------------
891  cp.getAffectedRegisters().add("instructionPointer", 32);
892  }
893  {
894  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
895 
896  cp.code() = std::string("//AMOMAXD\n");
897 
898 // -----------------------------------------------------------------------------
899 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
900 // -----------------------------------------------------------------------------
901  }
902 
903  return true;
904  },
905  0,
906  [] (BitArray & ba, Instruction & instr)
907  {
908 // -----------------------------------------------------------------------------
909 etiss_uint8 rd = 0;
910 static BitArrayRange R_rd_0(11, 7);
911 rd += R_rd_0.read(ba) << 0;
912 etiss_uint8 rs1 = 0;
913 static BitArrayRange R_rs1_0(19, 15);
914 rs1 += R_rs1_0.read(ba) << 0;
915 etiss_uint8 rs2 = 0;
916 static BitArrayRange R_rs2_0(24, 20);
917 rs2 += R_rs2_0.read(ba) << 0;
918 etiss_uint8 rl = 0;
919 static BitArrayRange R_rl_0(25, 25);
920 rl += R_rl_0.read(ba) << 0;
921 etiss_uint8 aq = 0;
922 static BitArrayRange R_aq_0(26, 26);
923 aq += R_aq_0.read(ba) << 0;
924 
925 // -----------------------------------------------------------------------------
926 
927  std::stringstream ss;
928 // -----------------------------------------------------------------------------
929 ss << "amomaxd" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
930 // -----------------------------------------------------------------------------
931  return ss.str();
932  }
933 );
934 
935 // AMOMINUD --------------------------------------------------------------------
936 static InstructionDefinition amominud_rd_rs1_rs2_rl_aq (
937  ISA32_RV64IMACFD,
938  "amominud",
939  (uint32_t) 0xc000302f,
940  (uint32_t) 0xf800707f,
941  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
942  {
943 
944 // -----------------------------------------------------------------------------
945 
946 // -----------------------------------------------------------------------------
947 
948 // -----------------------------------------------------------------------------
949 etiss_uint8 rd = 0;
950 static BitArrayRange R_rd_0(11, 7);
951 rd += R_rd_0.read(ba) << 0;
952 etiss_uint8 rs1 = 0;
953 static BitArrayRange R_rs1_0(19, 15);
954 rs1 += R_rs1_0.read(ba) << 0;
955 etiss_uint8 rs2 = 0;
956 static BitArrayRange R_rs2_0(24, 20);
957 rs2 += R_rs2_0.read(ba) << 0;
958 etiss_uint8 rl = 0;
959 static BitArrayRange R_rl_0(25, 25);
960 rl += R_rl_0.read(ba) << 0;
961 etiss_uint8 aq = 0;
962 static BitArrayRange R_aq_0(26, 26);
963 aq += R_aq_0.read(ba) << 0;
964 
965 // -----------------------------------------------------------------------------
966 
967  {
968  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
969 
970  cp.code() = std::string("//AMOMINUD\n");
971 
972 // -----------------------------------------------------------------------------
973 cp.code() += "etiss_coverage_count(1, 233);\n";
974 { // block
975 cp.code() += "etiss_coverage_count(1, 1169);\n";
976 cp.code() += "{ // block\n";
977 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
978 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
979 cp.code() += "} // block\n";
980 } // block
981 { // block
982 cp.code() += "etiss_coverage_count(1, 8779);\n";
983 cp.code() += "{ // block\n";
984 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
985 cp.code() += "etiss_coverage_count(4, 8736, 8735, 8734, 8732);\n";
986 cp.code() += "etiss_uint64 mem_val_0;\n";
987 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
988 cp.code() += "if (cpu->exception) { // conditional\n";
989 { // procedure
990 cp.code() += "{ // procedure\n";
991 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
992 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
993 cp.code() += "} // procedure\n";
994 } // procedure
995 cp.code() += "} // conditional\n";
996 cp.code() += "etiss_uint64 res = mem_val_0;\n";
997 cp.code() += "etiss_coverage_count(3, 8741, 8740, 8739);\n";
998 cp.code() += "etiss_coverage_count(1, 8742);\n";
999 if ((rd % 32ULL) != 0LL) { // conditional
1000 cp.code() += "etiss_coverage_count(5, 8748, 8745, 8743, 8746, 8747);\n";
1001 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res);\n";
1002 cp.code() += "etiss_coverage_count(6, 8757, 8753, 8752, 8750, 8756, 8754);\n";
1003 } // conditional
1004 cp.code() += "etiss_uint64 res2 = (res > *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res);\n";
1005 cp.code() += "etiss_coverage_count(11, 8773, 8772, 8765, 8759, 8764, 8763, 8761, 8770, 8769, 8767, 8771);\n";
1006 cp.code() += "etiss_uint64 mem_val_1;\n";
1007 cp.code() += "mem_val_1 = res2;\n";
1008 cp.code() += "etiss_coverage_count(4, 8778, 8776, 8775, 8777);\n";
1009 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
1010 cp.code() += "if (cpu->exception) { // conditional\n";
1011 { // procedure
1012 cp.code() += "{ // procedure\n";
1013 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1014 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1015 cp.code() += "} // procedure\n";
1016 } // procedure
1017 cp.code() += "} // conditional\n";
1018 cp.code() += "} // block\n";
1019 } // block
1020 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1021 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1022 // -----------------------------------------------------------------------------
1023  cp.getAffectedRegisters().add("instructionPointer", 32);
1024  }
1025  {
1026  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1027 
1028  cp.code() = std::string("//AMOMINUD\n");
1029 
1030 // -----------------------------------------------------------------------------
1031 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1032 // -----------------------------------------------------------------------------
1033  }
1034 
1035  return true;
1036  },
1037  0,
1038  [] (BitArray & ba, Instruction & instr)
1039  {
1040 // -----------------------------------------------------------------------------
1041 etiss_uint8 rd = 0;
1042 static BitArrayRange R_rd_0(11, 7);
1043 rd += R_rd_0.read(ba) << 0;
1044 etiss_uint8 rs1 = 0;
1045 static BitArrayRange R_rs1_0(19, 15);
1046 rs1 += R_rs1_0.read(ba) << 0;
1047 etiss_uint8 rs2 = 0;
1048 static BitArrayRange R_rs2_0(24, 20);
1049 rs2 += R_rs2_0.read(ba) << 0;
1050 etiss_uint8 rl = 0;
1051 static BitArrayRange R_rl_0(25, 25);
1052 rl += R_rl_0.read(ba) << 0;
1053 etiss_uint8 aq = 0;
1054 static BitArrayRange R_aq_0(26, 26);
1055 aq += R_aq_0.read(ba) << 0;
1056 
1057 // -----------------------------------------------------------------------------
1058 
1059  std::stringstream ss;
1060 // -----------------------------------------------------------------------------
1061 ss << "amominud" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
1062 // -----------------------------------------------------------------------------
1063  return ss.str();
1064  }
1065 );
1066 
1067 // AMOMAXUD --------------------------------------------------------------------
1068 static InstructionDefinition amomaxud_rd_rs1_rs2_rl_aq (
1069  ISA32_RV64IMACFD,
1070  "amomaxud",
1071  (uint32_t) 0xe000302f,
1072  (uint32_t) 0xf800707f,
1073  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1074  {
1075 
1076 // -----------------------------------------------------------------------------
1077 
1078 // -----------------------------------------------------------------------------
1079 
1080 // -----------------------------------------------------------------------------
1081 etiss_uint8 rd = 0;
1082 static BitArrayRange R_rd_0(11, 7);
1083 rd += R_rd_0.read(ba) << 0;
1084 etiss_uint8 rs1 = 0;
1085 static BitArrayRange R_rs1_0(19, 15);
1086 rs1 += R_rs1_0.read(ba) << 0;
1087 etiss_uint8 rs2 = 0;
1088 static BitArrayRange R_rs2_0(24, 20);
1089 rs2 += R_rs2_0.read(ba) << 0;
1090 etiss_uint8 rl = 0;
1091 static BitArrayRange R_rl_0(25, 25);
1092 rl += R_rl_0.read(ba) << 0;
1093 etiss_uint8 aq = 0;
1094 static BitArrayRange R_aq_0(26, 26);
1095 aq += R_aq_0.read(ba) << 0;
1096 
1097 // -----------------------------------------------------------------------------
1098 
1099  {
1100  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1101 
1102  cp.code() = std::string("//AMOMAXUD\n");
1103 
1104 // -----------------------------------------------------------------------------
1105 cp.code() += "etiss_coverage_count(1, 234);\n";
1106 { // block
1107 cp.code() += "etiss_coverage_count(1, 1169);\n";
1108 cp.code() += "{ // block\n";
1109 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1110 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1111 cp.code() += "} // block\n";
1112 } // block
1113 { // block
1114 cp.code() += "etiss_coverage_count(1, 8829);\n";
1115 cp.code() += "{ // block\n";
1116 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
1117 cp.code() += "etiss_coverage_count(4, 8786, 8785, 8784, 8782);\n";
1118 cp.code() += "etiss_uint64 mem_val_0;\n";
1119 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
1120 cp.code() += "if (cpu->exception) { // conditional\n";
1121 { // procedure
1122 cp.code() += "{ // procedure\n";
1123 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1124 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1125 cp.code() += "} // procedure\n";
1126 } // procedure
1127 cp.code() += "} // conditional\n";
1128 cp.code() += "etiss_uint64 res1 = mem_val_0;\n";
1129 cp.code() += "etiss_coverage_count(3, 8791, 8790, 8789);\n";
1130 cp.code() += "etiss_coverage_count(1, 8792);\n";
1131 if ((rd % 32ULL) != 0LL) { // conditional
1132 cp.code() += "etiss_coverage_count(5, 8798, 8795, 8793, 8796, 8797);\n";
1133 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res1);\n";
1134 cp.code() += "etiss_coverage_count(6, 8807, 8803, 8802, 8800, 8806, 8804);\n";
1135 } // conditional
1136 cp.code() += "etiss_uint64 res2 = (res1 < *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) : (res1);\n";
1137 cp.code() += "etiss_coverage_count(11, 8823, 8822, 8815, 8809, 8814, 8813, 8811, 8820, 8819, 8817, 8821);\n";
1138 cp.code() += "etiss_uint64 mem_val_1;\n";
1139 cp.code() += "mem_val_1 = res2;\n";
1140 cp.code() += "etiss_coverage_count(4, 8828, 8826, 8825, 8827);\n";
1141 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";
1142 cp.code() += "if (cpu->exception) { // conditional\n";
1143 { // procedure
1144 cp.code() += "{ // procedure\n";
1145 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1146 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1147 cp.code() += "} // procedure\n";
1148 } // procedure
1149 cp.code() += "} // conditional\n";
1150 cp.code() += "} // block\n";
1151 } // block
1152 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1153 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1154 // -----------------------------------------------------------------------------
1155  cp.getAffectedRegisters().add("instructionPointer", 32);
1156  }
1157  {
1158  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1159 
1160  cp.code() = std::string("//AMOMAXUD\n");
1161 
1162 // -----------------------------------------------------------------------------
1163 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1164 // -----------------------------------------------------------------------------
1165  }
1166 
1167  return true;
1168  },
1169  0,
1170  [] (BitArray & ba, Instruction & instr)
1171  {
1172 // -----------------------------------------------------------------------------
1173 etiss_uint8 rd = 0;
1174 static BitArrayRange R_rd_0(11, 7);
1175 rd += R_rd_0.read(ba) << 0;
1176 etiss_uint8 rs1 = 0;
1177 static BitArrayRange R_rs1_0(19, 15);
1178 rs1 += R_rs1_0.read(ba) << 0;
1179 etiss_uint8 rs2 = 0;
1180 static BitArrayRange R_rs2_0(24, 20);
1181 rs2 += R_rs2_0.read(ba) << 0;
1182 etiss_uint8 rl = 0;
1183 static BitArrayRange R_rl_0(25, 25);
1184 rl += R_rl_0.read(ba) << 0;
1185 etiss_uint8 aq = 0;
1186 static BitArrayRange R_aq_0(26, 26);
1187 aq += R_aq_0.read(ba) << 0;
1188 
1189 // -----------------------------------------------------------------------------
1190 
1191  std::stringstream ss;
1192 // -----------------------------------------------------------------------------
1193 ss << "amomaxud" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
1194 // -----------------------------------------------------------------------------
1195  return ss.str();
1196  }
1197 );
ISA32_RV64IMACFD
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
amoord_rd_rs1_rs2_rl_aq
static InstructionDefinition amoord_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoord",(uint32_t) 0x4000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOORD\n");cp.code()+="etiss_coverage_count(1, 230);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8629);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 8595, 8594, 8593, 8591);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 8600, 8599, 8598);\n";cp.code()+="etiss_coverage_count(1, 8601);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8607, 8604, 8602, 8605, 8606);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 8614, 8612, 8611, 8609, 8613);\n";} cp.code()+="etiss_uint64 res2 = res | *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(6, 8623, 8622, 8616, 8621, 8620, 8618);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(4, 8628, 8626, 8625, 8627);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOORD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoord"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
amomaxud_rd_rs1_rs2_rl_aq
static InstructionDefinition amomaxud_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amomaxud",(uint32_t) 0xe000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOMAXUD\n");cp.code()+="etiss_coverage_count(1, 234);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8829);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 8786, 8785, 8784, 8782);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint64 res1 = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 8791, 8790, 8789);\n";cp.code()+="etiss_coverage_count(1, 8792);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8798, 8795, 8793, 8796, 8797);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(res1);\n";cp.code()+="etiss_coverage_count(6, 8807, 8803, 8802, 8800, 8806, 8804);\n";} cp.code()+="etiss_uint64 res2 = (res1 < *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) ? (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) : (res1);\n";cp.code()+="etiss_coverage_count(11, 8823, 8822, 8815, 8809, 8814, 8813, 8811, 8820, 8819, 8817, 8821);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(4, 8828, 8826, 8825, 8827);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOMAXUD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amomaxud"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
amoswapd_rd_rs1_rs2_rl_aq
static InstructionDefinition amoswapd_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoswapd",(uint32_t) 0x800302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOSWAPD\n");cp.code()+="etiss_coverage_count(1, 226);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8465);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 8432, 8431, 8430, 8428);\n";cp.code()+="etiss_coverage_count(1, 8433);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8439, 8436, 8434, 8437, 8438);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(((etiss_int64)(mem_val_0)));\n";cp.code()+="etiss_coverage_count(9, 8453, 8444, 8443, 8441, 8452, 8449, 8447, 8446, 8450);\n";} cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(7, 8464, 8456, 8455, 8463, 8461, 8460, 8458);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOSWAPD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoswapd"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
amoxord_rd_rs1_rs2_rl_aq
static InstructionDefinition amoxord_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoxord",(uint32_t) 0x2000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOXORD\n");cp.code()+="etiss_coverage_count(1, 228);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8547);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 8513, 8512, 8511, 8509);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 8518, 8517, 8516);\n";cp.code()+="etiss_coverage_count(1, 8519);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8525, 8522, 8520, 8523, 8524);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 8532, 8530, 8529, 8527, 8531);\n";} cp.code()+="etiss_uint64 res2 = res ^ *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(6, 8541, 8540, 8534, 8539, 8538, 8536);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(4, 8546, 8544, 8543, 8545);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOXORD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoxord"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
amoandd_rd_rs1_rs2_rl_aq
static InstructionDefinition amoandd_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoandd",(uint32_t) 0x6000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOANDD\n");cp.code()+="etiss_coverage_count(1, 229);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8588);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 8554, 8553, 8552, 8550);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 8559, 8558, 8557);\n";cp.code()+="etiss_coverage_count(1, 8560);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8566, 8563, 8561, 8564, 8565);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 8573, 8571, 8570, 8568, 8572);\n";} cp.code()+="etiss_uint64 res2 = res & *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(6, 8582, 8581, 8575, 8580, 8579, 8577);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(4, 8587, 8585, 8584, 8586);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOANDD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoandd"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
amomaxd_rd_rs1_rs2_rl_aq
static InstructionDefinition amomaxd_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amomaxd",(uint32_t) 0xa000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOMAXD\n");cp.code()+="etiss_coverage_count(1, 232);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8729);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 8686, 8685, 8684, 8682);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 8691, 8690, 8689);\n";cp.code()+="etiss_coverage_count(1, 8692);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8698, 8695, 8693, 8696, 8697);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 8705, 8703, 8702, 8700, 8704);\n";} cp.code()+="etiss_uint64 res2 = (res < (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) ? (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) : (res);\n";cp.code()+="etiss_coverage_count(12, 8723, 8722, 8715, 8707, 8714, 8712, 8711, 8709, 8720, 8719, 8717, 8721);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(4, 8728, 8726, 8725, 8727);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOMAXD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amomaxd"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
amoaddd_rd_rs1_rs2_rl_aq
static InstructionDefinition amoaddd_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoaddd",(uint32_t) 0x00302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOADDD\n");cp.code()+="etiss_coverage_count(1, 227);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8506);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 8472, 8471, 8470, 8468);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 8477, 8476, 8475);\n";cp.code()+="etiss_coverage_count(1, 8478);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8484, 8481, 8479, 8482, 8483);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 8491, 8489, 8488, 8486, 8490);\n";} cp.code()+="etiss_uint64 res2 = res + *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(6, 8500, 8499, 8493, 8498, 8497, 8495);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(4, 8505, 8503, 8502, 8504);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOADDD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoaddd"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
amominud_rd_rs1_rs2_rl_aq
static InstructionDefinition amominud_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amominud",(uint32_t) 0xc000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOMINUD\n");cp.code()+="etiss_coverage_count(1, 233);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8779);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 8736, 8735, 8734, 8732);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint64 res = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 8741, 8740, 8739);\n";cp.code()+="etiss_coverage_count(1, 8742);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8748, 8745, 8743, 8746, 8747);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(res);\n";cp.code()+="etiss_coverage_count(6, 8757, 8753, 8752, 8750, 8756, 8754);\n";} cp.code()+="etiss_uint64 res2 = (res > *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) ? (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) : (res);\n";cp.code()+="etiss_coverage_count(11, 8773, 8772, 8765, 8759, 8764, 8763, 8761, 8770, 8769, 8767, 8771);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(4, 8778, 8776, 8775, 8777);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOMINUD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amominud"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
amomind_rd_rs1_rs2_rl_aq
static InstructionDefinition amomind_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amomind",(uint32_t) 0x8000302f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOMIND\n");cp.code()+="etiss_coverage_count(1, 231);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 8679);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 8636, 8635, 8634, 8632);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int64 res1 = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 8641, 8640, 8639);\n";cp.code()+="etiss_coverage_count(1, 8642);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 8648, 8645, 8643, 8646, 8647);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res1;\n";cp.code()+="etiss_coverage_count(5, 8655, 8653, 8652, 8650, 8654);\n";} cp.code()+="etiss_uint64 res2 = (res1 > (etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) ? (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) : (res1);\n";cp.code()+="etiss_coverage_count(12, 8673, 8672, 8665, 8657, 8664, 8662, 8661, 8659, 8670, 8669, 8667, 8671);\n";cp.code()+="etiss_uint64 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(4, 8678, 8676, 8675, 8677);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOMIND\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amomind"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
uint32_t
static __inline__ uint32_t
Definition: arm_cde.h:25
etiss_uint8
uint8_t etiss_uint8
Definition: types.h:87
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:386
etiss::CodePart::APPENDEDRETURNINGREQUIRED
@ APPENDEDRETURNINGREQUIRED
Definition: CodePart.h:402
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition: Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition: Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
Generated on Thu Oct 24 2024 09:40:11 for ETISS 0.8.0 by doxygen 1.9.1