32rd += R_rd_0.
read(ba) << 0;
35imm += R_imm_3.
read(ba) << 3;
37imm += R_imm_2.
read(ba) << 2;
39imm += R_imm_6.
read(ba) << 6;
41imm += R_imm_4.
read(ba) << 4;
49 cp.
code() = std::string(
"//CADDI4SPN\n");
52cp.
code() +=
"etiss_coverage_count(1, 42);\n";
54cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
55cp.
code() +=
"{ // block\n";
57cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
58cp.
code() +=
"} // block\n";
60cp.
code() +=
"etiss_coverage_count(1, 2327);\n";
62cp.
code() +=
"etiss_coverage_count(1, 2328);\n";
63cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) +
"ULL] = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(imm) +
"ULL;\n";
64cp.
code() +=
"etiss_coverage_count(9, 2339, 2333, 2332, 2330, 2331, 2338, 2336, 2335, 2337);\n";
68cp.
code() +=
"{ // procedure\n";
69cp.
code() +=
"RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";
70cp.
code() +=
"etiss_coverage_count(2, 2342, 2340);\n";
72cp.
code() +=
"} // procedure\n";
76cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
83 cp.
code() = std::string(
"//CADDI4SPN\n");
86cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
98rd += R_rd_0.read(ba) << 0;
101imm += R_imm_3.read(ba) << 3;
103imm += R_imm_2.read(ba) << 2;
105imm += R_imm_6.read(ba) << 6;
107imm += R_imm_4.read(ba) << 4;
111 std::stringstream ss;
113ss <<
"caddi4spn" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | imm=" + std::to_string(imm) +
"]");
136rd += R_rd_0.
read(ba) << 0;
139uimm += R_uimm_6.
read(ba) << 6;
141uimm += R_uimm_2.
read(ba) << 2;
144rs1 += R_rs1_0.
read(ba) << 0;
146uimm += R_uimm_3.
read(ba) << 3;
154 cp.
code() = std::string(
"//CLW\n");
157cp.
code() +=
"etiss_coverage_count(1, 43);\n";
159cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
160cp.
code() +=
"{ // block\n";
162cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
163cp.
code() +=
"} // block\n";
166cp.
code() +=
"etiss_coverage_count(1, 2363);\n";
167cp.
code() +=
"{ // block\n";
168cp.
code() +=
"etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) +
"ULL] + " + std::to_string(uimm) +
"ULL;\n";
169cp.
code() +=
"etiss_coverage_count(7, 2351, 2350, 2348, 2347, 2345, 2346, 2349);\n";
170cp.
code() +=
"etiss_uint32 mem_val_0;\n";
171cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
172cp.
code() +=
"if (cpu->exception) { // conditional\n";
174cp.
code() +=
"{ // procedure\n";
175cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
177cp.
code() +=
"} // procedure\n";
179cp.
code() +=
"} // conditional\n";
180cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) +
"ULL] = (etiss_int32)(mem_val_0);\n";
181cp.
code() +=
"etiss_coverage_count(8, 2362, 2356, 2355, 2353, 2354, 2361, 2359, 2358);\n";
182cp.
code() +=
"} // block\n";
185cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
192 cp.
code() = std::string(
"//CLW\n");
195cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
207rd += R_rd_0.read(ba) << 0;
210uimm += R_uimm_6.read(ba) << 6;
212uimm += R_uimm_2.read(ba) << 2;
215rs1 += R_rs1_0.read(ba) << 0;
217uimm += R_uimm_3.read(ba) << 3;
221 std::stringstream ss;
223ss <<
"clw" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | uimm=" + std::to_string(uimm) +
" | rs1=" + std::to_string(rs1) +
"]");
246rs2 += R_rs2_0.
read(ba) << 0;
249uimm += R_uimm_6.
read(ba) << 6;
251uimm += R_uimm_2.
read(ba) << 2;
254rs1 += R_rs1_0.
read(ba) << 0;
256uimm += R_uimm_3.
read(ba) << 3;
264 cp.
code() = std::string(
"//CSW\n");
267cp.
code() +=
"etiss_coverage_count(1, 44);\n";
269cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
270cp.
code() +=
"{ // block\n";
272cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
273cp.
code() +=
"} // block\n";
276cp.
code() +=
"etiss_coverage_count(1, 2384);\n";
277cp.
code() +=
"{ // block\n";
278cp.
code() +=
"etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) +
"ULL] + " + std::to_string(uimm) +
"ULL;\n";
279cp.
code() +=
"etiss_coverage_count(7, 2372, 2371, 2369, 2368, 2366, 2367, 2370);\n";
280cp.
code() +=
"etiss_uint32 mem_val_0;\n";
281cp.
code() +=
"mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) +
"ULL]);\n";
282cp.
code() +=
"etiss_coverage_count(8, 2383, 2375, 2374, 2382, 2380, 2379, 2377, 2378);\n";
283cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
284cp.
code() +=
"if (cpu->exception) { // conditional\n";
286cp.
code() +=
"{ // procedure\n";
287cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
289cp.
code() +=
"} // procedure\n";
291cp.
code() +=
"} // conditional\n";
292cp.
code() +=
"} // block\n";
295cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
302 cp.
code() = std::string(
"//CSW\n");
305cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
317rs2 += R_rs2_0.read(ba) << 0;
320uimm += R_uimm_6.read(ba) << 6;
322uimm += R_uimm_2.read(ba) << 2;
325rs1 += R_rs1_0.read(ba) << 0;
327uimm += R_uimm_3.read(ba) << 3;
331 std::stringstream ss;
333ss <<
"csw" <<
" # " << ba << (
" [rs2=" + std::to_string(rs2) +
" | uimm=" + std::to_string(uimm) +
" | rs1=" + std::to_string(rs1) +
"]");
356imm += R_imm_0.
read(ba) << 0;
359rs1 += R_rs1_0.
read(ba) << 0;
361imm += R_imm_5.
read(ba) << 5;
369 cp.
code() = std::string(
"//CADDI\n");
372cp.
code() +=
"etiss_coverage_count(1, 45);\n";
374cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
375cp.
code() +=
"{ // block\n";
377cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
378cp.
code() +=
"} // block\n";
380cp.
code() +=
"etiss_coverage_count(1, 2385);\n";
381if ((rs1 % 32ULL) != 0LL) {
382cp.
code() +=
"etiss_coverage_count(5, 2391, 2388, 2386, 2389, 2390);\n";
383cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL] + " + std::to_string(((
etiss_int8)(((
etiss_int8)imm) << (2)) >> (2))) +
"LL;\n";
384cp.
code() +=
"etiss_coverage_count(10, 2406, 2396, 2395, 2393, 2405, 2401, 2400, 2398, 2404, 2402);\n";
387cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
400imm += R_imm_0.read(ba) << 0;
403rs1 += R_rs1_0.read(ba) << 0;
405imm += R_imm_5.read(ba) << 5;
409 std::stringstream ss;
411ss <<
"caddi" <<
" # " << ba << (
" [imm=" + std::to_string(imm) +
" | rs1=" + std::to_string(rs1) +
"]");
434nzimm += R_nzimm_0.
read(ba) << 0;
436nzimm += R_nzimm_5.
read(ba) << 5;
444 cp.
code() = std::string(
"//CNOP\n");
447cp.
code() +=
"etiss_coverage_count(1, 46);\n";
449cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
450cp.
code() +=
"{ // block\n";
452cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
453cp.
code() +=
"} // block\n";
456cp.
code() +=
"etiss_coverage_count(1, 2407);\n";
457cp.
code() +=
"{ // block\n";
458cp.
code() +=
"} // block\n";
461cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
474nzimm += R_nzimm_0.read(ba) << 0;
476nzimm += R_nzimm_5.read(ba) << 5;
480 std::stringstream ss;
482ss <<
"cnop" <<
" # " << ba << (
" [nzimm=" + std::to_string(nzimm) +
"]");
505imm += R_imm_0.
read(ba) << 0;
508rd += R_rd_0.
read(ba) << 0;
510imm += R_imm_5.
read(ba) << 5;
518 cp.
code() = std::string(
"//CLI\n");
521cp.
code() +=
"etiss_coverage_count(1, 48);\n";
523cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
524cp.
code() +=
"{ // block\n";
526cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
527cp.
code() +=
"} // block\n";
530cp.
code() +=
"etiss_coverage_count(1, 2439);\n";
531cp.
code() +=
"{ // block\n";
532cp.
code() +=
"etiss_coverage_count(1, 2423);\n";
533if ((rd % 32ULL) != 0LL) {
534cp.
code() +=
"etiss_coverage_count(5, 2429, 2426, 2424, 2427, 2428);\n";
535cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = " + std::to_string(((
etiss_int8)(((
etiss_int8)imm) << (2)) >> (2))) +
"LL;\n";
536cp.
code() +=
"etiss_coverage_count(6, 2438, 2434, 2433, 2431, 2437, 2435);\n";
538cp.
code() +=
"} // block\n";
541cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
554imm += R_imm_0.read(ba) << 0;
557rd += R_rd_0.read(ba) << 0;
559imm += R_imm_5.read(ba) << 5;
563 std::stringstream ss;
565ss <<
"cli" <<
" # " << ba << (
" [imm=" + std::to_string(imm) +
" | rd=" + std::to_string(rd) +
"]");
588imm += R_imm_12.
read(ba) << 12;
591rd += R_rd_0.
read(ba) << 0;
593imm += R_imm_17.
read(ba) << 17;
601 cp.
code() = std::string(
"//CLUI\n");
604cp.
code() +=
"etiss_coverage_count(1, 49);\n";
606cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
607cp.
code() +=
"{ // block\n";
609cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
610cp.
code() +=
"} // block\n";
613cp.
code() +=
"etiss_coverage_count(1, 2463);\n";
614cp.
code() +=
"{ // block\n";
615cp.
code() +=
"etiss_coverage_count(1, 2440);\n";
617cp.
code() +=
"etiss_coverage_count(3, 2443, 2441, 2442);\n";
619cp.
code() +=
"{ // procedure\n";
620cp.
code() +=
"RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";
621cp.
code() +=
"etiss_coverage_count(2, 2446, 2444);\n";
623cp.
code() +=
"} // procedure\n";
626cp.
code() +=
"etiss_coverage_count(1, 2447);\n";
627if ((rd % 32ULL) != 0LL) {
628cp.
code() +=
"etiss_coverage_count(5, 2453, 2450, 2448, 2451, 2452);\n";
629cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = " + std::to_string(((
etiss_int32)(((
etiss_int32)imm) << (14)) >> (14))) +
"LL;\n";
630cp.
code() +=
"etiss_coverage_count(6, 2462, 2458, 2457, 2455, 2461, 2459);\n";
632cp.
code() +=
"} // block\n";
635cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
642 cp.
code() = std::string(
"//CLUI\n");
645cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
657imm += R_imm_12.read(ba) << 12;
660rd += R_rd_0.read(ba) << 0;
662imm += R_imm_17.read(ba) << 17;
666 std::stringstream ss;
668ss <<
"clui" <<
" # " << ba << (
" [imm=" + std::to_string(imm) +
" | rd=" + std::to_string(rd) +
"]");
691nzimm += R_nzimm_5.
read(ba) << 5;
693nzimm += R_nzimm_7.
read(ba) << 7;
695nzimm += R_nzimm_6.
read(ba) << 6;
697nzimm += R_nzimm_4.
read(ba) << 4;
699nzimm += R_nzimm_9.
read(ba) << 9;
707 cp.
code() = std::string(
"//CADDI16SP\n");
710cp.
code() +=
"etiss_coverage_count(1, 50);\n";
712cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
713cp.
code() +=
"{ // block\n";
715cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
716cp.
code() +=
"} // block\n";
718cp.
code() +=
"etiss_coverage_count(1, 2464);\n";
720cp.
code() +=
"etiss_coverage_count(1, 2465);\n";
721cp.
code() +=
"*((RV64IMACFD*)cpu)->X[2ULL] = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(((
etiss_int16)(((
etiss_int16)nzimm) << (6)) >> (6))) +
"LL;\n";
722cp.
code() +=
"etiss_coverage_count(8, 2476, 2468, 2467, 2475, 2471, 2470, 2474, 2472);\n";
726cp.
code() +=
"{ // procedure\n";
727cp.
code() +=
"RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";
728cp.
code() +=
"etiss_coverage_count(2, 2479, 2477);\n";
730cp.
code() +=
"} // procedure\n";
734cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
741 cp.
code() = std::string(
"//CADDI16SP\n");
744cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
756nzimm += R_nzimm_5.read(ba) << 5;
758nzimm += R_nzimm_7.read(ba) << 7;
760nzimm += R_nzimm_6.read(ba) << 6;
762nzimm += R_nzimm_4.read(ba) << 4;
764nzimm += R_nzimm_9.read(ba) << 9;
768 std::stringstream ss;
770ss <<
"caddi16sp" <<
" # " << ba << (
" [nzimm=" + std::to_string(nzimm) +
"]");
793rd += R_rd_0.
read(ba) << 0;
801 cp.
code() = std::string(
"//__reserved_clui\n");
804cp.
code() +=
"etiss_coverage_count(1, 51);\n";
806cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
807cp.
code() +=
"{ // block\n";
809cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
810cp.
code() +=
"} // block\n";
813cp.
code() +=
"{ // procedure\n";
814cp.
code() +=
"RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";
815cp.
code() +=
"etiss_coverage_count(2, 2482, 2480);\n";
817cp.
code() +=
"} // procedure\n";
820cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
827 cp.
code() = std::string(
"//__reserved_clui\n");
830cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
842rd += R_rd_0.read(ba) << 0;
846 std::stringstream ss;
848ss <<
"__reserved_clui" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
"]");
871shamt += R_shamt_0.
read(ba) << 0;
874rs1 += R_rs1_0.
read(ba) << 0;
882 cp.
code() = std::string(
"//CSRLI\n");
885cp.
code() +=
"etiss_coverage_count(1, 52);\n";
887cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
888cp.
code() +=
"{ // block\n";
890cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
891cp.
code() +=
"} // block\n";
894cp.
code() +=
"etiss_coverage_count(1, 2496);\n";
895cp.
code() +=
"{ // block\n";
896cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) +
"ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) +
"ULL] >> " + std::to_string(shamt) +
"ULL;\n";
897cp.
code() +=
"etiss_coverage_count(11, 2495, 2487, 2486, 2484, 2485, 2494, 2492, 2491, 2489, 2490, 2493);\n";
898cp.
code() +=
"} // block\n";
901cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
914shamt += R_shamt_0.read(ba) << 0;
917rs1 += R_rs1_0.read(ba) << 0;
921 std::stringstream ss;
923ss <<
"csrli" <<
" # " << ba << (
" [shamt=" + std::to_string(shamt) +
" | rs1=" + std::to_string(rs1) +
"]");
946shamt += R_shamt_0.
read(ba) << 0;
949rs1 += R_rs1_0.
read(ba) << 0;
957 cp.
code() = std::string(
"//CSRAI\n");
960cp.
code() +=
"etiss_coverage_count(1, 53);\n";
962cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
963cp.
code() +=
"{ // block\n";
965cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
966cp.
code() +=
"} // block\n";
969cp.
code() +=
"etiss_coverage_count(1, 2536);\n";
970cp.
code() +=
"{ // block\n";
971cp.
code() +=
"etiss_coverage_count(1, 2497);\n";
973cp.
code() +=
"etiss_coverage_count(1, 2498);\n";
975cp.
code() +=
"etiss_coverage_count(1, 2518);\n";
976cp.
code() +=
"{ // block\n";
977cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) +
"ULL] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) +
"ULL])) >> " + std::to_string(shamt) +
"ULL;\n";
978cp.
code() +=
"etiss_coverage_count(13, 2517, 2506, 2505, 2503, 2504, 2516, 2513, 2511, 2510, 2508, 2509, 2514, 2515);\n";
979cp.
code() +=
"} // block\n";
982cp.
code() +=
"} // block\n";
985cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
998shamt += R_shamt_0.read(ba) << 0;
1001rs1 += R_rs1_0.read(ba) << 0;
1005 std::stringstream ss;
1007ss <<
"csrai" <<
" # " << ba << (
" [shamt=" + std::to_string(shamt) +
" | rs1=" + std::to_string(rs1) +
"]");
1030imm += R_imm_0.
read(ba) << 0;
1033rs1 += R_rs1_0.
read(ba) << 0;
1035imm += R_imm_5.
read(ba) << 5;
1043 cp.
code() = std::string(
"//CANDI\n");
1046cp.
code() +=
"etiss_coverage_count(1, 54);\n";
1048cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
1049cp.
code() +=
"{ // block\n";
1051cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1052cp.
code() +=
"} // block\n";
1055cp.
code() +=
"etiss_coverage_count(1, 2552);\n";
1056cp.
code() +=
"{ // block\n";
1057cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) +
"ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) +
"ULL] & " + std::to_string(((
etiss_int8)(((
etiss_int8)imm) << (2)) >> (2))) +
"LL;\n";
1058cp.
code() +=
"etiss_coverage_count(12, 2551, 2541, 2540, 2538, 2539, 2550, 2546, 2545, 2543, 2544, 2549, 2547);\n";
1059cp.
code() +=
"} // block\n";
1062cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
1075imm += R_imm_0.read(ba) << 0;
1078rs1 += R_rs1_0.read(ba) << 0;
1080imm += R_imm_5.read(ba) << 5;
1084 std::stringstream ss;
1086ss <<
"candi" <<
" # " << ba << (
" [imm=" + std::to_string(imm) +
" | rs1=" + std::to_string(rs1) +
"]");
1109rs2 += R_rs2_0.
read(ba) << 0;
1112rd += R_rd_0.
read(ba) << 0;
1120 cp.
code() = std::string(
"//CSUB\n");
1123cp.
code() +=
"etiss_coverage_count(1, 55);\n";
1125cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
1126cp.
code() +=
"{ // block\n";
1128cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1129cp.
code() +=
"} // block\n";
1132cp.
code() +=
"etiss_coverage_count(1, 2570);\n";
1133cp.
code() +=
"{ // block\n";
1134cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) +
"ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) +
"ULL] - *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) +
"ULL];\n";
1135cp.
code() +=
"etiss_coverage_count(14, 2569, 2557, 2556, 2554, 2555, 2568, 2562, 2561, 2559, 2560, 2567, 2566, 2564, 2565);\n";
1136cp.
code() +=
"} // block\n";
1139cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
1152rs2 += R_rs2_0.read(ba) << 0;
1155rd += R_rd_0.read(ba) << 0;
1159 std::stringstream ss;
1161ss <<
"csub" <<
" # " << ba << (
" [rs2=" + std::to_string(rs2) +
" | rd=" + std::to_string(rd) +
"]");
1184rs2 += R_rs2_0.
read(ba) << 0;
1187rd += R_rd_0.
read(ba) << 0;
1195 cp.
code() = std::string(
"//CXOR\n");
1198cp.
code() +=
"etiss_coverage_count(1, 56);\n";
1200cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
1201cp.
code() +=
"{ // block\n";
1203cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1204cp.
code() +=
"} // block\n";
1207cp.
code() +=
"etiss_coverage_count(1, 2588);\n";
1208cp.
code() +=
"{ // block\n";
1209cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) +
"ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) +
"ULL] ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) +
"ULL];\n";
1210cp.
code() +=
"etiss_coverage_count(14, 2587, 2575, 2574, 2572, 2573, 2586, 2580, 2579, 2577, 2578, 2585, 2584, 2582, 2583);\n";
1211cp.
code() +=
"} // block\n";
1214cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
1227rs2 += R_rs2_0.read(ba) << 0;
1230rd += R_rd_0.read(ba) << 0;
1234 std::stringstream ss;
1236ss <<
"cxor" <<
" # " << ba << (
" [rs2=" + std::to_string(rs2) +
" | rd=" + std::to_string(rd) +
"]");
1259rs2 += R_rs2_0.
read(ba) << 0;
1262rd += R_rd_0.
read(ba) << 0;
1270 cp.
code() = std::string(
"//COR\n");
1273cp.
code() +=
"etiss_coverage_count(1, 57);\n";
1275cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
1276cp.
code() +=
"{ // block\n";
1278cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1279cp.
code() +=
"} // block\n";
1282cp.
code() +=
"etiss_coverage_count(1, 2606);\n";
1283cp.
code() +=
"{ // block\n";
1284cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) +
"ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) +
"ULL] | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) +
"ULL];\n";
1285cp.
code() +=
"etiss_coverage_count(14, 2605, 2593, 2592, 2590, 2591, 2604, 2598, 2597, 2595, 2596, 2603, 2602, 2600, 2601);\n";
1286cp.
code() +=
"} // block\n";
1289cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
1302rs2 += R_rs2_0.read(ba) << 0;
1305rd += R_rd_0.read(ba) << 0;
1309 std::stringstream ss;
1311ss <<
"cor" <<
" # " << ba << (
" [rs2=" + std::to_string(rs2) +
" | rd=" + std::to_string(rd) +
"]");
1334rs2 += R_rs2_0.
read(ba) << 0;
1337rd += R_rd_0.
read(ba) << 0;
1345 cp.
code() = std::string(
"//CAND\n");
1348cp.
code() +=
"etiss_coverage_count(1, 58);\n";
1350cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
1351cp.
code() +=
"{ // block\n";
1353cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1354cp.
code() +=
"} // block\n";
1357cp.
code() +=
"etiss_coverage_count(1, 2624);\n";
1358cp.
code() +=
"{ // block\n";
1359cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) +
"ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) +
"ULL] & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) +
"ULL];\n";
1360cp.
code() +=
"etiss_coverage_count(14, 2623, 2611, 2610, 2608, 2609, 2622, 2616, 2615, 2613, 2614, 2621, 2620, 2618, 2619);\n";
1361cp.
code() +=
"} // block\n";
1364cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
1377rs2 += R_rs2_0.read(ba) << 0;
1380rd += R_rd_0.read(ba) << 0;
1384 std::stringstream ss;
1386ss <<
"cand" <<
" # " << ba << (
" [rs2=" + std::to_string(rs2) +
" | rd=" + std::to_string(rd) +
"]");
1409imm += R_imm_5.
read(ba) << 5;
1411imm += R_imm_1.
read(ba) << 1;
1413imm += R_imm_7.
read(ba) << 7;
1415imm += R_imm_6.
read(ba) << 6;
1417imm += R_imm_10.
read(ba) << 10;
1419imm += R_imm_8.
read(ba) << 8;
1421imm += R_imm_4.
read(ba) << 4;
1423imm += R_imm_11.
read(ba) << 11;
1431 cp.
code() = std::string(
"//CJ\n");
1434cp.
code() +=
"etiss_coverage_count(1, 59);\n";
1436cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
1437cp.
code() +=
"{ // block\n";
1439cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1440cp.
code() +=
"} // block\n";
1443cp.
code() +=
"etiss_coverage_count(6, 2631, 2625, 2630, 2626, 2629, 2627);\n";
1445cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
1452 cp.
code() = std::string(
"//CJ\n");
1455cp.
code() +=
"return cpu->exception;\n";
1467imm += R_imm_5.read(ba) << 5;
1469imm += R_imm_1.read(ba) << 1;
1471imm += R_imm_7.read(ba) << 7;
1473imm += R_imm_6.read(ba) << 6;
1475imm += R_imm_10.read(ba) << 10;
1477imm += R_imm_8.read(ba) << 8;
1479imm += R_imm_4.read(ba) << 4;
1481imm += R_imm_11.read(ba) << 11;
1485 std::stringstream ss;
1487ss <<
"cj" <<
" # " << ba << (
" [imm=" + std::to_string(imm) +
"]");
1510imm += R_imm_5.
read(ba) << 5;
1512imm += R_imm_1.
read(ba) << 1;
1514imm += R_imm_6.
read(ba) << 6;
1517rs1 += R_rs1_0.
read(ba) << 0;
1519imm += R_imm_3.
read(ba) << 3;
1521imm += R_imm_8.
read(ba) << 8;
1529 cp.
code() = std::string(
"//CBEQZ\n");
1532cp.
code() +=
"etiss_coverage_count(1, 60);\n";
1534cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
1535cp.
code() +=
"{ // block\n";
1537cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1538cp.
code() +=
"} // block\n";
1540cp.
code() +=
"etiss_coverage_count(1, 2632);\n";
1541cp.
code() +=
"if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) +
"ULL] == 0LL) { // conditional\n";
1542cp.
code() +=
"etiss_coverage_count(6, 2639, 2637, 2636, 2634, 2635, 2638);\n";
1544cp.
code() +=
"etiss_coverage_count(6, 2646, 2640, 2645, 2641, 2644, 2642);\n";
1545cp.
code() +=
"} // conditional\n";
1547cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
1554 cp.
code() = std::string(
"//CBEQZ\n");
1557cp.
code() +=
"if (cpu->nextPc != " + std::to_string(ic.
current_address_ + 2) +
"ULL) return cpu->exception;\n";
1569imm += R_imm_5.read(ba) << 5;
1571imm += R_imm_1.read(ba) << 1;
1573imm += R_imm_6.read(ba) << 6;
1576rs1 += R_rs1_0.read(ba) << 0;
1578imm += R_imm_3.read(ba) << 3;
1580imm += R_imm_8.read(ba) << 8;
1584 std::stringstream ss;
1586ss <<
"cbeqz" <<
" # " << ba << (
" [imm=" + std::to_string(imm) +
" | rs1=" + std::to_string(rs1) +
"]");
1609imm += R_imm_5.
read(ba) << 5;
1611imm += R_imm_1.
read(ba) << 1;
1613imm += R_imm_6.
read(ba) << 6;
1616rs1 += R_rs1_0.
read(ba) << 0;
1618imm += R_imm_3.
read(ba) << 3;
1620imm += R_imm_8.
read(ba) << 8;
1628 cp.
code() = std::string(
"//CBNEZ\n");
1631cp.
code() +=
"etiss_coverage_count(1, 61);\n";
1633cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
1634cp.
code() +=
"{ // block\n";
1636cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1637cp.
code() +=
"} // block\n";
1639cp.
code() +=
"etiss_coverage_count(1, 2647);\n";
1640cp.
code() +=
"if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) +
"ULL] != 0LL) { // conditional\n";
1641cp.
code() +=
"etiss_coverage_count(6, 2654, 2652, 2651, 2649, 2650, 2653);\n";
1643cp.
code() +=
"etiss_coverage_count(6, 2661, 2655, 2660, 2656, 2659, 2657);\n";
1644cp.
code() +=
"} // conditional\n";
1646cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
1653 cp.
code() = std::string(
"//CBNEZ\n");
1656cp.
code() +=
"if (cpu->nextPc != " + std::to_string(ic.
current_address_ + 2) +
"ULL) return cpu->exception;\n";
1668imm += R_imm_5.read(ba) << 5;
1670imm += R_imm_1.read(ba) << 1;
1672imm += R_imm_6.read(ba) << 6;
1675rs1 += R_rs1_0.read(ba) << 0;
1677imm += R_imm_3.read(ba) << 3;
1679imm += R_imm_8.read(ba) << 8;
1683 std::stringstream ss;
1685ss <<
"cbnez" <<
" # " << ba << (
" [imm=" + std::to_string(imm) +
" | rs1=" + std::to_string(rs1) +
"]");
1708nzuimm += R_nzuimm_0.
read(ba) << 0;
1711rs1 += R_rs1_0.
read(ba) << 0;
1719 cp.
code() = std::string(
"//CSLLI\n");
1722cp.
code() +=
"etiss_coverage_count(1, 62);\n";
1724cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
1725cp.
code() +=
"{ // block\n";
1727cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1728cp.
code() +=
"} // block\n";
1730cp.
code() +=
"etiss_coverage_count(1, 2662);\n";
1732cp.
code() +=
"etiss_coverage_count(1, 2663);\n";
1733cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL] << " + std::to_string(nzuimm) +
"ULL;\n";
1734cp.
code() +=
"etiss_coverage_count(9, 2676, 2668, 2667, 2665, 2675, 2673, 2672, 2670, 2674);\n";
1737cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
1750nzuimm += R_nzuimm_0.read(ba) << 0;
1753rs1 += R_rs1_0.read(ba) << 0;
1757 std::stringstream ss;
1759ss <<
"cslli" <<
" # " << ba << (
" [nzuimm=" + std::to_string(nzuimm) +
" | rs1=" + std::to_string(rs1) +
"]");
1782uimm += R_uimm_6.
read(ba) << 6;
1784uimm += R_uimm_2.
read(ba) << 2;
1787rd += R_rd_0.
read(ba) << 0;
1789uimm += R_uimm_5.
read(ba) << 5;
1797 cp.
code() = std::string(
"//CLWSP\n");
1800cp.
code() +=
"etiss_coverage_count(1, 63);\n";
1802cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
1803cp.
code() +=
"{ // block\n";
1805cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1806cp.
code() +=
"} // block\n";
1809cp.
code() +=
"etiss_coverage_count(1, 2703);\n";
1810cp.
code() +=
"{ // block\n";
1811cp.
code() +=
"etiss_coverage_count(1, 2677);\n";
1813cp.
code() +=
"etiss_coverage_count(2, 2680, 2678);\n";
1815cp.
code() +=
"etiss_coverage_count(1, 2699);\n";
1816cp.
code() +=
"{ // block\n";
1817cp.
code() +=
"etiss_uint32 mem_val_0;\n";
1818cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) +
"ULL, (etiss_uint8*)&mem_val_0, 4);\n";
1819cp.
code() +=
"if (cpu->exception) { // conditional\n";
1821cp.
code() +=
"{ // procedure\n";
1822cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1824cp.
code() +=
"} // procedure\n";
1826cp.
code() +=
"} // conditional\n";
1827cp.
code() +=
"etiss_int32 res = mem_val_0;\n";
1828cp.
code() +=
"etiss_coverage_count(6, 2689, 2688, 2687, 2685, 2684, 2686);\n";
1829cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = (etiss_int64)(res);\n";
1830cp.
code() +=
"etiss_coverage_count(6, 2698, 2694, 2693, 2691, 2697, 2695);\n";
1831cp.
code() +=
"} // block\n";
1836cp.
code() +=
"{ // procedure\n";
1837cp.
code() +=
"RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2ULL);\n";
1838cp.
code() +=
"etiss_coverage_count(3, 2702, 2700, 2701);\n";
1840cp.
code() +=
"} // procedure\n";
1843cp.
code() +=
"} // block\n";
1846cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
1853 cp.
code() = std::string(
"//CLWSP\n");
1856cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1868uimm += R_uimm_6.read(ba) << 6;
1870uimm += R_uimm_2.read(ba) << 2;
1873rd += R_rd_0.read(ba) << 0;
1875uimm += R_uimm_5.read(ba) << 5;
1879 std::stringstream ss;
1881ss <<
"clwsp" <<
" # " << ba << (
" [uimm=" + std::to_string(uimm) +
" | rd=" + std::to_string(rd) +
"]");
1904rs2 += R_rs2_0.
read(ba) << 0;
1907rd += R_rd_0.
read(ba) << 0;
1915 cp.
code() = std::string(
"//CMV\n");
1918cp.
code() +=
"etiss_coverage_count(1, 64);\n";
1920cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
1921cp.
code() +=
"{ // block\n";
1923cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1924cp.
code() +=
"} // block\n";
1926cp.
code() +=
"etiss_coverage_count(1, 2704);\n";
1927if ((rd % 32ULL) != 0LL) {
1928cp.
code() +=
"etiss_coverage_count(5, 2710, 2707, 2705, 2708, 2709);\n";
1929cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL];\n";
1930cp.
code() +=
"etiss_coverage_count(7, 2721, 2715, 2714, 2712, 2720, 2719, 2717);\n";
1933cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
1946rs2 += R_rs2_0.read(ba) << 0;
1949rd += R_rd_0.read(ba) << 0;
1953 std::stringstream ss;
1955ss <<
"cmv" <<
" # " << ba << (
" [rs2=" + std::to_string(rs2) +
" | rd=" + std::to_string(rd) +
"]");
1978rs1 += R_rs1_0.
read(ba) << 0;
1986 cp.
code() = std::string(
"//CJR\n");
1989cp.
code() +=
"etiss_coverage_count(1, 65);\n";
1991cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
1992cp.
code() +=
"{ // block\n";
1994cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1995cp.
code() +=
"} // block\n";
1997cp.
code() +=
"etiss_coverage_count(1, 2722);\n";
1999cp.
code() +=
"etiss_coverage_count(1, 2723);\n";
2000cp.
code() +=
"cpu->nextPc = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL] & -2LL;\n";
2001cp.
code() +=
"etiss_coverage_count(6, 2733, 2724, 2732, 2729, 2728, 2726);\n";
2005cp.
code() +=
"{ // procedure\n";
2006cp.
code() +=
"RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2ULL);\n";
2007cp.
code() +=
"etiss_coverage_count(3, 2736, 2734, 2735);\n";
2009cp.
code() +=
"} // procedure\n";
2013cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
2020 cp.
code() = std::string(
"//CJR\n");
2023cp.
code() +=
"return cpu->exception;\n";
2035rs1 += R_rs1_0.read(ba) << 0;
2039 std::stringstream ss;
2041ss <<
"cjr" <<
" # " << ba << (
" [rs1=" + std::to_string(rs1) +
"]");
2069 cp.
code() = std::string(
"//__reserved_cmv\n");
2072cp.
code() +=
"etiss_coverage_count(1, 66);\n";
2074cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
2075cp.
code() +=
"{ // block\n";
2077cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2078cp.
code() +=
"} // block\n";
2081cp.
code() +=
"{ // procedure\n";
2082cp.
code() +=
"RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2ULL);\n";
2083cp.
code() +=
"etiss_coverage_count(3, 2739, 2737, 2738);\n";
2085cp.
code() +=
"} // procedure\n";
2088cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
2095 cp.
code() = std::string(
"//__reserved_cmv\n");
2098cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
2111 std::stringstream ss;
2113ss <<
"__reserved_cmv" <<
" # " << ba << (
" []");
2136rs2 += R_rs2_0.
read(ba) << 0;
2139rd += R_rd_0.
read(ba) << 0;
2147 cp.
code() = std::string(
"//CADD\n");
2150cp.
code() +=
"etiss_coverage_count(1, 67);\n";
2152cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
2153cp.
code() +=
"{ // block\n";
2155cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2156cp.
code() +=
"} // block\n";
2158cp.
code() +=
"etiss_coverage_count(1, 2740);\n";
2159if ((rd % 32ULL) != 0LL) {
2160cp.
code() +=
"etiss_coverage_count(5, 2746, 2743, 2741, 2744, 2745);\n";
2161cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL];\n";
2162cp.
code() +=
"etiss_coverage_count(11, 2763, 2751, 2750, 2748, 2762, 2756, 2755, 2753, 2761, 2760, 2758);\n";
2165cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
2178rs2 += R_rs2_0.read(ba) << 0;
2181rd += R_rd_0.read(ba) << 0;
2185 std::stringstream ss;
2187ss <<
"cadd" <<
" # " << ba << (
" [rs2=" + std::to_string(rs2) +
" | rd=" + std::to_string(rd) +
"]");
2210rs1 += R_rs1_0.
read(ba) << 0;
2218 cp.
code() = std::string(
"//CJALR\n");
2221cp.
code() +=
"etiss_coverage_count(1, 68);\n";
2223cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
2224cp.
code() +=
"{ // block\n";
2226cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2227cp.
code() +=
"} // block\n";
2230cp.
code() +=
"etiss_coverage_count(1, 2784);\n";
2231cp.
code() +=
"{ // block\n";
2232cp.
code() +=
"etiss_uint64 new_pc = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
2233cp.
code() +=
"etiss_coverage_count(4, 2770, 2769, 2768, 2766);\n";
2234cp.
code() +=
"*((RV64IMACFD*)cpu)->X[1ULL] = " + std::to_string(ic.
current_address_ + 2ULL) +
"ULL;\n";
2235cp.
code() +=
"etiss_coverage_count(6, 2777, 2773, 2772, 2776, 2774, 2775);\n";
2236cp.
code() +=
"cpu->nextPc = new_pc & -2LL;\n";
2237cp.
code() +=
"etiss_coverage_count(4, 2783, 2778, 2782, 2779);\n";
2238cp.
code() +=
"} // block\n";
2241cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
2248 cp.
code() = std::string(
"//CJALR\n");
2251cp.
code() +=
"return cpu->exception;\n";
2263rs1 += R_rs1_0.read(ba) << 0;
2267 std::stringstream ss;
2269ss <<
"cjalr" <<
" # " << ba << (
" [rs1=" + std::to_string(rs1) +
"]");
2297 cp.
code() = std::string(
"//CEBREAK\n");
2300cp.
code() +=
"etiss_coverage_count(1, 69);\n";
2302cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
2303cp.
code() +=
"{ // block\n";
2305cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2306cp.
code() +=
"} // block\n";
2309cp.
code() +=
"{ // procedure\n";
2310cp.
code() +=
"RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 3LL);\n";
2311cp.
code() +=
"etiss_coverage_count(2, 2787, 2785);\n";
2313cp.
code() +=
"} // procedure\n";
2316cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
2323 cp.
code() = std::string(
"//CEBREAK\n");
2326cp.
code() +=
"return cpu->exception;\n";
2339 std::stringstream ss;
2341ss <<
"cebreak" <<
" # " << ba << (
" []");
2364rs2 += R_rs2_0.
read(ba) << 0;
2367uimm += R_uimm_6.
read(ba) << 6;
2369uimm += R_uimm_2.
read(ba) << 2;
2377 cp.
code() = std::string(
"//CSWSP\n");
2380cp.
code() +=
"etiss_coverage_count(1, 70);\n";
2382cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
2383cp.
code() +=
"{ // block\n";
2385cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2386cp.
code() +=
"} // block\n";
2389cp.
code() +=
"etiss_coverage_count(1, 2806);\n";
2390cp.
code() +=
"{ // block\n";
2391cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) +
"ULL;\n";
2392cp.
code() +=
"etiss_coverage_count(5, 2794, 2793, 2791, 2790, 2792);\n";
2393cp.
code() +=
"etiss_uint32 mem_val_0;\n";
2394cp.
code() +=
"mem_val_0 = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL]);\n";
2395cp.
code() +=
"etiss_coverage_count(7, 2805, 2797, 2796, 2804, 2802, 2801, 2799);\n";
2396cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
2397cp.
code() +=
"if (cpu->exception) { // conditional\n";
2399cp.
code() +=
"{ // procedure\n";
2400cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
2402cp.
code() +=
"} // procedure\n";
2404cp.
code() +=
"} // conditional\n";
2405cp.
code() +=
"} // block\n";
2408cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
2415 cp.
code() = std::string(
"//CSWSP\n");
2418cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
2430rs2 += R_rs2_0.read(ba) << 0;
2433uimm += R_uimm_6.read(ba) << 6;
2435uimm += R_uimm_2.read(ba) << 2;
2439 std::stringstream ss;
2441ss <<
"cswsp" <<
" # " << ba << (
" [rs2=" + std::to_string(rs2) +
" | uimm=" + std::to_string(uimm) +
"]");
2469 cp.
code() = std::string(
"//DII\n");
2472cp.
code() +=
"etiss_coverage_count(1, 71);\n";
2474cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
2475cp.
code() +=
"{ // block\n";
2477cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2478cp.
code() +=
"} // block\n";
2481cp.
code() +=
"{ // procedure\n";
2482cp.
code() +=
"RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";
2483cp.
code() +=
"etiss_coverage_count(2, 2809, 2807);\n";
2485cp.
code() +=
"} // procedure\n";
2488cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
2495 cp.
code() = std::string(
"//DII\n");
2498cp.
code() +=
"return cpu->exception;\n";
2511 std::stringstream ss;
2513ss <<
"dii" <<
" # " << ba << (
" []");
etiss::instr::InstructionGroup ISA16_RV64IMACFD("ISA16_RV64IMACFD", 16)
static InstructionDefinition cnop_nzimm(ISA16_RV64IMACFD, "cnop",(uint16_t) 0x01,(uint16_t) 0xef83, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 nzimm=0;static BitArrayRange R_nzimm_0(6, 2);nzimm+=R_nzimm_0.read(ba)<< 0;static BitArrayRange R_nzimm_5(12, 12);nzimm+=R_nzimm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CNOP\n");cp.code()+="etiss_coverage_count(1, 46);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2407);\n";cp.code()+="{ // block\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 nzimm=0;static BitArrayRange R_nzimm_0(6, 2);nzimm+=R_nzimm_0.read(ba)<< 0;static BitArrayRange R_nzimm_5(12, 12);nzimm+=R_nzimm_5.read(ba)<< 5;std::stringstream ss;ss<< "cnop"<< " # "<< ba<<(" [nzimm="+std::to_string(nzimm)+"]");return ss.str();})
static InstructionDefinition cjr_rs1(ISA16_RV64IMACFD, "cjr",(uint16_t) 0x8002,(uint16_t) 0xf07f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CJR\n");cp.code()+="etiss_coverage_count(1, 65);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2722);\n";if(rs1) { cp.code()+="etiss_coverage_count(1, 2723);\n";cp.code()+="cpu->nextPc = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] & -2LL;\n";cp.code()+="etiss_coverage_count(6, 2733, 2724, 2732, 2729, 2728, 2726);\n";} else { { cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2ULL);\n";cp.code()+="etiss_coverage_count(3, 2736, 2734, 2735);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} } cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CJR\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "cjr"<< " # "<< ba<<(" [rs1="+std::to_string(rs1)+"]");return ss.str();})
static InstructionDefinition cj_imm(ISA16_RV64IMACFD, "cj",(uint16_t) 0xa001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_5(2, 2);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_1(5, 3);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_7(6, 6);imm+=R_imm_7.read(ba)<< 7;static BitArrayRange R_imm_6(7, 7);imm+=R_imm_6.read(ba)<< 6;static BitArrayRange R_imm_10(8, 8);imm+=R_imm_10.read(ba)<< 10;static BitArrayRange R_imm_8(10, 9);imm+=R_imm_8.read(ba)<< 8;static BitArrayRange R_imm_4(11, 11);imm+=R_imm_4.read(ba)<< 4;static BitArrayRange R_imm_11(12, 12);imm+=R_imm_11.read(ba)<< 11;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CJ\n");cp.code()+="etiss_coverage_count(1, 59);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))+"LL;\n";cp.code()+="etiss_coverage_count(6, 2631, 2625, 2630, 2626, 2629, 2627);\n";cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CJ\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_5(2, 2);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_1(5, 3);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_7(6, 6);imm+=R_imm_7.read(ba)<< 7;static BitArrayRange R_imm_6(7, 7);imm+=R_imm_6.read(ba)<< 6;static BitArrayRange R_imm_10(8, 8);imm+=R_imm_10.read(ba)<< 10;static BitArrayRange R_imm_8(10, 9);imm+=R_imm_8.read(ba)<< 8;static BitArrayRange R_imm_4(11, 11);imm+=R_imm_4.read(ba)<< 4;static BitArrayRange R_imm_11(12, 12);imm+=R_imm_11.read(ba)<< 11;std::stringstream ss;ss<< "cj"<< " # "<< ba<<(" [imm="+std::to_string(imm)+"]");return ss.str();})
static InstructionDefinition caddi16sp_nzimm(ISA16_RV64IMACFD, "caddi16sp",(uint16_t) 0x6101,(uint16_t) 0xef83, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 nzimm=0;static BitArrayRange R_nzimm_5(2, 2);nzimm+=R_nzimm_5.read(ba)<< 5;static BitArrayRange R_nzimm_7(4, 3);nzimm+=R_nzimm_7.read(ba)<< 7;static BitArrayRange R_nzimm_6(5, 5);nzimm+=R_nzimm_6.read(ba)<< 6;static BitArrayRange R_nzimm_4(6, 6);nzimm+=R_nzimm_4.read(ba)<< 4;static BitArrayRange R_nzimm_9(12, 12);nzimm+=R_nzimm_9.read(ba)<< 9;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CADDI16SP\n");cp.code()+="etiss_coverage_count(1, 50);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2464);\n";if(nzimm) { cp.code()+="etiss_coverage_count(1, 2465);\n";cp.code()+="*((RV64IMACFD*)cpu)->X[2ULL] = *((RV64IMACFD*)cpu)->X[2ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) nzimm)<<(6)) > >(6)))+"LL;\n";cp.code()+="etiss_coverage_count(8, 2476, 2468, 2467, 2475, 2471, 2470, 2474, 2472);\n";} else { { cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="etiss_coverage_count(2, 2479, 2477);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} } cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CADDI16SP\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 nzimm=0;static BitArrayRange R_nzimm_5(2, 2);nzimm+=R_nzimm_5.read(ba)<< 5;static BitArrayRange R_nzimm_7(4, 3);nzimm+=R_nzimm_7.read(ba)<< 7;static BitArrayRange R_nzimm_6(5, 5);nzimm+=R_nzimm_6.read(ba)<< 6;static BitArrayRange R_nzimm_4(6, 6);nzimm+=R_nzimm_4.read(ba)<< 4;static BitArrayRange R_nzimm_9(12, 12);nzimm+=R_nzimm_9.read(ba)<< 9;std::stringstream ss;ss<< "caddi16sp"<< " # "<< ba<<(" [nzimm="+std::to_string(nzimm)+"]");return ss.str();})
static InstructionDefinition clwsp_uimm_rd(ISA16_RV64IMACFD, "clwsp",(uint16_t) 0x4002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(3, 2);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 4);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_uimm_5(12, 12);uimm+=R_uimm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CLWSP\n");cp.code()+="etiss_coverage_count(1, 63);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2703);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2677);\n";if(rd % 32ULL) { cp.code()+="etiss_coverage_count(2, 2680, 2678);\n";{ cp.code()+="etiss_coverage_count(1, 2699);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, *((RV64IMACFD*)cpu)->X[2ULL] + "+std::to_string(uimm)+"ULL, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int32 res = mem_val_0;\n";cp.code()+="etiss_coverage_count(6, 2689, 2688, 2687, 2685, 2684, 2686);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(res);\n";cp.code()+="etiss_coverage_count(6, 2698, 2694, 2693, 2691, 2697, 2695);\n";cp.code()+="} // block\n";} } else { { cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2ULL);\n";cp.code()+="etiss_coverage_count(3, 2702, 2700, 2701);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CLWSP\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(3, 2);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 4);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_uimm_5(12, 12);uimm+=R_uimm_5.read(ba)<< 5;std::stringstream ss;ss<< "clwsp"<< " # "<< ba<<(" [uimm="+std::to_string(uimm)+" | rd="+std::to_string(rd)+"]");return ss.str();})
static InstructionDefinition caddi_imm_rs1(ISA16_RV64IMACFD, "caddi",(uint16_t) 0x01,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 imm=0;static BitArrayRange R_imm_0(6, 2);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_5(12, 12);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CADDI\n");cp.code()+="etiss_coverage_count(1, 45);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2385);\n";if((rs1 % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2391, 2388, 2386, 2389, 2390);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int8)(((etiss_int8) imm)<<(2)) > >(2)))+"LL;\n";cp.code()+="etiss_coverage_count(10, 2406, 2396, 2395, 2393, 2405, 2401, 2400, 2398, 2404, 2402);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 imm=0;static BitArrayRange R_imm_0(6, 2);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_5(12, 12);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "caddi"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
static InstructionDefinition cjalr_rs1(ISA16_RV64IMACFD, "cjalr",(uint16_t) 0x9002,(uint16_t) 0xf07f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CJALR\n");cp.code()+="etiss_coverage_count(1, 68);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2784);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 new_pc = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 2770, 2769, 2768, 2766);\n";cp.code()+="*((RV64IMACFD*)cpu)->X[1ULL] = "+std::to_string(ic.current_address_+2ULL)+"ULL;\n";cp.code()+="etiss_coverage_count(6, 2777, 2773, 2772, 2776, 2774, 2775);\n";cp.code()+="cpu->nextPc = new_pc & -2LL;\n";cp.code()+="etiss_coverage_count(4, 2783, 2778, 2782, 2779);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CJALR\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "cjalr"<< " # "<< ba<<(" [rs1="+std::to_string(rs1)+"]");return ss.str();})
static InstructionDefinition csrai_shamt_rs1(ISA16_RV64IMACFD, "csrai",(uint16_t) 0x8401,(uint16_t) 0xfc03, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(6, 2);shamt+=R_shamt_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRAI\n");cp.code()+="etiss_coverage_count(1, 53);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2536);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2497);\n";if(shamt) { cp.code()+="etiss_coverage_count(1, 2498);\n";{ cp.code()+="etiss_coverage_count(1, 2518);\n";cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL])) >> "+std::to_string(shamt)+"ULL;\n";cp.code()+="etiss_coverage_count(13, 2517, 2506, 2505, 2503, 2504, 2516, 2513, 2511, 2510, 2508, 2509, 2514, 2515);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(6, 2);shamt+=R_shamt_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "csrai"<< " # "<< ba<<(" [shamt="+std::to_string(shamt)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
static InstructionDefinition cand_rs2_rd(ISA16_RV64IMACFD, "cand",(uint16_t) 0x8c61,(uint16_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CAND\n");cp.code()+="etiss_coverage_count(1, 58);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2624);\n";cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] & *((RV64IMACFD*)cpu)->X["+std::to_string(rs2+8ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(14, 2623, 2611, 2610, 2608, 2609, 2622, 2616, 2615, 2613, 2614, 2621, 2620, 2618, 2619);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "cand"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | rd="+std::to_string(rd)+"]");return ss.str();})
static InstructionDefinition caddi4spn_rd_imm(ISA16_RV64IMACFD, "caddi4spn",(uint16_t) 0x00,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_3(5, 5);imm+=R_imm_3.read(ba)<< 3;static BitArrayRange R_imm_2(6, 6);imm+=R_imm_2.read(ba)<< 2;static BitArrayRange R_imm_6(10, 7);imm+=R_imm_6.read(ba)<< 6;static BitArrayRange R_imm_4(12, 11);imm+=R_imm_4.read(ba)<< 4;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CADDI4SPN\n");cp.code()+="etiss_coverage_count(1, 42);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2327);\n";if(imm) { cp.code()+="etiss_coverage_count(1, 2328);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = *((RV64IMACFD*)cpu)->X[2ULL] + "+std::to_string(imm)+"ULL;\n";cp.code()+="etiss_coverage_count(9, 2339, 2333, 2332, 2330, 2331, 2338, 2336, 2335, 2337);\n";} else { { cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="etiss_coverage_count(2, 2342, 2340);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} } cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CADDI4SPN\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_3(5, 5);imm+=R_imm_3.read(ba)<< 3;static BitArrayRange R_imm_2(6, 6);imm+=R_imm_2.read(ba)<< 2;static BitArrayRange R_imm_6(10, 7);imm+=R_imm_6.read(ba)<< 6;static BitArrayRange R_imm_4(12, 11);imm+=R_imm_4.read(ba)<< 4;std::stringstream ss;ss<< "caddi4spn"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | imm="+std::to_string(imm)+"]");return ss.str();})
static InstructionDefinition cbnez_imm_rs1(ISA16_RV64IMACFD, "cbnez",(uint16_t) 0xe001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_5(2, 2);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_1(4, 3);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_6(6, 5);imm+=R_imm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_3(11, 10);imm+=R_imm_3.read(ba)<< 3;static BitArrayRange R_imm_8(12, 12);imm+=R_imm_8.read(ba)<< 8;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CBNEZ\n");cp.code()+="etiss_coverage_count(1, 61);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2647);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(6, 2654, 2652, 2651, 2649, 2650, 2653);\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(7)) > >(7)))+"LL;\n";cp.code()+="etiss_coverage_count(6, 2661, 2655, 2660, 2656, 2659, 2657);\n";cp.code()+="} // conditional\n";cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CBNEZ\n");cp.code()+="if (cpu->nextPc != "+std::to_string(ic.current_address_+2)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_5(2, 2);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_1(4, 3);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_6(6, 5);imm+=R_imm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_3(11, 10);imm+=R_imm_3.read(ba)<< 3;static BitArrayRange R_imm_8(12, 12);imm+=R_imm_8.read(ba)<< 8;std::stringstream ss;ss<< "cbnez"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
static InstructionDefinition cebreak_(ISA16_RV64IMACFD, "cebreak",(uint16_t) 0x9002,(uint16_t) 0xffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CEBREAK\n");cp.code()+="etiss_coverage_count(1, 69);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 3LL);\n";cp.code()+="etiss_coverage_count(2, 2787, 2785);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CEBREAK\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "cebreak"<< " # "<< ba<<(" []");return ss.str();})
static InstructionDefinition csw_rs2_uimm_rs1(ISA16_RV64IMACFD, "csw",(uint16_t) 0xc000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(5, 5);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 6);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSW\n");cp.code()+="etiss_coverage_count(1, 44);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2384);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(7, 2372, 2371, 2369, 2368, 2366, 2367, 2370);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2+8ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(8, 2383, 2375, 2374, 2382, 2380, 2379, 2377, 2378);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CSW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(5, 5);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 6);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;std::stringstream ss;ss<< "csw"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | uimm="+std::to_string(uimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
static InstructionDefinition cxor_rs2_rd(ISA16_RV64IMACFD, "cxor",(uint16_t) 0x8c21,(uint16_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CXOR\n");cp.code()+="etiss_coverage_count(1, 56);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2588);\n";cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] ^ *((RV64IMACFD*)cpu)->X["+std::to_string(rs2+8ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(14, 2587, 2575, 2574, 2572, 2573, 2586, 2580, 2579, 2577, 2578, 2585, 2584, 2582, 2583);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "cxor"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | rd="+std::to_string(rd)+"]");return ss.str();})
static InstructionDefinition cor_rs2_rd(ISA16_RV64IMACFD, "cor",(uint16_t) 0x8c41,(uint16_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//COR\n");cp.code()+="etiss_coverage_count(1, 57);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2606);\n";cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] | *((RV64IMACFD*)cpu)->X["+std::to_string(rs2+8ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(14, 2605, 2593, 2592, 2590, 2591, 2604, 2598, 2597, 2595, 2596, 2603, 2602, 2600, 2601);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "cor"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | rd="+std::to_string(rd)+"]");return ss.str();})
static InstructionDefinition cslli_nzuimm_rs1(ISA16_RV64IMACFD, "cslli",(uint16_t) 0x02,(uint16_t) 0xf003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 nzuimm=0;static BitArrayRange R_nzuimm_0(6, 2);nzuimm+=R_nzuimm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSLLI\n");cp.code()+="etiss_coverage_count(1, 62);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2662);\n";if(nzuimm) { cp.code()+="etiss_coverage_count(1, 2663);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] << "+std::to_string(nzuimm)+"ULL;\n";cp.code()+="etiss_coverage_count(9, 2676, 2668, 2667, 2665, 2675, 2673, 2672, 2670, 2674);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 nzuimm=0;static BitArrayRange R_nzuimm_0(6, 2);nzuimm+=R_nzuimm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "cslli"<< " # "<< ba<<(" [nzuimm="+std::to_string(nzuimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
static InstructionDefinition dii_(ISA16_RV64IMACFD, "dii",(uint16_t) 0x00,(uint16_t) 0xffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//DII\n");cp.code()+="etiss_coverage_count(1, 71);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="etiss_coverage_count(2, 2809, 2807);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//DII\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "dii"<< " # "<< ba<<(" []");return ss.str();})
static InstructionDefinition cmv_rs2_rd(ISA16_RV64IMACFD, "cmv",(uint16_t) 0x8002,(uint16_t) 0xf003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CMV\n");cp.code()+="etiss_coverage_count(1, 64);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2704);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2710, 2707, 2705, 2708, 2709);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(7, 2721, 2715, 2714, 2712, 2720, 2719, 2717);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "cmv"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | rd="+std::to_string(rd)+"]");return ss.str();})
static InstructionDefinition csrli_shamt_rs1(ISA16_RV64IMACFD, "csrli",(uint16_t) 0x8001,(uint16_t) 0xfc03, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(6, 2);shamt+=R_shamt_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRLI\n");cp.code()+="etiss_coverage_count(1, 52);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2496);\n";cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] >> "+std::to_string(shamt)+"ULL;\n";cp.code()+="etiss_coverage_count(11, 2495, 2487, 2486, 2484, 2485, 2494, 2492, 2491, 2489, 2490, 2493);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(6, 2);shamt+=R_shamt_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "csrli"<< " # "<< ba<<(" [shamt="+std::to_string(shamt)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
static InstructionDefinition candi_imm_rs1(ISA16_RV64IMACFD, "candi",(uint16_t) 0x8801,(uint16_t) 0xec03, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 imm=0;static BitArrayRange R_imm_0(6, 2);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_5(12, 12);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CANDI\n");cp.code()+="etiss_coverage_count(1, 54);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2552);\n";cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] & "+std::to_string(((etiss_int8)(((etiss_int8) imm)<<(2)) > >(2)))+"LL;\n";cp.code()+="etiss_coverage_count(12, 2551, 2541, 2540, 2538, 2539, 2550, 2546, 2545, 2543, 2544, 2549, 2547);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 imm=0;static BitArrayRange R_imm_0(6, 2);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_5(12, 12);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "candi"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
static InstructionDefinition __reserved_cmv_(ISA16_RV64IMACFD, "__reserved_cmv",(uint16_t) 0x8002,(uint16_t) 0xffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//__reserved_cmv\n");cp.code()+="etiss_coverage_count(1, 66);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2ULL);\n";cp.code()+="etiss_coverage_count(3, 2739, 2737, 2738);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//__reserved_cmv\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "__reserved_cmv"<< " # "<< ba<<(" []");return ss.str();})
static InstructionDefinition cadd_rs2_rd(ISA16_RV64IMACFD, "cadd",(uint16_t) 0x9002,(uint16_t) 0xf003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CADD\n");cp.code()+="etiss_coverage_count(1, 67);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2740);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2746, 2743, 2741, 2744, 2745);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] + *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 2763, 2751, 2750, 2748, 2762, 2756, 2755, 2753, 2761, 2760, 2758);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "cadd"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | rd="+std::to_string(rd)+"]");return ss.str();})
static InstructionDefinition __reserved_clui_rd(ISA16_RV64IMACFD, "__reserved_clui",(uint16_t) 0x6001,(uint16_t) 0xf07f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//__reserved_clui\n");cp.code()+="etiss_coverage_count(1, 51);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="etiss_coverage_count(2, 2482, 2480);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//__reserved_clui\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "__reserved_clui"<< " # "<< ba<<(" [rd="+std::to_string(rd)+"]");return ss.str();})
static InstructionDefinition clw_rd_uimm_rs1(ISA16_RV64IMACFD, "clw",(uint16_t) 0x4000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(5, 5);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 6);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CLW\n");cp.code()+="etiss_coverage_count(1, 43);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2363);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(7, 2351, 2350, 2348, 2347, 2345, 2346, 2349);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = (etiss_int32)(mem_val_0);\n";cp.code()+="etiss_coverage_count(8, 2362, 2356, 2355, 2353, 2354, 2361, 2359, 2358);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CLW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(5, 5);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 6);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;std::stringstream ss;ss<< "clw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | uimm="+std::to_string(uimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
static InstructionDefinition cli_imm_rd(ISA16_RV64IMACFD, "cli",(uint16_t) 0x4001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 imm=0;static BitArrayRange R_imm_0(6, 2);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_imm_5(12, 12);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CLI\n");cp.code()+="etiss_coverage_count(1, 48);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2439);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2423);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2429, 2426, 2424, 2427, 2428);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string(((etiss_int8)(((etiss_int8) imm)<<(2)) > >(2)))+"LL;\n";cp.code()+="etiss_coverage_count(6, 2438, 2434, 2433, 2431, 2437, 2435);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 imm=0;static BitArrayRange R_imm_0(6, 2);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_imm_5(12, 12);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "cli"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rd="+std::to_string(rd)+"]");return ss.str();})
static InstructionDefinition clui_imm_rd(ISA16_RV64IMACFD, "clui",(uint16_t) 0x6001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint32 imm=0;static BitArrayRange R_imm_12(6, 2);imm+=R_imm_12.read(ba)<< 12;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_imm_17(12, 12);imm+=R_imm_17.read(ba)<< 17;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CLUI\n");cp.code()+="etiss_coverage_count(1, 49);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2463);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2440);\n";if(imm==0LL) { cp.code()+="etiss_coverage_count(3, 2443, 2441, 2442);\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="etiss_coverage_count(2, 2446, 2444);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} } cp.code()+="etiss_coverage_count(1, 2447);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2453, 2450, 2448, 2451, 2452);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string(((etiss_int32)(((etiss_int32) imm)<<(14)) > >(14)))+"LL;\n";cp.code()+="etiss_coverage_count(6, 2462, 2458, 2457, 2455, 2461, 2459);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CLUI\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint32 imm=0;static BitArrayRange R_imm_12(6, 2);imm+=R_imm_12.read(ba)<< 12;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_imm_17(12, 12);imm+=R_imm_17.read(ba)<< 17;std::stringstream ss;ss<< "clui"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rd="+std::to_string(rd)+"]");return ss.str();})
static InstructionDefinition cswsp_rs2_uimm(ISA16_RV64IMACFD, "cswsp",(uint16_t) 0xc002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(8, 7);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(12, 9);uimm+=R_uimm_2.read(ba)<< 2;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSWSP\n");cp.code()+="etiss_coverage_count(1, 70);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2806);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 2794, 2793, 2791, 2790, 2792);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(7, 2805, 2797, 2796, 2804, 2802, 2801, 2799);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CSWSP\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(8, 7);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(12, 9);uimm+=R_uimm_2.read(ba)<< 2;std::stringstream ss;ss<< "cswsp"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | uimm="+std::to_string(uimm)+"]");return ss.str();})
static InstructionDefinition cbeqz_imm_rs1(ISA16_RV64IMACFD, "cbeqz",(uint16_t) 0xc001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_5(2, 2);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_1(4, 3);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_6(6, 5);imm+=R_imm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_3(11, 10);imm+=R_imm_3.read(ba)<< 3;static BitArrayRange R_imm_8(12, 12);imm+=R_imm_8.read(ba)<< 8;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CBEQZ\n");cp.code()+="etiss_coverage_count(1, 60);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2632);\n";cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] == 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(6, 2639, 2637, 2636, 2634, 2635, 2638);\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(7)) > >(7)))+"LL;\n";cp.code()+="etiss_coverage_count(6, 2646, 2640, 2645, 2641, 2644, 2642);\n";cp.code()+="} // conditional\n";cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CBEQZ\n");cp.code()+="if (cpu->nextPc != "+std::to_string(ic.current_address_+2)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_5(2, 2);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_1(4, 3);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_6(6, 5);imm+=R_imm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_3(11, 10);imm+=R_imm_3.read(ba)<< 3;static BitArrayRange R_imm_8(12, 12);imm+=R_imm_8.read(ba)<< 8;std::stringstream ss;ss<< "cbeqz"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
static InstructionDefinition csub_rs2_rd(ISA16_RV64IMACFD, "csub",(uint16_t) 0x8c01,(uint16_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSUB\n");cp.code()+="etiss_coverage_count(1, 55);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2570);\n";cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] - *((RV64IMACFD*)cpu)->X["+std::to_string(rs2+8ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(14, 2569, 2557, 2556, 2554, 2555, 2568, 2562, 2561, 2559, 2560, 2567, 2566, 2564, 2565);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "csub"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | rd="+std::to_string(rd)+"]");return ss.str();})
Contains a small code snipped.
@ APPENDEDRETURNINGREQUIRED
RegisterSet & getAffectedRegisters()
void append(const CodePart &part, CodePart::TYPE type)
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Reading through it will only return bits within the range.
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
this class contains parameters that persist in between instruction lookpus/translation within a trans...
uint64_t current_address_
start address of current instruction
holds information and translation callbacks for an instruction.