ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV64IMACFD_RV32ICInstr.cpp
Go to the documentation of this file.
1 
8 #include "RV64IMACFDArch.h"
9 #include "RV64IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // CADDI4SPN -------------------------------------------------------------------
16 static InstructionDefinition caddi4spn_rd_imm (
17  ISA16_RV64IMACFD,
18  "caddi4spn",
19  (uint16_t) 0x00,
20  (uint16_t) 0xe003,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 etiss_uint8 rd = 0;
30 static BitArrayRange R_rd_0(4, 2);
31 rd += R_rd_0.read(ba) << 0;
32 etiss_uint16 imm = 0;
33 static BitArrayRange R_imm_3(5, 5);
34 imm += R_imm_3.read(ba) << 3;
35 static BitArrayRange R_imm_2(6, 6);
36 imm += R_imm_2.read(ba) << 2;
37 static BitArrayRange R_imm_6(10, 7);
38 imm += R_imm_6.read(ba) << 6;
39 static BitArrayRange R_imm_4(12, 11);
40 imm += R_imm_4.read(ba) << 4;
41 
42 // -----------------------------------------------------------------------------
43 
44  {
45  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
46 
47  cp.code() = std::string("//CADDI4SPN\n");
48 
49 // -----------------------------------------------------------------------------
50 { // block
51 cp.code() += "{ // block\n";
52 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
53 cp.code() += "} // block\n";
54 } // block
55 if (imm) { // conditional
56 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(imm) + "ULL;\n";
57 } // conditional
58 else { // conditional
59 { // procedure
60 cp.code() += "{ // procedure\n";
61 cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";
62 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
63 cp.code() += "} // procedure\n";
64 } // procedure
65 } // conditional
66 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
67 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
68 // -----------------------------------------------------------------------------
69  cp.getAffectedRegisters().add("instructionPointer", 32);
70  }
71  {
72  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
73 
74  cp.code() = std::string("//CADDI4SPN\n");
75 
76 // -----------------------------------------------------------------------------
77 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
78 // -----------------------------------------------------------------------------
79  }
80 
81  return true;
82  },
83  0,
84  [] (BitArray & ba, Instruction & instr)
85  {
86 // -----------------------------------------------------------------------------
87 etiss_uint8 rd = 0;
88 static BitArrayRange R_rd_0(4, 2);
89 rd += R_rd_0.read(ba) << 0;
90 etiss_uint16 imm = 0;
91 static BitArrayRange R_imm_3(5, 5);
92 imm += R_imm_3.read(ba) << 3;
93 static BitArrayRange R_imm_2(6, 6);
94 imm += R_imm_2.read(ba) << 2;
95 static BitArrayRange R_imm_6(10, 7);
96 imm += R_imm_6.read(ba) << 6;
97 static BitArrayRange R_imm_4(12, 11);
98 imm += R_imm_4.read(ba) << 4;
99 
100 // -----------------------------------------------------------------------------
101 
102  std::stringstream ss;
103 // -----------------------------------------------------------------------------
104 ss << "caddi4spn" << " # " << ba << (" [rd=" + std::to_string(rd) + " | imm=" + std::to_string(imm) + "]");
105 // -----------------------------------------------------------------------------
106  return ss.str();
107  }
108 );
109 
110 // CLW -------------------------------------------------------------------------
111 static InstructionDefinition clw_rd_uimm_rs1 (
112  ISA16_RV64IMACFD,
113  "clw",
114  (uint16_t) 0x4000,
115  (uint16_t) 0xe003,
116  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
117  {
118 
119 // -----------------------------------------------------------------------------
120 
121 // -----------------------------------------------------------------------------
122 
123 // -----------------------------------------------------------------------------
124 etiss_uint8 rd = 0;
125 static BitArrayRange R_rd_0(4, 2);
126 rd += R_rd_0.read(ba) << 0;
127 etiss_uint8 uimm = 0;
128 static BitArrayRange R_uimm_6(5, 5);
129 uimm += R_uimm_6.read(ba) << 6;
130 static BitArrayRange R_uimm_2(6, 6);
131 uimm += R_uimm_2.read(ba) << 2;
132 etiss_uint8 rs1 = 0;
133 static BitArrayRange R_rs1_0(9, 7);
134 rs1 += R_rs1_0.read(ba) << 0;
135 static BitArrayRange R_uimm_3(12, 10);
136 uimm += R_uimm_3.read(ba) << 3;
137 
138 // -----------------------------------------------------------------------------
139 
140  {
141  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
142 
143  cp.code() = std::string("//CLW\n");
144 
145 // -----------------------------------------------------------------------------
146 { // block
147 cp.code() += "{ // block\n";
148 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
149 cp.code() += "} // block\n";
150 } // block
151 { // block
152 cp.code() += "{ // block\n";
153 cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
154 cp.code() += "etiss_uint32 mem_val_0;\n";
155 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
156 cp.code() += "if (cpu->exception) { // conditional\n";
157 { // procedure
158 cp.code() += "{ // procedure\n";
159 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
160 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
161 cp.code() += "} // procedure\n";
162 } // procedure
163 cp.code() += "} // conditional\n";
164 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = (etiss_int32)(mem_val_0);\n";
165 cp.code() += "} // block\n";
166 } // block
167 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
168 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
169 // -----------------------------------------------------------------------------
170  cp.getAffectedRegisters().add("instructionPointer", 32);
171  }
172  {
173  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
174 
175  cp.code() = std::string("//CLW\n");
176 
177 // -----------------------------------------------------------------------------
178 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
179 // -----------------------------------------------------------------------------
180  }
181 
182  return true;
183  },
184  0,
185  [] (BitArray & ba, Instruction & instr)
186  {
187 // -----------------------------------------------------------------------------
188 etiss_uint8 rd = 0;
189 static BitArrayRange R_rd_0(4, 2);
190 rd += R_rd_0.read(ba) << 0;
191 etiss_uint8 uimm = 0;
192 static BitArrayRange R_uimm_6(5, 5);
193 uimm += R_uimm_6.read(ba) << 6;
194 static BitArrayRange R_uimm_2(6, 6);
195 uimm += R_uimm_2.read(ba) << 2;
196 etiss_uint8 rs1 = 0;
197 static BitArrayRange R_rs1_0(9, 7);
198 rs1 += R_rs1_0.read(ba) << 0;
199 static BitArrayRange R_uimm_3(12, 10);
200 uimm += R_uimm_3.read(ba) << 3;
201 
202 // -----------------------------------------------------------------------------
203 
204  std::stringstream ss;
205 // -----------------------------------------------------------------------------
206 ss << "clw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | uimm=" + std::to_string(uimm) + " | rs1=" + std::to_string(rs1) + "]");
207 // -----------------------------------------------------------------------------
208  return ss.str();
209  }
210 );
211 
212 // CSW -------------------------------------------------------------------------
213 static InstructionDefinition csw_rs2_uimm_rs1 (
214  ISA16_RV64IMACFD,
215  "csw",
216  (uint16_t) 0xc000,
217  (uint16_t) 0xe003,
218  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
219  {
220 
221 // -----------------------------------------------------------------------------
222 
223 // -----------------------------------------------------------------------------
224 
225 // -----------------------------------------------------------------------------
226 etiss_uint8 rs2 = 0;
227 static BitArrayRange R_rs2_0(4, 2);
228 rs2 += R_rs2_0.read(ba) << 0;
229 etiss_uint8 uimm = 0;
230 static BitArrayRange R_uimm_6(5, 5);
231 uimm += R_uimm_6.read(ba) << 6;
232 static BitArrayRange R_uimm_2(6, 6);
233 uimm += R_uimm_2.read(ba) << 2;
234 etiss_uint8 rs1 = 0;
235 static BitArrayRange R_rs1_0(9, 7);
236 rs1 += R_rs1_0.read(ba) << 0;
237 static BitArrayRange R_uimm_3(12, 10);
238 uimm += R_uimm_3.read(ba) << 3;
239 
240 // -----------------------------------------------------------------------------
241 
242  {
243  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
244 
245  cp.code() = std::string("//CSW\n");
246 
247 // -----------------------------------------------------------------------------
248 { // block
249 cp.code() += "{ // block\n";
250 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
251 cp.code() += "} // block\n";
252 } // block
253 { // block
254 cp.code() += "{ // block\n";
255 cp.code() += "etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
256 cp.code() += "etiss_uint32 mem_val_0;\n";
257 cp.code() += "mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL]);\n";
258 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
259 cp.code() += "if (cpu->exception) { // conditional\n";
260 { // procedure
261 cp.code() += "{ // procedure\n";
262 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
263 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
264 cp.code() += "} // procedure\n";
265 } // procedure
266 cp.code() += "} // conditional\n";
267 cp.code() += "} // block\n";
268 } // block
269 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
270 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
271 // -----------------------------------------------------------------------------
272  cp.getAffectedRegisters().add("instructionPointer", 32);
273  }
274  {
275  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
276 
277  cp.code() = std::string("//CSW\n");
278 
279 // -----------------------------------------------------------------------------
280 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
281 // -----------------------------------------------------------------------------
282  }
283 
284  return true;
285  },
286  0,
287  [] (BitArray & ba, Instruction & instr)
288  {
289 // -----------------------------------------------------------------------------
290 etiss_uint8 rs2 = 0;
291 static BitArrayRange R_rs2_0(4, 2);
292 rs2 += R_rs2_0.read(ba) << 0;
293 etiss_uint8 uimm = 0;
294 static BitArrayRange R_uimm_6(5, 5);
295 uimm += R_uimm_6.read(ba) << 6;
296 static BitArrayRange R_uimm_2(6, 6);
297 uimm += R_uimm_2.read(ba) << 2;
298 etiss_uint8 rs1 = 0;
299 static BitArrayRange R_rs1_0(9, 7);
300 rs1 += R_rs1_0.read(ba) << 0;
301 static BitArrayRange R_uimm_3(12, 10);
302 uimm += R_uimm_3.read(ba) << 3;
303 
304 // -----------------------------------------------------------------------------
305 
306  std::stringstream ss;
307 // -----------------------------------------------------------------------------
308 ss << "csw" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | uimm=" + std::to_string(uimm) + " | rs1=" + std::to_string(rs1) + "]");
309 // -----------------------------------------------------------------------------
310  return ss.str();
311  }
312 );
313 
314 // CADDI -----------------------------------------------------------------------
315 static InstructionDefinition caddi_imm_rs1 (
316  ISA16_RV64IMACFD,
317  "caddi",
318  (uint16_t) 0x01,
319  (uint16_t) 0xe003,
320  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
321  {
322 
323 // -----------------------------------------------------------------------------
324 
325 // -----------------------------------------------------------------------------
326 
327 // -----------------------------------------------------------------------------
328 etiss_uint8 imm = 0;
329 static BitArrayRange R_imm_0(6, 2);
330 imm += R_imm_0.read(ba) << 0;
331 etiss_uint8 rs1 = 0;
332 static BitArrayRange R_rs1_0(11, 7);
333 rs1 += R_rs1_0.read(ba) << 0;
334 static BitArrayRange R_imm_5(12, 12);
335 imm += R_imm_5.read(ba) << 5;
336 
337 // -----------------------------------------------------------------------------
338 
339  {
340  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
341 
342  cp.code() = std::string("//CADDI\n");
343 
344 // -----------------------------------------------------------------------------
345 { // block
346 cp.code() += "{ // block\n";
347 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
348 cp.code() += "} // block\n";
349 } // block
350 if ((rs1 % 32ULL) != 0LL) { // conditional
351 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int8)(((etiss_int8)imm) << (2)) >> (2))) + "LL;\n";
352 } // conditional
353 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
354 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
355 // -----------------------------------------------------------------------------
356  cp.getAffectedRegisters().add("instructionPointer", 32);
357  }
358 
359  return true;
360  },
361  0,
362  [] (BitArray & ba, Instruction & instr)
363  {
364 // -----------------------------------------------------------------------------
365 etiss_uint8 imm = 0;
366 static BitArrayRange R_imm_0(6, 2);
367 imm += R_imm_0.read(ba) << 0;
368 etiss_uint8 rs1 = 0;
369 static BitArrayRange R_rs1_0(11, 7);
370 rs1 += R_rs1_0.read(ba) << 0;
371 static BitArrayRange R_imm_5(12, 12);
372 imm += R_imm_5.read(ba) << 5;
373 
374 // -----------------------------------------------------------------------------
375 
376  std::stringstream ss;
377 // -----------------------------------------------------------------------------
378 ss << "caddi" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + "]");
379 // -----------------------------------------------------------------------------
380  return ss.str();
381  }
382 );
383 
384 // CNOP ------------------------------------------------------------------------
385 static InstructionDefinition cnop_nzimm (
386  ISA16_RV64IMACFD,
387  "cnop",
388  (uint16_t) 0x01,
389  (uint16_t) 0xef83,
390  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
391  {
392 
393 // -----------------------------------------------------------------------------
394 
395 // -----------------------------------------------------------------------------
396 
397 // -----------------------------------------------------------------------------
398 etiss_uint8 nzimm = 0;
399 static BitArrayRange R_nzimm_0(6, 2);
400 nzimm += R_nzimm_0.read(ba) << 0;
401 static BitArrayRange R_nzimm_5(12, 12);
402 nzimm += R_nzimm_5.read(ba) << 5;
403 
404 // -----------------------------------------------------------------------------
405 
406  {
407  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
408 
409  cp.code() = std::string("//CNOP\n");
410 
411 // -----------------------------------------------------------------------------
412 { // block
413 cp.code() += "{ // block\n";
414 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
415 cp.code() += "} // block\n";
416 } // block
417 { // block
418 cp.code() += "{ // block\n";
419 cp.code() += "} // block\n";
420 } // block
421 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
422 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
423 // -----------------------------------------------------------------------------
424  cp.getAffectedRegisters().add("instructionPointer", 32);
425  }
426 
427  return true;
428  },
429  0,
430  [] (BitArray & ba, Instruction & instr)
431  {
432 // -----------------------------------------------------------------------------
433 etiss_uint8 nzimm = 0;
434 static BitArrayRange R_nzimm_0(6, 2);
435 nzimm += R_nzimm_0.read(ba) << 0;
436 static BitArrayRange R_nzimm_5(12, 12);
437 nzimm += R_nzimm_5.read(ba) << 5;
438 
439 // -----------------------------------------------------------------------------
440 
441  std::stringstream ss;
442 // -----------------------------------------------------------------------------
443 ss << "cnop" << " # " << ba << (" [nzimm=" + std::to_string(nzimm) + "]");
444 // -----------------------------------------------------------------------------
445  return ss.str();
446  }
447 );
448 
449 // CLI -------------------------------------------------------------------------
450 static InstructionDefinition cli_imm_rd (
451  ISA16_RV64IMACFD,
452  "cli",
453  (uint16_t) 0x4001,
454  (uint16_t) 0xe003,
455  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
456  {
457 
458 // -----------------------------------------------------------------------------
459 
460 // -----------------------------------------------------------------------------
461 
462 // -----------------------------------------------------------------------------
463 etiss_uint8 imm = 0;
464 static BitArrayRange R_imm_0(6, 2);
465 imm += R_imm_0.read(ba) << 0;
466 etiss_uint8 rd = 0;
467 static BitArrayRange R_rd_0(11, 7);
468 rd += R_rd_0.read(ba) << 0;
469 static BitArrayRange R_imm_5(12, 12);
470 imm += R_imm_5.read(ba) << 5;
471 
472 // -----------------------------------------------------------------------------
473 
474  {
475  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
476 
477  cp.code() = std::string("//CLI\n");
478 
479 // -----------------------------------------------------------------------------
480 { // block
481 cp.code() += "{ // block\n";
482 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
483 cp.code() += "} // block\n";
484 } // block
485 { // block
486 cp.code() += "{ // block\n";
487 if ((rd % 32ULL) != 0LL) { // conditional
488 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(((etiss_int8)(((etiss_int8)imm) << (2)) >> (2))) + "LL;\n";
489 } // conditional
490 cp.code() += "} // block\n";
491 } // block
492 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
493 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
494 // -----------------------------------------------------------------------------
495  cp.getAffectedRegisters().add("instructionPointer", 32);
496  }
497 
498  return true;
499  },
500  0,
501  [] (BitArray & ba, Instruction & instr)
502  {
503 // -----------------------------------------------------------------------------
504 etiss_uint8 imm = 0;
505 static BitArrayRange R_imm_0(6, 2);
506 imm += R_imm_0.read(ba) << 0;
507 etiss_uint8 rd = 0;
508 static BitArrayRange R_rd_0(11, 7);
509 rd += R_rd_0.read(ba) << 0;
510 static BitArrayRange R_imm_5(12, 12);
511 imm += R_imm_5.read(ba) << 5;
512 
513 // -----------------------------------------------------------------------------
514 
515  std::stringstream ss;
516 // -----------------------------------------------------------------------------
517 ss << "cli" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rd=" + std::to_string(rd) + "]");
518 // -----------------------------------------------------------------------------
519  return ss.str();
520  }
521 );
522 
523 // CLUI ------------------------------------------------------------------------
524 static InstructionDefinition clui_imm_rd (
525  ISA16_RV64IMACFD,
526  "clui",
527  (uint16_t) 0x6001,
528  (uint16_t) 0xe003,
529  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
530  {
531 
532 // -----------------------------------------------------------------------------
533 
534 // -----------------------------------------------------------------------------
535 
536 // -----------------------------------------------------------------------------
537 etiss_uint32 imm = 0;
538 static BitArrayRange R_imm_12(6, 2);
539 imm += R_imm_12.read(ba) << 12;
540 etiss_uint8 rd = 0;
541 static BitArrayRange R_rd_0(11, 7);
542 rd += R_rd_0.read(ba) << 0;
543 static BitArrayRange R_imm_17(12, 12);
544 imm += R_imm_17.read(ba) << 17;
545 
546 // -----------------------------------------------------------------------------
547 
548  {
549  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
550 
551  cp.code() = std::string("//CLUI\n");
552 
553 // -----------------------------------------------------------------------------
554 { // block
555 cp.code() += "{ // block\n";
556 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
557 cp.code() += "} // block\n";
558 } // block
559 { // block
560 cp.code() += "{ // block\n";
561 if (imm == 0LL) { // conditional
562 { // procedure
563 cp.code() += "{ // procedure\n";
564 cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";
565 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
566 cp.code() += "} // procedure\n";
567 } // procedure
568 } // conditional
569 if ((rd % 32ULL) != 0LL) { // conditional
570 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(((etiss_int32)(((etiss_int32)imm) << (14)) >> (14))) + "LL;\n";
571 } // conditional
572 cp.code() += "} // block\n";
573 } // block
574 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
575 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
576 // -----------------------------------------------------------------------------
577  cp.getAffectedRegisters().add("instructionPointer", 32);
578  }
579  {
580  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
581 
582  cp.code() = std::string("//CLUI\n");
583 
584 // -----------------------------------------------------------------------------
585 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
586 // -----------------------------------------------------------------------------
587  }
588 
589  return true;
590  },
591  0,
592  [] (BitArray & ba, Instruction & instr)
593  {
594 // -----------------------------------------------------------------------------
595 etiss_uint32 imm = 0;
596 static BitArrayRange R_imm_12(6, 2);
597 imm += R_imm_12.read(ba) << 12;
598 etiss_uint8 rd = 0;
599 static BitArrayRange R_rd_0(11, 7);
600 rd += R_rd_0.read(ba) << 0;
601 static BitArrayRange R_imm_17(12, 12);
602 imm += R_imm_17.read(ba) << 17;
603 
604 // -----------------------------------------------------------------------------
605 
606  std::stringstream ss;
607 // -----------------------------------------------------------------------------
608 ss << "clui" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rd=" + std::to_string(rd) + "]");
609 // -----------------------------------------------------------------------------
610  return ss.str();
611  }
612 );
613 
614 // CADDI16SP -------------------------------------------------------------------
615 static InstructionDefinition caddi16sp_nzimm (
616  ISA16_RV64IMACFD,
617  "caddi16sp",
618  (uint16_t) 0x6101,
619  (uint16_t) 0xef83,
620  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
621  {
622 
623 // -----------------------------------------------------------------------------
624 
625 // -----------------------------------------------------------------------------
626 
627 // -----------------------------------------------------------------------------
628 etiss_uint16 nzimm = 0;
629 static BitArrayRange R_nzimm_5(2, 2);
630 nzimm += R_nzimm_5.read(ba) << 5;
631 static BitArrayRange R_nzimm_7(4, 3);
632 nzimm += R_nzimm_7.read(ba) << 7;
633 static BitArrayRange R_nzimm_6(5, 5);
634 nzimm += R_nzimm_6.read(ba) << 6;
635 static BitArrayRange R_nzimm_4(6, 6);
636 nzimm += R_nzimm_4.read(ba) << 4;
637 static BitArrayRange R_nzimm_9(12, 12);
638 nzimm += R_nzimm_9.read(ba) << 9;
639 
640 // -----------------------------------------------------------------------------
641 
642  {
643  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
644 
645  cp.code() = std::string("//CADDI16SP\n");
646 
647 // -----------------------------------------------------------------------------
648 { // block
649 cp.code() += "{ // block\n";
650 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
651 cp.code() += "} // block\n";
652 } // block
653 if (nzimm) { // conditional
654 cp.code() += "*((RV64IMACFD*)cpu)->X[2ULL] = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)nzimm) << (6)) >> (6))) + "LL;\n";
655 } // conditional
656 else { // conditional
657 { // procedure
658 cp.code() += "{ // procedure\n";
659 cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";
660 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
661 cp.code() += "} // procedure\n";
662 } // procedure
663 } // conditional
664 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
665 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
666 // -----------------------------------------------------------------------------
667  cp.getAffectedRegisters().add("instructionPointer", 32);
668  }
669  {
670  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
671 
672  cp.code() = std::string("//CADDI16SP\n");
673 
674 // -----------------------------------------------------------------------------
675 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
676 // -----------------------------------------------------------------------------
677  }
678 
679  return true;
680  },
681  0,
682  [] (BitArray & ba, Instruction & instr)
683  {
684 // -----------------------------------------------------------------------------
685 etiss_uint16 nzimm = 0;
686 static BitArrayRange R_nzimm_5(2, 2);
687 nzimm += R_nzimm_5.read(ba) << 5;
688 static BitArrayRange R_nzimm_7(4, 3);
689 nzimm += R_nzimm_7.read(ba) << 7;
690 static BitArrayRange R_nzimm_6(5, 5);
691 nzimm += R_nzimm_6.read(ba) << 6;
692 static BitArrayRange R_nzimm_4(6, 6);
693 nzimm += R_nzimm_4.read(ba) << 4;
694 static BitArrayRange R_nzimm_9(12, 12);
695 nzimm += R_nzimm_9.read(ba) << 9;
696 
697 // -----------------------------------------------------------------------------
698 
699  std::stringstream ss;
700 // -----------------------------------------------------------------------------
701 ss << "caddi16sp" << " # " << ba << (" [nzimm=" + std::to_string(nzimm) + "]");
702 // -----------------------------------------------------------------------------
703  return ss.str();
704  }
705 );
706 
707 // __reserved_clui -------------------------------------------------------------
708 static InstructionDefinition __reserved_clui_rd (
709  ISA16_RV64IMACFD,
710  "__reserved_clui",
711  (uint16_t) 0x6001,
712  (uint16_t) 0xf07f,
713  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
714  {
715 
716 // -----------------------------------------------------------------------------
717 
718 // -----------------------------------------------------------------------------
719 
720 // -----------------------------------------------------------------------------
721 etiss_uint8 rd = 0;
722 static BitArrayRange R_rd_0(11, 7);
723 rd += R_rd_0.read(ba) << 0;
724 
725 // -----------------------------------------------------------------------------
726 
727  {
728  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
729 
730  cp.code() = std::string("//__reserved_clui\n");
731 
732 // -----------------------------------------------------------------------------
733 { // block
734 cp.code() += "{ // block\n";
735 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
736 cp.code() += "} // block\n";
737 } // block
738 { // procedure
739 cp.code() += "{ // procedure\n";
740 cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";
741 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
742 cp.code() += "} // procedure\n";
743 } // procedure
744 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
745 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
746 // -----------------------------------------------------------------------------
747  cp.getAffectedRegisters().add("instructionPointer", 32);
748  }
749  {
750  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
751 
752  cp.code() = std::string("//__reserved_clui\n");
753 
754 // -----------------------------------------------------------------------------
755 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
756 // -----------------------------------------------------------------------------
757  }
758 
759  return true;
760  },
761  0,
762  [] (BitArray & ba, Instruction & instr)
763  {
764 // -----------------------------------------------------------------------------
765 etiss_uint8 rd = 0;
766 static BitArrayRange R_rd_0(11, 7);
767 rd += R_rd_0.read(ba) << 0;
768 
769 // -----------------------------------------------------------------------------
770 
771  std::stringstream ss;
772 // -----------------------------------------------------------------------------
773 ss << "__reserved_clui" << " # " << ba << (" [rd=" + std::to_string(rd) + "]");
774 // -----------------------------------------------------------------------------
775  return ss.str();
776  }
777 );
778 
779 // CSRLI -----------------------------------------------------------------------
780 static InstructionDefinition csrli_shamt_rs1 (
781  ISA16_RV64IMACFD,
782  "csrli",
783  (uint16_t) 0x8001,
784  (uint16_t) 0xfc03,
785  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
786  {
787 
788 // -----------------------------------------------------------------------------
789 
790 // -----------------------------------------------------------------------------
791 
792 // -----------------------------------------------------------------------------
793 etiss_uint8 shamt = 0;
794 static BitArrayRange R_shamt_0(6, 2);
795 shamt += R_shamt_0.read(ba) << 0;
796 etiss_uint8 rs1 = 0;
797 static BitArrayRange R_rs1_0(9, 7);
798 rs1 += R_rs1_0.read(ba) << 0;
799 
800 // -----------------------------------------------------------------------------
801 
802  {
803  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
804 
805  cp.code() = std::string("//CSRLI\n");
806 
807 // -----------------------------------------------------------------------------
808 { // block
809 cp.code() += "{ // block\n";
810 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
811 cp.code() += "} // block\n";
812 } // block
813 { // block
814 cp.code() += "{ // block\n";
815 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] >> " + std::to_string(shamt) + "ULL;\n";
816 cp.code() += "} // block\n";
817 } // block
818 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
819 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
820 // -----------------------------------------------------------------------------
821  cp.getAffectedRegisters().add("instructionPointer", 32);
822  }
823 
824  return true;
825  },
826  0,
827  [] (BitArray & ba, Instruction & instr)
828  {
829 // -----------------------------------------------------------------------------
830 etiss_uint8 shamt = 0;
831 static BitArrayRange R_shamt_0(6, 2);
832 shamt += R_shamt_0.read(ba) << 0;
833 etiss_uint8 rs1 = 0;
834 static BitArrayRange R_rs1_0(9, 7);
835 rs1 += R_rs1_0.read(ba) << 0;
836 
837 // -----------------------------------------------------------------------------
838 
839  std::stringstream ss;
840 // -----------------------------------------------------------------------------
841 ss << "csrli" << " # " << ba << (" [shamt=" + std::to_string(shamt) + " | rs1=" + std::to_string(rs1) + "]");
842 // -----------------------------------------------------------------------------
843  return ss.str();
844  }
845 );
846 
847 // CSRAI -----------------------------------------------------------------------
848 static InstructionDefinition csrai_shamt_rs1 (
849  ISA16_RV64IMACFD,
850  "csrai",
851  (uint16_t) 0x8401,
852  (uint16_t) 0xfc03,
853  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
854  {
855 
856 // -----------------------------------------------------------------------------
857 
858 // -----------------------------------------------------------------------------
859 
860 // -----------------------------------------------------------------------------
861 etiss_uint8 shamt = 0;
862 static BitArrayRange R_shamt_0(6, 2);
863 shamt += R_shamt_0.read(ba) << 0;
864 etiss_uint8 rs1 = 0;
865 static BitArrayRange R_rs1_0(9, 7);
866 rs1 += R_rs1_0.read(ba) << 0;
867 
868 // -----------------------------------------------------------------------------
869 
870  {
871  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
872 
873  cp.code() = std::string("//CSRAI\n");
874 
875 // -----------------------------------------------------------------------------
876 { // block
877 cp.code() += "{ // block\n";
878 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
879 cp.code() += "} // block\n";
880 } // block
881 { // block
882 cp.code() += "{ // block\n";
883 if (shamt) { // conditional
884 { // block
885 cp.code() += "{ // block\n";
886 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL])) >> " + std::to_string(shamt) + "ULL;\n";
887 cp.code() += "} // block\n";
888 } // block
889 } // conditional
890 cp.code() += "} // block\n";
891 } // block
892 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
893 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
894 // -----------------------------------------------------------------------------
895  cp.getAffectedRegisters().add("instructionPointer", 32);
896  }
897 
898  return true;
899  },
900  0,
901  [] (BitArray & ba, Instruction & instr)
902  {
903 // -----------------------------------------------------------------------------
904 etiss_uint8 shamt = 0;
905 static BitArrayRange R_shamt_0(6, 2);
906 shamt += R_shamt_0.read(ba) << 0;
907 etiss_uint8 rs1 = 0;
908 static BitArrayRange R_rs1_0(9, 7);
909 rs1 += R_rs1_0.read(ba) << 0;
910 
911 // -----------------------------------------------------------------------------
912 
913  std::stringstream ss;
914 // -----------------------------------------------------------------------------
915 ss << "csrai" << " # " << ba << (" [shamt=" + std::to_string(shamt) + " | rs1=" + std::to_string(rs1) + "]");
916 // -----------------------------------------------------------------------------
917  return ss.str();
918  }
919 );
920 
921 // CANDI -----------------------------------------------------------------------
922 static InstructionDefinition candi_imm_rs1 (
923  ISA16_RV64IMACFD,
924  "candi",
925  (uint16_t) 0x8801,
926  (uint16_t) 0xec03,
927  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
928  {
929 
930 // -----------------------------------------------------------------------------
931 
932 // -----------------------------------------------------------------------------
933 
934 // -----------------------------------------------------------------------------
935 etiss_uint8 imm = 0;
936 static BitArrayRange R_imm_0(6, 2);
937 imm += R_imm_0.read(ba) << 0;
938 etiss_uint8 rs1 = 0;
939 static BitArrayRange R_rs1_0(9, 7);
940 rs1 += R_rs1_0.read(ba) << 0;
941 static BitArrayRange R_imm_5(12, 12);
942 imm += R_imm_5.read(ba) << 5;
943 
944 // -----------------------------------------------------------------------------
945 
946  {
947  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
948 
949  cp.code() = std::string("//CANDI\n");
950 
951 // -----------------------------------------------------------------------------
952 { // block
953 cp.code() += "{ // block\n";
954 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
955 cp.code() += "} // block\n";
956 } // block
957 { // block
958 cp.code() += "{ // block\n";
959 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] & " + std::to_string(((etiss_int8)(((etiss_int8)imm) << (2)) >> (2))) + "LL;\n";
960 cp.code() += "} // block\n";
961 } // block
962 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
963 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
964 // -----------------------------------------------------------------------------
965  cp.getAffectedRegisters().add("instructionPointer", 32);
966  }
967 
968  return true;
969  },
970  0,
971  [] (BitArray & ba, Instruction & instr)
972  {
973 // -----------------------------------------------------------------------------
974 etiss_uint8 imm = 0;
975 static BitArrayRange R_imm_0(6, 2);
976 imm += R_imm_0.read(ba) << 0;
977 etiss_uint8 rs1 = 0;
978 static BitArrayRange R_rs1_0(9, 7);
979 rs1 += R_rs1_0.read(ba) << 0;
980 static BitArrayRange R_imm_5(12, 12);
981 imm += R_imm_5.read(ba) << 5;
982 
983 // -----------------------------------------------------------------------------
984 
985  std::stringstream ss;
986 // -----------------------------------------------------------------------------
987 ss << "candi" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + "]");
988 // -----------------------------------------------------------------------------
989  return ss.str();
990  }
991 );
992 
993 // CSUB ------------------------------------------------------------------------
994 static InstructionDefinition csub_rs2_rd (
995  ISA16_RV64IMACFD,
996  "csub",
997  (uint16_t) 0x8c01,
998  (uint16_t) 0xfc63,
999  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1000  {
1001 
1002 // -----------------------------------------------------------------------------
1003 
1004 // -----------------------------------------------------------------------------
1005 
1006 // -----------------------------------------------------------------------------
1007 etiss_uint8 rs2 = 0;
1008 static BitArrayRange R_rs2_0(4, 2);
1009 rs2 += R_rs2_0.read(ba) << 0;
1010 etiss_uint8 rd = 0;
1011 static BitArrayRange R_rd_0(9, 7);
1012 rd += R_rd_0.read(ba) << 0;
1013 
1014 // -----------------------------------------------------------------------------
1015 
1016  {
1017  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1018 
1019  cp.code() = std::string("//CSUB\n");
1020 
1021 // -----------------------------------------------------------------------------
1022 { // block
1023 cp.code() += "{ // block\n";
1024 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1025 cp.code() += "} // block\n";
1026 } // block
1027 { // block
1028 cp.code() += "{ // block\n";
1029 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] - *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n";
1030 cp.code() += "} // block\n";
1031 } // block
1032 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1033 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1034 // -----------------------------------------------------------------------------
1035  cp.getAffectedRegisters().add("instructionPointer", 32);
1036  }
1037 
1038  return true;
1039  },
1040  0,
1041  [] (BitArray & ba, Instruction & instr)
1042  {
1043 // -----------------------------------------------------------------------------
1044 etiss_uint8 rs2 = 0;
1045 static BitArrayRange R_rs2_0(4, 2);
1046 rs2 += R_rs2_0.read(ba) << 0;
1047 etiss_uint8 rd = 0;
1048 static BitArrayRange R_rd_0(9, 7);
1049 rd += R_rd_0.read(ba) << 0;
1050 
1051 // -----------------------------------------------------------------------------
1052 
1053  std::stringstream ss;
1054 // -----------------------------------------------------------------------------
1055 ss << "csub" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]");
1056 // -----------------------------------------------------------------------------
1057  return ss.str();
1058  }
1059 );
1060 
1061 // CXOR ------------------------------------------------------------------------
1062 static InstructionDefinition cxor_rs2_rd (
1063  ISA16_RV64IMACFD,
1064  "cxor",
1065  (uint16_t) 0x8c21,
1066  (uint16_t) 0xfc63,
1067  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1068  {
1069 
1070 // -----------------------------------------------------------------------------
1071 
1072 // -----------------------------------------------------------------------------
1073 
1074 // -----------------------------------------------------------------------------
1075 etiss_uint8 rs2 = 0;
1076 static BitArrayRange R_rs2_0(4, 2);
1077 rs2 += R_rs2_0.read(ba) << 0;
1078 etiss_uint8 rd = 0;
1079 static BitArrayRange R_rd_0(9, 7);
1080 rd += R_rd_0.read(ba) << 0;
1081 
1082 // -----------------------------------------------------------------------------
1083 
1084  {
1085  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1086 
1087  cp.code() = std::string("//CXOR\n");
1088 
1089 // -----------------------------------------------------------------------------
1090 { // block
1091 cp.code() += "{ // block\n";
1092 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1093 cp.code() += "} // block\n";
1094 } // block
1095 { // block
1096 cp.code() += "{ // block\n";
1097 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n";
1098 cp.code() += "} // block\n";
1099 } // block
1100 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1101 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1102 // -----------------------------------------------------------------------------
1103  cp.getAffectedRegisters().add("instructionPointer", 32);
1104  }
1105 
1106  return true;
1107  },
1108  0,
1109  [] (BitArray & ba, Instruction & instr)
1110  {
1111 // -----------------------------------------------------------------------------
1112 etiss_uint8 rs2 = 0;
1113 static BitArrayRange R_rs2_0(4, 2);
1114 rs2 += R_rs2_0.read(ba) << 0;
1115 etiss_uint8 rd = 0;
1116 static BitArrayRange R_rd_0(9, 7);
1117 rd += R_rd_0.read(ba) << 0;
1118 
1119 // -----------------------------------------------------------------------------
1120 
1121  std::stringstream ss;
1122 // -----------------------------------------------------------------------------
1123 ss << "cxor" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]");
1124 // -----------------------------------------------------------------------------
1125  return ss.str();
1126  }
1127 );
1128 
1129 // COR -------------------------------------------------------------------------
1130 static InstructionDefinition cor_rs2_rd (
1131  ISA16_RV64IMACFD,
1132  "cor",
1133  (uint16_t) 0x8c41,
1134  (uint16_t) 0xfc63,
1135  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1136  {
1137 
1138 // -----------------------------------------------------------------------------
1139 
1140 // -----------------------------------------------------------------------------
1141 
1142 // -----------------------------------------------------------------------------
1143 etiss_uint8 rs2 = 0;
1144 static BitArrayRange R_rs2_0(4, 2);
1145 rs2 += R_rs2_0.read(ba) << 0;
1146 etiss_uint8 rd = 0;
1147 static BitArrayRange R_rd_0(9, 7);
1148 rd += R_rd_0.read(ba) << 0;
1149 
1150 // -----------------------------------------------------------------------------
1151 
1152  {
1153  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1154 
1155  cp.code() = std::string("//COR\n");
1156 
1157 // -----------------------------------------------------------------------------
1158 { // block
1159 cp.code() += "{ // block\n";
1160 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1161 cp.code() += "} // block\n";
1162 } // block
1163 { // block
1164 cp.code() += "{ // block\n";
1165 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n";
1166 cp.code() += "} // block\n";
1167 } // block
1168 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1169 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1170 // -----------------------------------------------------------------------------
1171  cp.getAffectedRegisters().add("instructionPointer", 32);
1172  }
1173 
1174  return true;
1175  },
1176  0,
1177  [] (BitArray & ba, Instruction & instr)
1178  {
1179 // -----------------------------------------------------------------------------
1180 etiss_uint8 rs2 = 0;
1181 static BitArrayRange R_rs2_0(4, 2);
1182 rs2 += R_rs2_0.read(ba) << 0;
1183 etiss_uint8 rd = 0;
1184 static BitArrayRange R_rd_0(9, 7);
1185 rd += R_rd_0.read(ba) << 0;
1186 
1187 // -----------------------------------------------------------------------------
1188 
1189  std::stringstream ss;
1190 // -----------------------------------------------------------------------------
1191 ss << "cor" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]");
1192 // -----------------------------------------------------------------------------
1193  return ss.str();
1194  }
1195 );
1196 
1197 // CAND ------------------------------------------------------------------------
1198 static InstructionDefinition cand_rs2_rd (
1199  ISA16_RV64IMACFD,
1200  "cand",
1201  (uint16_t) 0x8c61,
1202  (uint16_t) 0xfc63,
1203  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1204  {
1205 
1206 // -----------------------------------------------------------------------------
1207 
1208 // -----------------------------------------------------------------------------
1209 
1210 // -----------------------------------------------------------------------------
1211 etiss_uint8 rs2 = 0;
1212 static BitArrayRange R_rs2_0(4, 2);
1213 rs2 += R_rs2_0.read(ba) << 0;
1214 etiss_uint8 rd = 0;
1215 static BitArrayRange R_rd_0(9, 7);
1216 rd += R_rd_0.read(ba) << 0;
1217 
1218 // -----------------------------------------------------------------------------
1219 
1220  {
1221  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1222 
1223  cp.code() = std::string("//CAND\n");
1224 
1225 // -----------------------------------------------------------------------------
1226 { // block
1227 cp.code() += "{ // block\n";
1228 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1229 cp.code() += "} // block\n";
1230 } // block
1231 { // block
1232 cp.code() += "{ // block\n";
1233 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n";
1234 cp.code() += "} // block\n";
1235 } // block
1236 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1237 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1238 // -----------------------------------------------------------------------------
1239  cp.getAffectedRegisters().add("instructionPointer", 32);
1240  }
1241 
1242  return true;
1243  },
1244  0,
1245  [] (BitArray & ba, Instruction & instr)
1246  {
1247 // -----------------------------------------------------------------------------
1248 etiss_uint8 rs2 = 0;
1249 static BitArrayRange R_rs2_0(4, 2);
1250 rs2 += R_rs2_0.read(ba) << 0;
1251 etiss_uint8 rd = 0;
1252 static BitArrayRange R_rd_0(9, 7);
1253 rd += R_rd_0.read(ba) << 0;
1254 
1255 // -----------------------------------------------------------------------------
1256 
1257  std::stringstream ss;
1258 // -----------------------------------------------------------------------------
1259 ss << "cand" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]");
1260 // -----------------------------------------------------------------------------
1261  return ss.str();
1262  }
1263 );
1264 
1265 // CJ --------------------------------------------------------------------------
1266 static InstructionDefinition cj_imm (
1267  ISA16_RV64IMACFD,
1268  "cj",
1269  (uint16_t) 0xa001,
1270  (uint16_t) 0xe003,
1271  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1272  {
1273 
1274 // -----------------------------------------------------------------------------
1275 
1276 // -----------------------------------------------------------------------------
1277 
1278 // -----------------------------------------------------------------------------
1279 etiss_uint16 imm = 0;
1280 static BitArrayRange R_imm_5(2, 2);
1281 imm += R_imm_5.read(ba) << 5;
1282 static BitArrayRange R_imm_1(5, 3);
1283 imm += R_imm_1.read(ba) << 1;
1284 static BitArrayRange R_imm_7(6, 6);
1285 imm += R_imm_7.read(ba) << 7;
1286 static BitArrayRange R_imm_6(7, 7);
1287 imm += R_imm_6.read(ba) << 6;
1288 static BitArrayRange R_imm_10(8, 8);
1289 imm += R_imm_10.read(ba) << 10;
1290 static BitArrayRange R_imm_8(10, 9);
1291 imm += R_imm_8.read(ba) << 8;
1292 static BitArrayRange R_imm_4(11, 11);
1293 imm += R_imm_4.read(ba) << 4;
1294 static BitArrayRange R_imm_11(12, 12);
1295 imm += R_imm_11.read(ba) << 11;
1296 
1297 // -----------------------------------------------------------------------------
1298 
1299  {
1300  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1301 
1302  cp.code() = std::string("//CJ\n");
1303 
1304 // -----------------------------------------------------------------------------
1305 { // block
1306 cp.code() += "{ // block\n";
1307 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1308 cp.code() += "} // block\n";
1309 } // block
1310 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1311 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1312 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1313 // -----------------------------------------------------------------------------
1314  cp.getAffectedRegisters().add("instructionPointer", 32);
1315  }
1316  {
1317  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1318 
1319  cp.code() = std::string("//CJ\n");
1320 
1321 // -----------------------------------------------------------------------------
1322 cp.code() += "return cpu->exception;\n";
1323 // -----------------------------------------------------------------------------
1324  }
1325 
1326  return true;
1327  },
1328  0,
1329  [] (BitArray & ba, Instruction & instr)
1330  {
1331 // -----------------------------------------------------------------------------
1332 etiss_uint16 imm = 0;
1333 static BitArrayRange R_imm_5(2, 2);
1334 imm += R_imm_5.read(ba) << 5;
1335 static BitArrayRange R_imm_1(5, 3);
1336 imm += R_imm_1.read(ba) << 1;
1337 static BitArrayRange R_imm_7(6, 6);
1338 imm += R_imm_7.read(ba) << 7;
1339 static BitArrayRange R_imm_6(7, 7);
1340 imm += R_imm_6.read(ba) << 6;
1341 static BitArrayRange R_imm_10(8, 8);
1342 imm += R_imm_10.read(ba) << 10;
1343 static BitArrayRange R_imm_8(10, 9);
1344 imm += R_imm_8.read(ba) << 8;
1345 static BitArrayRange R_imm_4(11, 11);
1346 imm += R_imm_4.read(ba) << 4;
1347 static BitArrayRange R_imm_11(12, 12);
1348 imm += R_imm_11.read(ba) << 11;
1349 
1350 // -----------------------------------------------------------------------------
1351 
1352  std::stringstream ss;
1353 // -----------------------------------------------------------------------------
1354 ss << "cj" << " # " << ba << (" [imm=" + std::to_string(imm) + "]");
1355 // -----------------------------------------------------------------------------
1356  return ss.str();
1357  }
1358 );
1359 
1360 // CBEQZ -----------------------------------------------------------------------
1361 static InstructionDefinition cbeqz_imm_rs1 (
1362  ISA16_RV64IMACFD,
1363  "cbeqz",
1364  (uint16_t) 0xc001,
1365  (uint16_t) 0xe003,
1366  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1367  {
1368 
1369 // -----------------------------------------------------------------------------
1370 
1371 // -----------------------------------------------------------------------------
1372 
1373 // -----------------------------------------------------------------------------
1374 etiss_uint16 imm = 0;
1375 static BitArrayRange R_imm_5(2, 2);
1376 imm += R_imm_5.read(ba) << 5;
1377 static BitArrayRange R_imm_1(4, 3);
1378 imm += R_imm_1.read(ba) << 1;
1379 static BitArrayRange R_imm_6(6, 5);
1380 imm += R_imm_6.read(ba) << 6;
1381 etiss_uint8 rs1 = 0;
1382 static BitArrayRange R_rs1_0(9, 7);
1383 rs1 += R_rs1_0.read(ba) << 0;
1384 static BitArrayRange R_imm_3(11, 10);
1385 imm += R_imm_3.read(ba) << 3;
1386 static BitArrayRange R_imm_8(12, 12);
1387 imm += R_imm_8.read(ba) << 8;
1388 
1389 // -----------------------------------------------------------------------------
1390 
1391  {
1392  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1393 
1394  cp.code() = std::string("//CBEQZ\n");
1395 
1396 // -----------------------------------------------------------------------------
1397 { // block
1398 cp.code() += "{ // block\n";
1399 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1400 cp.code() += "} // block\n";
1401 } // block
1402 cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] == 0LL) { // conditional\n";
1403 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (7)) >> (7))) + "LL;\n";
1404 cp.code() += "} // conditional\n";
1405 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1406 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1407 // -----------------------------------------------------------------------------
1408  cp.getAffectedRegisters().add("instructionPointer", 32);
1409  }
1410  {
1411  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1412 
1413  cp.code() = std::string("//CBEQZ\n");
1414 
1415 // -----------------------------------------------------------------------------
1416 cp.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + "ULL) return cpu->exception;\n";
1417 // -----------------------------------------------------------------------------
1418  }
1419 
1420  return true;
1421  },
1422  0,
1423  [] (BitArray & ba, Instruction & instr)
1424  {
1425 // -----------------------------------------------------------------------------
1426 etiss_uint16 imm = 0;
1427 static BitArrayRange R_imm_5(2, 2);
1428 imm += R_imm_5.read(ba) << 5;
1429 static BitArrayRange R_imm_1(4, 3);
1430 imm += R_imm_1.read(ba) << 1;
1431 static BitArrayRange R_imm_6(6, 5);
1432 imm += R_imm_6.read(ba) << 6;
1433 etiss_uint8 rs1 = 0;
1434 static BitArrayRange R_rs1_0(9, 7);
1435 rs1 += R_rs1_0.read(ba) << 0;
1436 static BitArrayRange R_imm_3(11, 10);
1437 imm += R_imm_3.read(ba) << 3;
1438 static BitArrayRange R_imm_8(12, 12);
1439 imm += R_imm_8.read(ba) << 8;
1440 
1441 // -----------------------------------------------------------------------------
1442 
1443  std::stringstream ss;
1444 // -----------------------------------------------------------------------------
1445 ss << "cbeqz" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + "]");
1446 // -----------------------------------------------------------------------------
1447  return ss.str();
1448  }
1449 );
1450 
1451 // CBNEZ -----------------------------------------------------------------------
1452 static InstructionDefinition cbnez_imm_rs1 (
1453  ISA16_RV64IMACFD,
1454  "cbnez",
1455  (uint16_t) 0xe001,
1456  (uint16_t) 0xe003,
1457  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1458  {
1459 
1460 // -----------------------------------------------------------------------------
1461 
1462 // -----------------------------------------------------------------------------
1463 
1464 // -----------------------------------------------------------------------------
1465 etiss_uint16 imm = 0;
1466 static BitArrayRange R_imm_5(2, 2);
1467 imm += R_imm_5.read(ba) << 5;
1468 static BitArrayRange R_imm_1(4, 3);
1469 imm += R_imm_1.read(ba) << 1;
1470 static BitArrayRange R_imm_6(6, 5);
1471 imm += R_imm_6.read(ba) << 6;
1472 etiss_uint8 rs1 = 0;
1473 static BitArrayRange R_rs1_0(9, 7);
1474 rs1 += R_rs1_0.read(ba) << 0;
1475 static BitArrayRange R_imm_3(11, 10);
1476 imm += R_imm_3.read(ba) << 3;
1477 static BitArrayRange R_imm_8(12, 12);
1478 imm += R_imm_8.read(ba) << 8;
1479 
1480 // -----------------------------------------------------------------------------
1481 
1482  {
1483  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1484 
1485  cp.code() = std::string("//CBNEZ\n");
1486 
1487 // -----------------------------------------------------------------------------
1488 { // block
1489 cp.code() += "{ // block\n";
1490 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1491 cp.code() += "} // block\n";
1492 } // block
1493 cp.code() += "if (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] != 0LL) { // conditional\n";
1494 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (7)) >> (7))) + "LL;\n";
1495 cp.code() += "} // conditional\n";
1496 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1497 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1498 // -----------------------------------------------------------------------------
1499  cp.getAffectedRegisters().add("instructionPointer", 32);
1500  }
1501  {
1502  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1503 
1504  cp.code() = std::string("//CBNEZ\n");
1505 
1506 // -----------------------------------------------------------------------------
1507 cp.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + "ULL) return cpu->exception;\n";
1508 // -----------------------------------------------------------------------------
1509  }
1510 
1511  return true;
1512  },
1513  0,
1514  [] (BitArray & ba, Instruction & instr)
1515  {
1516 // -----------------------------------------------------------------------------
1517 etiss_uint16 imm = 0;
1518 static BitArrayRange R_imm_5(2, 2);
1519 imm += R_imm_5.read(ba) << 5;
1520 static BitArrayRange R_imm_1(4, 3);
1521 imm += R_imm_1.read(ba) << 1;
1522 static BitArrayRange R_imm_6(6, 5);
1523 imm += R_imm_6.read(ba) << 6;
1524 etiss_uint8 rs1 = 0;
1525 static BitArrayRange R_rs1_0(9, 7);
1526 rs1 += R_rs1_0.read(ba) << 0;
1527 static BitArrayRange R_imm_3(11, 10);
1528 imm += R_imm_3.read(ba) << 3;
1529 static BitArrayRange R_imm_8(12, 12);
1530 imm += R_imm_8.read(ba) << 8;
1531 
1532 // -----------------------------------------------------------------------------
1533 
1534  std::stringstream ss;
1535 // -----------------------------------------------------------------------------
1536 ss << "cbnez" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + "]");
1537 // -----------------------------------------------------------------------------
1538  return ss.str();
1539  }
1540 );
1541 
1542 // CSLLI -----------------------------------------------------------------------
1543 static InstructionDefinition cslli_nzuimm_rs1 (
1544  ISA16_RV64IMACFD,
1545  "cslli",
1546  (uint16_t) 0x02,
1547  (uint16_t) 0xf003,
1548  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1549  {
1550 
1551 // -----------------------------------------------------------------------------
1552 
1553 // -----------------------------------------------------------------------------
1554 
1555 // -----------------------------------------------------------------------------
1556 etiss_uint8 nzuimm = 0;
1557 static BitArrayRange R_nzuimm_0(6, 2);
1558 nzuimm += R_nzuimm_0.read(ba) << 0;
1559 etiss_uint8 rs1 = 0;
1560 static BitArrayRange R_rs1_0(11, 7);
1561 rs1 += R_rs1_0.read(ba) << 0;
1562 
1563 // -----------------------------------------------------------------------------
1564 
1565  {
1566  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1567 
1568  cp.code() = std::string("//CSLLI\n");
1569 
1570 // -----------------------------------------------------------------------------
1571 { // block
1572 cp.code() += "{ // block\n";
1573 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1574 cp.code() += "} // block\n";
1575 } // block
1576 if (nzuimm) { // conditional
1577 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << " + std::to_string(nzuimm) + "ULL;\n";
1578 } // conditional
1579 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1580 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1581 // -----------------------------------------------------------------------------
1582  cp.getAffectedRegisters().add("instructionPointer", 32);
1583  }
1584 
1585  return true;
1586  },
1587  0,
1588  [] (BitArray & ba, Instruction & instr)
1589  {
1590 // -----------------------------------------------------------------------------
1591 etiss_uint8 nzuimm = 0;
1592 static BitArrayRange R_nzuimm_0(6, 2);
1593 nzuimm += R_nzuimm_0.read(ba) << 0;
1594 etiss_uint8 rs1 = 0;
1595 static BitArrayRange R_rs1_0(11, 7);
1596 rs1 += R_rs1_0.read(ba) << 0;
1597 
1598 // -----------------------------------------------------------------------------
1599 
1600  std::stringstream ss;
1601 // -----------------------------------------------------------------------------
1602 ss << "cslli" << " # " << ba << (" [nzuimm=" + std::to_string(nzuimm) + " | rs1=" + std::to_string(rs1) + "]");
1603 // -----------------------------------------------------------------------------
1604  return ss.str();
1605  }
1606 );
1607 
1608 // CLWSP -----------------------------------------------------------------------
1609 static InstructionDefinition clwsp_uimm_rd (
1610  ISA16_RV64IMACFD,
1611  "clwsp",
1612  (uint16_t) 0x4002,
1613  (uint16_t) 0xe003,
1614  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1615  {
1616 
1617 // -----------------------------------------------------------------------------
1618 
1619 // -----------------------------------------------------------------------------
1620 
1621 // -----------------------------------------------------------------------------
1622 etiss_uint8 uimm = 0;
1623 static BitArrayRange R_uimm_6(3, 2);
1624 uimm += R_uimm_6.read(ba) << 6;
1625 static BitArrayRange R_uimm_2(6, 4);
1626 uimm += R_uimm_2.read(ba) << 2;
1627 etiss_uint8 rd = 0;
1628 static BitArrayRange R_rd_0(11, 7);
1629 rd += R_rd_0.read(ba) << 0;
1630 static BitArrayRange R_uimm_5(12, 12);
1631 uimm += R_uimm_5.read(ba) << 5;
1632 
1633 // -----------------------------------------------------------------------------
1634 
1635  {
1636  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1637 
1638  cp.code() = std::string("//CLWSP\n");
1639 
1640 // -----------------------------------------------------------------------------
1641 { // block
1642 cp.code() += "{ // block\n";
1643 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1644 cp.code() += "} // block\n";
1645 } // block
1646 { // block
1647 cp.code() += "{ // block\n";
1648 if (rd % 32ULL) { // conditional
1649 { // block
1650 cp.code() += "{ // block\n";
1651 cp.code() += "etiss_uint32 mem_val_0;\n";
1652 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL, (etiss_uint8*)&mem_val_0, 4);\n";
1653 cp.code() += "if (cpu->exception) { // conditional\n";
1654 { // procedure
1655 cp.code() += "{ // procedure\n";
1656 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1657 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1658 cp.code() += "} // procedure\n";
1659 } // procedure
1660 cp.code() += "} // conditional\n";
1661 cp.code() += "etiss_int32 res = mem_val_0;\n";
1662 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int64)(res);\n";
1663 cp.code() += "} // block\n";
1664 } // block
1665 } // conditional
1666 else { // conditional
1667 { // procedure
1668 cp.code() += "{ // procedure\n";
1669 cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2ULL);\n";
1670 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1671 cp.code() += "} // procedure\n";
1672 } // procedure
1673 } // conditional
1674 cp.code() += "} // block\n";
1675 } // block
1676 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1677 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1678 // -----------------------------------------------------------------------------
1679  cp.getAffectedRegisters().add("instructionPointer", 32);
1680  }
1681  {
1682  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1683 
1684  cp.code() = std::string("//CLWSP\n");
1685 
1686 // -----------------------------------------------------------------------------
1687 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1688 // -----------------------------------------------------------------------------
1689  }
1690 
1691  return true;
1692  },
1693  0,
1694  [] (BitArray & ba, Instruction & instr)
1695  {
1696 // -----------------------------------------------------------------------------
1697 etiss_uint8 uimm = 0;
1698 static BitArrayRange R_uimm_6(3, 2);
1699 uimm += R_uimm_6.read(ba) << 6;
1700 static BitArrayRange R_uimm_2(6, 4);
1701 uimm += R_uimm_2.read(ba) << 2;
1702 etiss_uint8 rd = 0;
1703 static BitArrayRange R_rd_0(11, 7);
1704 rd += R_rd_0.read(ba) << 0;
1705 static BitArrayRange R_uimm_5(12, 12);
1706 uimm += R_uimm_5.read(ba) << 5;
1707 
1708 // -----------------------------------------------------------------------------
1709 
1710  std::stringstream ss;
1711 // -----------------------------------------------------------------------------
1712 ss << "clwsp" << " # " << ba << (" [uimm=" + std::to_string(uimm) + " | rd=" + std::to_string(rd) + "]");
1713 // -----------------------------------------------------------------------------
1714  return ss.str();
1715  }
1716 );
1717 
1718 // CMV -------------------------------------------------------------------------
1719 static InstructionDefinition cmv_rs2_rd (
1720  ISA16_RV64IMACFD,
1721  "cmv",
1722  (uint16_t) 0x8002,
1723  (uint16_t) 0xf003,
1724  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1725  {
1726 
1727 // -----------------------------------------------------------------------------
1728 
1729 // -----------------------------------------------------------------------------
1730 
1731 // -----------------------------------------------------------------------------
1732 etiss_uint8 rs2 = 0;
1733 static BitArrayRange R_rs2_0(6, 2);
1734 rs2 += R_rs2_0.read(ba) << 0;
1735 etiss_uint8 rd = 0;
1736 static BitArrayRange R_rd_0(11, 7);
1737 rd += R_rd_0.read(ba) << 0;
1738 
1739 // -----------------------------------------------------------------------------
1740 
1741  {
1742  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1743 
1744  cp.code() = std::string("//CMV\n");
1745 
1746 // -----------------------------------------------------------------------------
1747 { // block
1748 cp.code() += "{ // block\n";
1749 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1750 cp.code() += "} // block\n";
1751 } // block
1752 if ((rd % 32ULL) != 0LL) { // conditional
1753 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
1754 } // conditional
1755 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1756 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1757 // -----------------------------------------------------------------------------
1758  cp.getAffectedRegisters().add("instructionPointer", 32);
1759  }
1760 
1761  return true;
1762  },
1763  0,
1764  [] (BitArray & ba, Instruction & instr)
1765  {
1766 // -----------------------------------------------------------------------------
1767 etiss_uint8 rs2 = 0;
1768 static BitArrayRange R_rs2_0(6, 2);
1769 rs2 += R_rs2_0.read(ba) << 0;
1770 etiss_uint8 rd = 0;
1771 static BitArrayRange R_rd_0(11, 7);
1772 rd += R_rd_0.read(ba) << 0;
1773 
1774 // -----------------------------------------------------------------------------
1775 
1776  std::stringstream ss;
1777 // -----------------------------------------------------------------------------
1778 ss << "cmv" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]");
1779 // -----------------------------------------------------------------------------
1780  return ss.str();
1781  }
1782 );
1783 
1784 // CJR -------------------------------------------------------------------------
1785 static InstructionDefinition cjr_rs1 (
1786  ISA16_RV64IMACFD,
1787  "cjr",
1788  (uint16_t) 0x8002,
1789  (uint16_t) 0xf07f,
1790  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1791  {
1792 
1793 // -----------------------------------------------------------------------------
1794 
1795 // -----------------------------------------------------------------------------
1796 
1797 // -----------------------------------------------------------------------------
1798 etiss_uint8 rs1 = 0;
1799 static BitArrayRange R_rs1_0(11, 7);
1800 rs1 += R_rs1_0.read(ba) << 0;
1801 
1802 // -----------------------------------------------------------------------------
1803 
1804  {
1805  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1806 
1807  cp.code() = std::string("//CJR\n");
1808 
1809 // -----------------------------------------------------------------------------
1810 { // block
1811 cp.code() += "{ // block\n";
1812 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1813 cp.code() += "} // block\n";
1814 } // block
1815 if (rs1) { // conditional
1816 cp.code() += "cpu->nextPc = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] & -2LL;\n";
1817 } // conditional
1818 else { // conditional
1819 { // procedure
1820 cp.code() += "{ // procedure\n";
1821 cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2ULL);\n";
1822 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1823 cp.code() += "} // procedure\n";
1824 } // procedure
1825 } // conditional
1826 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1827 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1828 // -----------------------------------------------------------------------------
1829  cp.getAffectedRegisters().add("instructionPointer", 32);
1830  }
1831  {
1832  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1833 
1834  cp.code() = std::string("//CJR\n");
1835 
1836 // -----------------------------------------------------------------------------
1837 cp.code() += "return cpu->exception;\n";
1838 // -----------------------------------------------------------------------------
1839  }
1840 
1841  return true;
1842  },
1843  0,
1844  [] (BitArray & ba, Instruction & instr)
1845  {
1846 // -----------------------------------------------------------------------------
1847 etiss_uint8 rs1 = 0;
1848 static BitArrayRange R_rs1_0(11, 7);
1849 rs1 += R_rs1_0.read(ba) << 0;
1850 
1851 // -----------------------------------------------------------------------------
1852 
1853  std::stringstream ss;
1854 // -----------------------------------------------------------------------------
1855 ss << "cjr" << " # " << ba << (" [rs1=" + std::to_string(rs1) + "]");
1856 // -----------------------------------------------------------------------------
1857  return ss.str();
1858  }
1859 );
1860 
1861 // __reserved_cmv --------------------------------------------------------------
1862 static InstructionDefinition __reserved_cmv_ (
1863  ISA16_RV64IMACFD,
1864  "__reserved_cmv",
1865  (uint16_t) 0x8002,
1866  (uint16_t) 0xffff,
1867  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1868  {
1869 
1870 // -----------------------------------------------------------------------------
1871 
1872 // -----------------------------------------------------------------------------
1873 
1874 // -----------------------------------------------------------------------------
1875 
1876 // -----------------------------------------------------------------------------
1877 
1878  {
1879  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1880 
1881  cp.code() = std::string("//__reserved_cmv\n");
1882 
1883 // -----------------------------------------------------------------------------
1884 { // block
1885 cp.code() += "{ // block\n";
1886 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1887 cp.code() += "} // block\n";
1888 } // block
1889 { // procedure
1890 cp.code() += "{ // procedure\n";
1891 cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2ULL);\n";
1892 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1893 cp.code() += "} // procedure\n";
1894 } // procedure
1895 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1896 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1897 // -----------------------------------------------------------------------------
1898  cp.getAffectedRegisters().add("instructionPointer", 32);
1899  }
1900  {
1901  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1902 
1903  cp.code() = std::string("//__reserved_cmv\n");
1904 
1905 // -----------------------------------------------------------------------------
1906 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1907 // -----------------------------------------------------------------------------
1908  }
1909 
1910  return true;
1911  },
1912  0,
1913  [] (BitArray & ba, Instruction & instr)
1914  {
1915 // -----------------------------------------------------------------------------
1916 
1917 // -----------------------------------------------------------------------------
1918 
1919  std::stringstream ss;
1920 // -----------------------------------------------------------------------------
1921 ss << "__reserved_cmv" << " # " << ba << (" []");
1922 // -----------------------------------------------------------------------------
1923  return ss.str();
1924  }
1925 );
1926 
1927 // CADD ------------------------------------------------------------------------
1928 static InstructionDefinition cadd_rs2_rd (
1929  ISA16_RV64IMACFD,
1930  "cadd",
1931  (uint16_t) 0x9002,
1932  (uint16_t) 0xf003,
1933  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1934  {
1935 
1936 // -----------------------------------------------------------------------------
1937 
1938 // -----------------------------------------------------------------------------
1939 
1940 // -----------------------------------------------------------------------------
1941 etiss_uint8 rs2 = 0;
1942 static BitArrayRange R_rs2_0(6, 2);
1943 rs2 += R_rs2_0.read(ba) << 0;
1944 etiss_uint8 rd = 0;
1945 static BitArrayRange R_rd_0(11, 7);
1946 rd += R_rd_0.read(ba) << 0;
1947 
1948 // -----------------------------------------------------------------------------
1949 
1950  {
1951  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1952 
1953  cp.code() = std::string("//CADD\n");
1954 
1955 // -----------------------------------------------------------------------------
1956 { // block
1957 cp.code() += "{ // block\n";
1958 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1959 cp.code() += "} // block\n";
1960 } // block
1961 if ((rd % 32ULL) != 0LL) { // conditional
1962 cp.code() += "*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
1963 } // conditional
1964 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1965 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1966 // -----------------------------------------------------------------------------
1967  cp.getAffectedRegisters().add("instructionPointer", 32);
1968  }
1969 
1970  return true;
1971  },
1972  0,
1973  [] (BitArray & ba, Instruction & instr)
1974  {
1975 // -----------------------------------------------------------------------------
1976 etiss_uint8 rs2 = 0;
1977 static BitArrayRange R_rs2_0(6, 2);
1978 rs2 += R_rs2_0.read(ba) << 0;
1979 etiss_uint8 rd = 0;
1980 static BitArrayRange R_rd_0(11, 7);
1981 rd += R_rd_0.read(ba) << 0;
1982 
1983 // -----------------------------------------------------------------------------
1984 
1985  std::stringstream ss;
1986 // -----------------------------------------------------------------------------
1987 ss << "cadd" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]");
1988 // -----------------------------------------------------------------------------
1989  return ss.str();
1990  }
1991 );
1992 
1993 // CJALR -----------------------------------------------------------------------
1994 static InstructionDefinition cjalr_rs1 (
1995  ISA16_RV64IMACFD,
1996  "cjalr",
1997  (uint16_t) 0x9002,
1998  (uint16_t) 0xf07f,
1999  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2000  {
2001 
2002 // -----------------------------------------------------------------------------
2003 
2004 // -----------------------------------------------------------------------------
2005 
2006 // -----------------------------------------------------------------------------
2007 etiss_uint8 rs1 = 0;
2008 static BitArrayRange R_rs1_0(11, 7);
2009 rs1 += R_rs1_0.read(ba) << 0;
2010 
2011 // -----------------------------------------------------------------------------
2012 
2013  {
2014  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2015 
2016  cp.code() = std::string("//CJALR\n");
2017 
2018 // -----------------------------------------------------------------------------
2019 { // block
2020 cp.code() += "{ // block\n";
2021 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
2022 cp.code() += "} // block\n";
2023 } // block
2024 { // block
2025 cp.code() += "{ // block\n";
2026 cp.code() += "etiss_uint64 new_pc = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
2027 cp.code() += "*((RV64IMACFD*)cpu)->X[1ULL] = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
2028 cp.code() += "cpu->nextPc = new_pc & -2LL;\n";
2029 cp.code() += "} // block\n";
2030 } // block
2031 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2032 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2033 // -----------------------------------------------------------------------------
2034  cp.getAffectedRegisters().add("instructionPointer", 32);
2035  }
2036  {
2037  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
2038 
2039  cp.code() = std::string("//CJALR\n");
2040 
2041 // -----------------------------------------------------------------------------
2042 cp.code() += "return cpu->exception;\n";
2043 // -----------------------------------------------------------------------------
2044  }
2045 
2046  return true;
2047  },
2048  0,
2049  [] (BitArray & ba, Instruction & instr)
2050  {
2051 // -----------------------------------------------------------------------------
2052 etiss_uint8 rs1 = 0;
2053 static BitArrayRange R_rs1_0(11, 7);
2054 rs1 += R_rs1_0.read(ba) << 0;
2055 
2056 // -----------------------------------------------------------------------------
2057 
2058  std::stringstream ss;
2059 // -----------------------------------------------------------------------------
2060 ss << "cjalr" << " # " << ba << (" [rs1=" + std::to_string(rs1) + "]");
2061 // -----------------------------------------------------------------------------
2062  return ss.str();
2063  }
2064 );
2065 
2066 // CEBREAK ---------------------------------------------------------------------
2067 static InstructionDefinition cebreak_ (
2068  ISA16_RV64IMACFD,
2069  "cebreak",
2070  (uint16_t) 0x9002,
2071  (uint16_t) 0xffff,
2072  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2073  {
2074 
2075 // -----------------------------------------------------------------------------
2076 
2077 // -----------------------------------------------------------------------------
2078 
2079 // -----------------------------------------------------------------------------
2080 
2081 // -----------------------------------------------------------------------------
2082 
2083  {
2084  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2085 
2086  cp.code() = std::string("//CEBREAK\n");
2087 
2088 // -----------------------------------------------------------------------------
2089 { // block
2090 cp.code() += "{ // block\n";
2091 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
2092 cp.code() += "} // block\n";
2093 } // block
2094 { // procedure
2095 cp.code() += "{ // procedure\n";
2096 cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 3LL);\n";
2097 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
2098 cp.code() += "} // procedure\n";
2099 } // procedure
2100 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2101 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2102 // -----------------------------------------------------------------------------
2103  cp.getAffectedRegisters().add("instructionPointer", 32);
2104  }
2105  {
2106  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
2107 
2108  cp.code() = std::string("//CEBREAK\n");
2109 
2110 // -----------------------------------------------------------------------------
2111 cp.code() += "return cpu->exception;\n";
2112 // -----------------------------------------------------------------------------
2113  }
2114 
2115  return true;
2116  },
2117  0,
2118  [] (BitArray & ba, Instruction & instr)
2119  {
2120 // -----------------------------------------------------------------------------
2121 
2122 // -----------------------------------------------------------------------------
2123 
2124  std::stringstream ss;
2125 // -----------------------------------------------------------------------------
2126 ss << "cebreak" << " # " << ba << (" []");
2127 // -----------------------------------------------------------------------------
2128  return ss.str();
2129  }
2130 );
2131 
2132 // CSWSP -----------------------------------------------------------------------
2133 static InstructionDefinition cswsp_rs2_uimm (
2134  ISA16_RV64IMACFD,
2135  "cswsp",
2136  (uint16_t) 0xc002,
2137  (uint16_t) 0xe003,
2138  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2139  {
2140 
2141 // -----------------------------------------------------------------------------
2142 
2143 // -----------------------------------------------------------------------------
2144 
2145 // -----------------------------------------------------------------------------
2146 etiss_uint8 rs2 = 0;
2147 static BitArrayRange R_rs2_0(6, 2);
2148 rs2 += R_rs2_0.read(ba) << 0;
2149 etiss_uint8 uimm = 0;
2150 static BitArrayRange R_uimm_6(8, 7);
2151 uimm += R_uimm_6.read(ba) << 6;
2152 static BitArrayRange R_uimm_2(12, 9);
2153 uimm += R_uimm_2.read(ba) << 2;
2154 
2155 // -----------------------------------------------------------------------------
2156 
2157  {
2158  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2159 
2160  cp.code() = std::string("//CSWSP\n");
2161 
2162 // -----------------------------------------------------------------------------
2163 { // block
2164 cp.code() += "{ // block\n";
2165 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
2166 cp.code() += "} // block\n";
2167 } // block
2168 { // block
2169 cp.code() += "{ // block\n";
2170 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
2171 cp.code() += "etiss_uint32 mem_val_0;\n";
2172 cp.code() += "mem_val_0 = (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
2173 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
2174 cp.code() += "if (cpu->exception) { // conditional\n";
2175 { // procedure
2176 cp.code() += "{ // procedure\n";
2177 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
2178 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
2179 cp.code() += "} // procedure\n";
2180 } // procedure
2181 cp.code() += "} // conditional\n";
2182 cp.code() += "} // block\n";
2183 } // block
2184 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2185 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2186 // -----------------------------------------------------------------------------
2187  cp.getAffectedRegisters().add("instructionPointer", 32);
2188  }
2189  {
2190  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
2191 
2192  cp.code() = std::string("//CSWSP\n");
2193 
2194 // -----------------------------------------------------------------------------
2195 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
2196 // -----------------------------------------------------------------------------
2197  }
2198 
2199  return true;
2200  },
2201  0,
2202  [] (BitArray & ba, Instruction & instr)
2203  {
2204 // -----------------------------------------------------------------------------
2205 etiss_uint8 rs2 = 0;
2206 static BitArrayRange R_rs2_0(6, 2);
2207 rs2 += R_rs2_0.read(ba) << 0;
2208 etiss_uint8 uimm = 0;
2209 static BitArrayRange R_uimm_6(8, 7);
2210 uimm += R_uimm_6.read(ba) << 6;
2211 static BitArrayRange R_uimm_2(12, 9);
2212 uimm += R_uimm_2.read(ba) << 2;
2213 
2214 // -----------------------------------------------------------------------------
2215 
2216  std::stringstream ss;
2217 // -----------------------------------------------------------------------------
2218 ss << "cswsp" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | uimm=" + std::to_string(uimm) + "]");
2219 // -----------------------------------------------------------------------------
2220  return ss.str();
2221  }
2222 );
2223 
2224 // DII -------------------------------------------------------------------------
2225 static InstructionDefinition dii_ (
2226  ISA16_RV64IMACFD,
2227  "dii",
2228  (uint16_t) 0x00,
2229  (uint16_t) 0xffff,
2230  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2231  {
2232 
2233 // -----------------------------------------------------------------------------
2234 
2235 // -----------------------------------------------------------------------------
2236 
2237 // -----------------------------------------------------------------------------
2238 
2239 // -----------------------------------------------------------------------------
2240 
2241  {
2242  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2243 
2244  cp.code() = std::string("//DII\n");
2245 
2246 // -----------------------------------------------------------------------------
2247 { // block
2248 cp.code() += "{ // block\n";
2249 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
2250 cp.code() += "} // block\n";
2251 } // block
2252 { // procedure
2253 cp.code() += "{ // procedure\n";
2254 cp.code() += "RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";
2255 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
2256 cp.code() += "} // procedure\n";
2257 } // procedure
2258 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2259 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2260 // -----------------------------------------------------------------------------
2261  cp.getAffectedRegisters().add("instructionPointer", 32);
2262  }
2263  {
2264  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
2265 
2266  cp.code() = std::string("//DII\n");
2267 
2268 // -----------------------------------------------------------------------------
2269 cp.code() += "return cpu->exception;\n";
2270 // -----------------------------------------------------------------------------
2271  }
2272 
2273  return true;
2274  },
2275  0,
2276  [] (BitArray & ba, Instruction & instr)
2277  {
2278 // -----------------------------------------------------------------------------
2279 
2280 // -----------------------------------------------------------------------------
2281 
2282  std::stringstream ss;
2283 // -----------------------------------------------------------------------------
2284 ss << "dii" << " # " << ba << (" []");
2285 // -----------------------------------------------------------------------------
2286  return ss.str();
2287  }
2288 );
ISA16_RV64IMACFD
etiss::instr::InstructionGroup ISA16_RV64IMACFD("ISA16_RV64IMACFD", 16)
cor_rs2_rd
static InstructionDefinition cor_rs2_rd(ISA16_RV64IMACFD, "cor",(uint16_t) 0x8c41,(uint16_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//COR\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] | *((RV64IMACFD*)cpu)->X["+std::to_string(rs2+8ULL)+"ULL];\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "cor"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | rd="+std::to_string(rd)+"]");return ss.str();})
cj_imm
static InstructionDefinition cj_imm(ISA16_RV64IMACFD, "cj",(uint16_t) 0xa001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_5(2, 2);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_1(5, 3);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_7(6, 6);imm+=R_imm_7.read(ba)<< 7;static BitArrayRange R_imm_6(7, 7);imm+=R_imm_6.read(ba)<< 6;static BitArrayRange R_imm_10(8, 8);imm+=R_imm_10.read(ba)<< 10;static BitArrayRange R_imm_8(10, 9);imm+=R_imm_8.read(ba)<< 8;static BitArrayRange R_imm_4(11, 11);imm+=R_imm_4.read(ba)<< 4;static BitArrayRange R_imm_11(12, 12);imm+=R_imm_11.read(ba)<< 11;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CJ\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CJ\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_5(2, 2);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_1(5, 3);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_7(6, 6);imm+=R_imm_7.read(ba)<< 7;static BitArrayRange R_imm_6(7, 7);imm+=R_imm_6.read(ba)<< 6;static BitArrayRange R_imm_10(8, 8);imm+=R_imm_10.read(ba)<< 10;static BitArrayRange R_imm_8(10, 9);imm+=R_imm_8.read(ba)<< 8;static BitArrayRange R_imm_4(11, 11);imm+=R_imm_4.read(ba)<< 4;static BitArrayRange R_imm_11(12, 12);imm+=R_imm_11.read(ba)<< 11;std::stringstream ss;ss<< "cj"<< " # "<< ba<<(" [imm="+std::to_string(imm)+"]");return ss.str();})
dii_
static InstructionDefinition dii_(ISA16_RV64IMACFD, "dii",(uint16_t) 0x00,(uint16_t) 0xffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//DII\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//DII\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "dii"<< " # "<< ba<<(" []");return ss.str();})
cjr_rs1
static InstructionDefinition cjr_rs1(ISA16_RV64IMACFD, "cjr",(uint16_t) 0x8002,(uint16_t) 0xf07f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CJR\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} if(rs1) { cp.code()+="cpu->nextPc = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] & -2LL;\n";} else { { cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2ULL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} } cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CJR\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "cjr"<< " # "<< ba<<(" [rs1="+std::to_string(rs1)+"]");return ss.str();})
csub_rs2_rd
static InstructionDefinition csub_rs2_rd(ISA16_RV64IMACFD, "csub",(uint16_t) 0x8c01,(uint16_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSUB\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] - *((RV64IMACFD*)cpu)->X["+std::to_string(rs2+8ULL)+"ULL];\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "csub"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | rd="+std::to_string(rd)+"]");return ss.str();})
clui_imm_rd
static InstructionDefinition clui_imm_rd(ISA16_RV64IMACFD, "clui",(uint16_t) 0x6001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint32 imm=0;static BitArrayRange R_imm_12(6, 2);imm+=R_imm_12.read(ba)<< 12;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_imm_17(12, 12);imm+=R_imm_17.read(ba)<< 17;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CLUI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if(imm==0LL) { { cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} } if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string(((etiss_int32)(((etiss_int32) imm)<<(14)) >>(14)))+"LL;\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CLUI\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint32 imm=0;static BitArrayRange R_imm_12(6, 2);imm+=R_imm_12.read(ba)<< 12;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_imm_17(12, 12);imm+=R_imm_17.read(ba)<< 17;std::stringstream ss;ss<< "clui"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rd="+std::to_string(rd)+"]");return ss.str();})
cli_imm_rd
static InstructionDefinition cli_imm_rd(ISA16_RV64IMACFD, "cli",(uint16_t) 0x4001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 imm=0;static BitArrayRange R_imm_0(6, 2);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_imm_5(12, 12);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CLI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string(((etiss_int8)(((etiss_int8) imm)<<(2)) >>(2)))+"LL;\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 imm=0;static BitArrayRange R_imm_0(6, 2);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_imm_5(12, 12);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "cli"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rd="+std::to_string(rd)+"]");return ss.str();})
cjalr_rs1
static InstructionDefinition cjalr_rs1(ISA16_RV64IMACFD, "cjalr",(uint16_t) 0x9002,(uint16_t) 0xf07f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CJALR\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 new_pc = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="*((RV64IMACFD*)cpu)->X[1ULL] = "+std::to_string(ic.current_address_+2ULL)+"ULL;\n";cp.code()+="cpu->nextPc = new_pc & -2LL;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CJALR\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "cjalr"<< " # "<< ba<<(" [rs1="+std::to_string(rs1)+"]");return ss.str();})
candi_imm_rs1
static InstructionDefinition candi_imm_rs1(ISA16_RV64IMACFD, "candi",(uint16_t) 0x8801,(uint16_t) 0xec03, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 imm=0;static BitArrayRange R_imm_0(6, 2);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_5(12, 12);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CANDI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] & "+std::to_string(((etiss_int8)(((etiss_int8) imm)<<(2)) >>(2)))+"LL;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 imm=0;static BitArrayRange R_imm_0(6, 2);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_5(12, 12);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "candi"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
cebreak_
static InstructionDefinition cebreak_(ISA16_RV64IMACFD, "cebreak",(uint16_t) 0x9002,(uint16_t) 0xffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CEBREAK\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 3LL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CEBREAK\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "cebreak"<< " # "<< ba<<(" []");return ss.str();})
cmv_rs2_rd
static InstructionDefinition cmv_rs2_rd(ISA16_RV64IMACFD, "cmv",(uint16_t) 0x8002,(uint16_t) 0xf003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CMV\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "cmv"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | rd="+std::to_string(rd)+"]");return ss.str();})
clwsp_uimm_rd
static InstructionDefinition clwsp_uimm_rd(ISA16_RV64IMACFD, "clwsp",(uint16_t) 0x4002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(3, 2);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 4);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_uimm_5(12, 12);uimm+=R_uimm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CLWSP\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if(rd % 32ULL) { { cp.code()+="{ // block\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, *((RV64IMACFD*)cpu)->X[2ULL] + "+std::to_string(uimm)+"ULL, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int32 res = mem_val_0;\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(res);\n";cp.code()+="} // block\n";} } else { { cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2ULL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CLWSP\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(3, 2);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 4);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_uimm_5(12, 12);uimm+=R_uimm_5.read(ba)<< 5;std::stringstream ss;ss<< "clwsp"<< " # "<< ba<<(" [uimm="+std::to_string(uimm)+" | rd="+std::to_string(rd)+"]");return ss.str();})
cbeqz_imm_rs1
static InstructionDefinition cbeqz_imm_rs1(ISA16_RV64IMACFD, "cbeqz",(uint16_t) 0xc001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_5(2, 2);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_1(4, 3);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_6(6, 5);imm+=R_imm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_3(11, 10);imm+=R_imm_3.read(ba)<< 3;static BitArrayRange R_imm_8(12, 12);imm+=R_imm_8.read(ba)<< 8;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CBEQZ\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] == 0LL) { // conditional\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(7)) >>(7)))+"LL;\n";cp.code()+="} // conditional\n";cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CBEQZ\n");cp.code()+="if (cpu->nextPc != "+std::to_string(ic.current_address_+2)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_5(2, 2);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_1(4, 3);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_6(6, 5);imm+=R_imm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_3(11, 10);imm+=R_imm_3.read(ba)<< 3;static BitArrayRange R_imm_8(12, 12);imm+=R_imm_8.read(ba)<< 8;std::stringstream ss;ss<< "cbeqz"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
cswsp_rs2_uimm
static InstructionDefinition cswsp_rs2_uimm(ISA16_RV64IMACFD, "cswsp",(uint16_t) 0xc002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(8, 7);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(12, 9);uimm+=R_uimm_2.read(ba)<< 2;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSWSP\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CSWSP\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(8, 7);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(12, 9);uimm+=R_uimm_2.read(ba)<< 2;std::stringstream ss;ss<< "cswsp"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | uimm="+std::to_string(uimm)+"]");return ss.str();})
cslli_nzuimm_rs1
static InstructionDefinition cslli_nzuimm_rs1(ISA16_RV64IMACFD, "cslli",(uint16_t) 0x02,(uint16_t) 0xf003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 nzuimm=0;static BitArrayRange R_nzuimm_0(6, 2);nzuimm+=R_nzuimm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSLLI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} if(nzuimm) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] << "+std::to_string(nzuimm)+"ULL;\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 nzuimm=0;static BitArrayRange R_nzuimm_0(6, 2);nzuimm+=R_nzuimm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "cslli"<< " # "<< ba<<(" [nzuimm="+std::to_string(nzuimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
csrai_shamt_rs1
static InstructionDefinition csrai_shamt_rs1(ISA16_RV64IMACFD, "csrai",(uint16_t) 0x8401,(uint16_t) 0xfc03, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(6, 2);shamt+=R_shamt_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRAI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if(shamt) { { cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] = ((etiss_int64)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL])) >> "+std::to_string(shamt)+"ULL;\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(6, 2);shamt+=R_shamt_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "csrai"<< " # "<< ba<<(" [shamt="+std::to_string(shamt)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
caddi4spn_rd_imm
static InstructionDefinition caddi4spn_rd_imm(ISA16_RV64IMACFD, "caddi4spn",(uint16_t) 0x00,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_3(5, 5);imm+=R_imm_3.read(ba)<< 3;static BitArrayRange R_imm_2(6, 6);imm+=R_imm_2.read(ba)<< 2;static BitArrayRange R_imm_6(10, 7);imm+=R_imm_6.read(ba)<< 6;static BitArrayRange R_imm_4(12, 11);imm+=R_imm_4.read(ba)<< 4;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CADDI4SPN\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} if(imm) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = *((RV64IMACFD*)cpu)->X[2ULL] + "+std::to_string(imm)+"ULL;\n";} else { { cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} } cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CADDI4SPN\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_3(5, 5);imm+=R_imm_3.read(ba)<< 3;static BitArrayRange R_imm_2(6, 6);imm+=R_imm_2.read(ba)<< 2;static BitArrayRange R_imm_6(10, 7);imm+=R_imm_6.read(ba)<< 6;static BitArrayRange R_imm_4(12, 11);imm+=R_imm_4.read(ba)<< 4;std::stringstream ss;ss<< "caddi4spn"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | imm="+std::to_string(imm)+"]");return ss.str();})
cnop_nzimm
static InstructionDefinition cnop_nzimm(ISA16_RV64IMACFD, "cnop",(uint16_t) 0x01,(uint16_t) 0xef83, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 nzimm=0;static BitArrayRange R_nzimm_0(6, 2);nzimm+=R_nzimm_0.read(ba)<< 0;static BitArrayRange R_nzimm_5(12, 12);nzimm+=R_nzimm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CNOP\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 nzimm=0;static BitArrayRange R_nzimm_0(6, 2);nzimm+=R_nzimm_0.read(ba)<< 0;static BitArrayRange R_nzimm_5(12, 12);nzimm+=R_nzimm_5.read(ba)<< 5;std::stringstream ss;ss<< "cnop"<< " # "<< ba<<(" [nzimm="+std::to_string(nzimm)+"]");return ss.str();})
cxor_rs2_rd
static InstructionDefinition cxor_rs2_rd(ISA16_RV64IMACFD, "cxor",(uint16_t) 0x8c21,(uint16_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CXOR\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] ^ *((RV64IMACFD*)cpu)->X["+std::to_string(rs2+8ULL)+"ULL];\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "cxor"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | rd="+std::to_string(rd)+"]");return ss.str();})
cbnez_imm_rs1
static InstructionDefinition cbnez_imm_rs1(ISA16_RV64IMACFD, "cbnez",(uint16_t) 0xe001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_5(2, 2);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_1(4, 3);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_6(6, 5);imm+=R_imm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_3(11, 10);imm+=R_imm_3.read(ba)<< 3;static BitArrayRange R_imm_8(12, 12);imm+=R_imm_8.read(ba)<< 8;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CBNEZ\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} cp.code()+="if (*((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(7)) >>(7)))+"LL;\n";cp.code()+="} // conditional\n";cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CBNEZ\n");cp.code()+="if (cpu->nextPc != "+std::to_string(ic.current_address_+2)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_5(2, 2);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_1(4, 3);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_6(6, 5);imm+=R_imm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_3(11, 10);imm+=R_imm_3.read(ba)<< 3;static BitArrayRange R_imm_8(12, 12);imm+=R_imm_8.read(ba)<< 8;std::stringstream ss;ss<< "cbnez"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
csw_rs2_uimm_rs1
static InstructionDefinition csw_rs2_uimm_rs1(ISA16_RV64IMACFD, "csw",(uint16_t) 0xc000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(5, 5);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 6);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2+8ULL)+"ULL]);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CSW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(5, 5);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 6);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;std::stringstream ss;ss<< "csw"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | uimm="+std::to_string(uimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
caddi_imm_rs1
static InstructionDefinition caddi_imm_rs1(ISA16_RV64IMACFD, "caddi",(uint16_t) 0x01,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 imm=0;static BitArrayRange R_imm_0(6, 2);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_5(12, 12);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CADDI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} if((rs1 % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int8)(((etiss_int8) imm)<<(2)) >>(2)))+"LL;\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 imm=0;static BitArrayRange R_imm_0(6, 2);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_5(12, 12);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "caddi"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
__reserved_cmv_
static InstructionDefinition __reserved_cmv_(ISA16_RV64IMACFD, "__reserved_cmv",(uint16_t) 0x8002,(uint16_t) 0xffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//__reserved_cmv\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2ULL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//__reserved_cmv\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "__reserved_cmv"<< " # "<< ba<<(" []");return ss.str();})
csrli_shamt_rs1
static InstructionDefinition csrli_shamt_rs1(ISA16_RV64IMACFD, "csrli",(uint16_t) 0x8001,(uint16_t) 0xfc03, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(6, 2);shamt+=R_shamt_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRLI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] >> "+std::to_string(shamt)+"ULL;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(6, 2);shamt+=R_shamt_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "csrli"<< " # "<< ba<<(" [shamt="+std::to_string(shamt)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
__reserved_clui_rd
static InstructionDefinition __reserved_clui_rd(ISA16_RV64IMACFD, "__reserved_clui",(uint16_t) 0x6001,(uint16_t) 0xf07f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//__reserved_clui\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//__reserved_clui\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "__reserved_clui"<< " # "<< ba<<(" [rd="+std::to_string(rd)+"]");return ss.str();})
caddi16sp_nzimm
static InstructionDefinition caddi16sp_nzimm(ISA16_RV64IMACFD, "caddi16sp",(uint16_t) 0x6101,(uint16_t) 0xef83, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 nzimm=0;static BitArrayRange R_nzimm_5(2, 2);nzimm+=R_nzimm_5.read(ba)<< 5;static BitArrayRange R_nzimm_7(4, 3);nzimm+=R_nzimm_7.read(ba)<< 7;static BitArrayRange R_nzimm_6(5, 5);nzimm+=R_nzimm_6.read(ba)<< 6;static BitArrayRange R_nzimm_4(6, 6);nzimm+=R_nzimm_4.read(ba)<< 4;static BitArrayRange R_nzimm_9(12, 12);nzimm+=R_nzimm_9.read(ba)<< 9;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CADDI16SP\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} if(nzimm) { cp.code()+="*((RV64IMACFD*)cpu)->X[2ULL] = *((RV64IMACFD*)cpu)->X[2ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) nzimm)<<(6)) >>(6)))+"LL;\n";} else { { cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} } cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CADDI16SP\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 nzimm=0;static BitArrayRange R_nzimm_5(2, 2);nzimm+=R_nzimm_5.read(ba)<< 5;static BitArrayRange R_nzimm_7(4, 3);nzimm+=R_nzimm_7.read(ba)<< 7;static BitArrayRange R_nzimm_6(5, 5);nzimm+=R_nzimm_6.read(ba)<< 6;static BitArrayRange R_nzimm_4(6, 6);nzimm+=R_nzimm_4.read(ba)<< 4;static BitArrayRange R_nzimm_9(12, 12);nzimm+=R_nzimm_9.read(ba)<< 9;std::stringstream ss;ss<< "caddi16sp"<< " # "<< ba<<(" [nzimm="+std::to_string(nzimm)+"]");return ss.str();})
cadd_rs2_rd
static InstructionDefinition cadd_rs2_rd(ISA16_RV64IMACFD, "cadd",(uint16_t) 0x9002,(uint16_t) 0xf003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CADD\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] + *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "cadd"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | rd="+std::to_string(rd)+"]");return ss.str();})
cand_rs2_rd
static InstructionDefinition cand_rs2_rd(ISA16_RV64IMACFD, "cand",(uint16_t) 0x8c61,(uint16_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CAND\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = *((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] & *((RV64IMACFD*)cpu)->X["+std::to_string(rs2+8ULL)+"ULL];\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "cand"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | rd="+std::to_string(rd)+"]");return ss.str();})
clw_rd_uimm_rs1
static InstructionDefinition clw_rd_uimm_rs1(ISA16_RV64IMACFD, "clw",(uint16_t) 0x4000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(5, 5);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 6);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CLW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 load_address = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = (etiss_int32)(mem_val_0);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CLW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(5, 5);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 6);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;std::stringstream ss;ss<< "clw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | uimm="+std::to_string(uimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
uint16_t
static __inline__ uint16_t
Definition: arm_mve.h:315
etiss_int16
int16_t etiss_int16
Definition: types.h:89
etiss_uint32
uint32_t etiss_uint32
Definition: types.h:93
etiss_int8
int8_t etiss_int8
Definition: types.h:86
etiss_uint8
uint8_t etiss_uint8
Definition: types.h:87
etiss_int32
int32_t etiss_int32
Definition: types.h:92
etiss_uint16
uint16_t etiss_uint16
Definition: types.h:90
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:386
etiss::CodePart::APPENDEDRETURNINGREQUIRED
@ APPENDEDRETURNINGREQUIRED
Definition: CodePart.h:402
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition: Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition: Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
Generated on Thu Jul 4 2024 12:41:52 for ETISS 0.8.0 by doxygen 1.9.1