ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
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RV64IMACFD_RV32DCInstr.cpp
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1
8#include "RV64IMACFDArch.h"
9#include "RV64IMACFDFuncs.h"
10
11using namespace etiss;
12using namespace etiss::instr;
13
14
15// CFLD ------------------------------------------------------------------------
16static InstructionDefinition cfld_rd_uimm_rs1 (
17 ISA16_RV64IMACFD,
18 "cfld",
19 (uint16_t) 0x2000,
20 (uint16_t) 0xe003,
21 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22 {
23
24// -----------------------------------------------------------------------------
25
26// -----------------------------------------------------------------------------
27
28// -----------------------------------------------------------------------------
29etiss_uint8 rd = 0;
30static BitArrayRange R_rd_0(4, 2);
31rd += R_rd_0.read(ba) << 0;
32etiss_uint8 uimm = 0;
33static BitArrayRange R_uimm_6(6, 5);
34uimm += R_uimm_6.read(ba) << 6;
35etiss_uint8 rs1 = 0;
36static BitArrayRange R_rs1_0(9, 7);
37rs1 += R_rs1_0.read(ba) << 0;
38static BitArrayRange R_uimm_3(12, 10);
39uimm += R_uimm_3.read(ba) << 3;
40
41// -----------------------------------------------------------------------------
42
43 {
44 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
45
46 cp.code() = std::string("//CFLD\n");
47
48// -----------------------------------------------------------------------------
49cp.code() += "etiss_coverage_count(1, 144);\n";
50{ // block
51cp.code() += "etiss_coverage_count(1, 1169);\n";
52cp.code() += "{ // block\n";
53cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
54cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
55cp.code() += "} // block\n";
56} // block
57{ // block
58cp.code() += "etiss_coverage_count(1, 6281);\n";
59cp.code() += "{ // block\n";
60cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
61cp.code() += "etiss_coverage_count(7, 6248, 6247, 6245, 6244, 6242, 6243, 6246);\n";
62cp.code() += "etiss_uint64 mem_val_0;\n";
63cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
64cp.code() += "if (cpu->exception) { // conditional\n";
65{ // procedure
66cp.code() += "{ // procedure\n";
67cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
68cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
69cp.code() += "} // procedure\n";
70} // procedure
71cp.code() += "} // conditional\n";
72cp.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
73cp.code() += "etiss_coverage_count(4, 6255, 6254, 6252, 6251);\n";
74cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd + 8ULL) + "ULL] = res;\n";
75cp.code() += "etiss_coverage_count(6, 6266, 6264, 6263, 6261, 6262, 6265);\n";
76cp.code() += "} // block\n";
77} // block
78cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
79cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
80// -----------------------------------------------------------------------------
81 cp.getAffectedRegisters().add("instructionPointer", 32);
82 }
83 {
84 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
85
86 cp.code() = std::string("//CFLD\n");
87
88// -----------------------------------------------------------------------------
89cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
90// -----------------------------------------------------------------------------
91 }
92
93 return true;
94 },
95 0,
96 [] (BitArray & ba, Instruction & instr)
97 {
98// -----------------------------------------------------------------------------
99etiss_uint8 rd = 0;
100static BitArrayRange R_rd_0(4, 2);
101rd += R_rd_0.read(ba) << 0;
102etiss_uint8 uimm = 0;
103static BitArrayRange R_uimm_6(6, 5);
104uimm += R_uimm_6.read(ba) << 6;
105etiss_uint8 rs1 = 0;
106static BitArrayRange R_rs1_0(9, 7);
107rs1 += R_rs1_0.read(ba) << 0;
108static BitArrayRange R_uimm_3(12, 10);
109uimm += R_uimm_3.read(ba) << 3;
110
111// -----------------------------------------------------------------------------
112
113 std::stringstream ss;
114// -----------------------------------------------------------------------------
115ss << "cfld" << " # " << ba << (" [rd=" + std::to_string(rd) + " | uimm=" + std::to_string(uimm) + " | rs1=" + std::to_string(rs1) + "]");
116// -----------------------------------------------------------------------------
117 return ss.str();
118 }
119);
120
121// CFSD ------------------------------------------------------------------------
122static InstructionDefinition cfsd_rs2_uimm_rs1 (
123 ISA16_RV64IMACFD,
124 "cfsd",
125 (uint16_t) 0xa000,
126 (uint16_t) 0xe003,
127 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
128 {
129
130// -----------------------------------------------------------------------------
131
132// -----------------------------------------------------------------------------
133
134// -----------------------------------------------------------------------------
135etiss_uint8 rs2 = 0;
136static BitArrayRange R_rs2_0(4, 2);
137rs2 += R_rs2_0.read(ba) << 0;
138etiss_uint8 uimm = 0;
139static BitArrayRange R_uimm_6(6, 5);
140uimm += R_uimm_6.read(ba) << 6;
141etiss_uint8 rs1 = 0;
142static BitArrayRange R_rs1_0(9, 7);
143rs1 += R_rs1_0.read(ba) << 0;
144static BitArrayRange R_uimm_3(12, 10);
145uimm += R_uimm_3.read(ba) << 3;
146
147// -----------------------------------------------------------------------------
148
149 {
150 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
151
152 cp.code() = std::string("//CFSD\n");
153
154// -----------------------------------------------------------------------------
155cp.code() += "etiss_coverage_count(1, 145);\n";
156{ // block
157cp.code() += "etiss_coverage_count(1, 1169);\n";
158cp.code() += "{ // block\n";
159cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
160cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
161cp.code() += "} // block\n";
162} // block
163{ // block
164cp.code() += "etiss_coverage_count(1, 6302);\n";
165cp.code() += "{ // block\n";
166cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
167cp.code() += "etiss_coverage_count(7, 6290, 6289, 6287, 6286, 6284, 6285, 6288);\n";
168cp.code() += "etiss_uint64 mem_val_0;\n";
169cp.code() += "mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2 + 8ULL) + "ULL]);\n";
170cp.code() += "etiss_coverage_count(8, 6301, 6293, 6292, 6300, 6298, 6297, 6295, 6296);\n";
171cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
172cp.code() += "if (cpu->exception) { // conditional\n";
173{ // procedure
174cp.code() += "{ // procedure\n";
175cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
176cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
177cp.code() += "} // procedure\n";
178} // procedure
179cp.code() += "} // conditional\n";
180cp.code() += "} // block\n";
181} // block
182cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
183cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
184// -----------------------------------------------------------------------------
185 cp.getAffectedRegisters().add("instructionPointer", 32);
186 }
187 {
188 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
189
190 cp.code() = std::string("//CFSD\n");
191
192// -----------------------------------------------------------------------------
193cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
194// -----------------------------------------------------------------------------
195 }
196
197 return true;
198 },
199 0,
200 [] (BitArray & ba, Instruction & instr)
201 {
202// -----------------------------------------------------------------------------
203etiss_uint8 rs2 = 0;
204static BitArrayRange R_rs2_0(4, 2);
205rs2 += R_rs2_0.read(ba) << 0;
206etiss_uint8 uimm = 0;
207static BitArrayRange R_uimm_6(6, 5);
208uimm += R_uimm_6.read(ba) << 6;
209etiss_uint8 rs1 = 0;
210static BitArrayRange R_rs1_0(9, 7);
211rs1 += R_rs1_0.read(ba) << 0;
212static BitArrayRange R_uimm_3(12, 10);
213uimm += R_uimm_3.read(ba) << 3;
214
215// -----------------------------------------------------------------------------
216
217 std::stringstream ss;
218// -----------------------------------------------------------------------------
219ss << "cfsd" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | uimm=" + std::to_string(uimm) + " | rs1=" + std::to_string(rs1) + "]");
220// -----------------------------------------------------------------------------
221 return ss.str();
222 }
223);
224
225// CFLDSP ----------------------------------------------------------------------
226static InstructionDefinition cfldsp_uimm_rd (
227 ISA16_RV64IMACFD,
228 "cfldsp",
229 (uint16_t) 0x2002,
230 (uint16_t) 0xe003,
231 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
232 {
233
234// -----------------------------------------------------------------------------
235
236// -----------------------------------------------------------------------------
237
238// -----------------------------------------------------------------------------
239etiss_uint16 uimm = 0;
240static BitArrayRange R_uimm_6(4, 2);
241uimm += R_uimm_6.read(ba) << 6;
242static BitArrayRange R_uimm_3(6, 5);
243uimm += R_uimm_3.read(ba) << 3;
244etiss_uint8 rd = 0;
245static BitArrayRange R_rd_0(11, 7);
246rd += R_rd_0.read(ba) << 0;
247static BitArrayRange R_uimm_5(12, 12);
248uimm += R_uimm_5.read(ba) << 5;
249
250// -----------------------------------------------------------------------------
251
252 {
253 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
254
255 cp.code() = std::string("//CFLDSP\n");
256
257// -----------------------------------------------------------------------------
258cp.code() += "etiss_coverage_count(1, 146);\n";
259{ // block
260cp.code() += "etiss_coverage_count(1, 1169);\n";
261cp.code() += "{ // block\n";
262cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
263cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
264cp.code() += "} // block\n";
265} // block
266{ // block
267cp.code() += "etiss_coverage_count(1, 6338);\n";
268cp.code() += "{ // block\n";
269cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
270cp.code() += "etiss_coverage_count(5, 6309, 6308, 6306, 6305, 6307);\n";
271cp.code() += "etiss_uint64 mem_val_0;\n";
272cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
273cp.code() += "if (cpu->exception) { // conditional\n";
274{ // procedure
275cp.code() += "{ // procedure\n";
276cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
277cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
278cp.code() += "} // procedure\n";
279} // procedure
280cp.code() += "} // conditional\n";
281cp.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
282cp.code() += "etiss_coverage_count(4, 6316, 6315, 6313, 6312);\n";
283cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
284cp.code() += "etiss_coverage_count(4, 6325, 6323, 6322, 6324);\n";
285cp.code() += "} // block\n";
286} // block
287cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
288cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
289// -----------------------------------------------------------------------------
290 cp.getAffectedRegisters().add("instructionPointer", 32);
291 }
292 {
293 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
294
295 cp.code() = std::string("//CFLDSP\n");
296
297// -----------------------------------------------------------------------------
298cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
299// -----------------------------------------------------------------------------
300 }
301
302 return true;
303 },
304 0,
305 [] (BitArray & ba, Instruction & instr)
306 {
307// -----------------------------------------------------------------------------
308etiss_uint16 uimm = 0;
309static BitArrayRange R_uimm_6(4, 2);
310uimm += R_uimm_6.read(ba) << 6;
311static BitArrayRange R_uimm_3(6, 5);
312uimm += R_uimm_3.read(ba) << 3;
313etiss_uint8 rd = 0;
314static BitArrayRange R_rd_0(11, 7);
315rd += R_rd_0.read(ba) << 0;
316static BitArrayRange R_uimm_5(12, 12);
317uimm += R_uimm_5.read(ba) << 5;
318
319// -----------------------------------------------------------------------------
320
321 std::stringstream ss;
322// -----------------------------------------------------------------------------
323ss << "cfldsp" << " # " << ba << (" [uimm=" + std::to_string(uimm) + " | rd=" + std::to_string(rd) + "]");
324// -----------------------------------------------------------------------------
325 return ss.str();
326 }
327);
328
329// CFSDSP ----------------------------------------------------------------------
330static InstructionDefinition cfsdsp_rs2_uimm (
331 ISA16_RV64IMACFD,
332 "cfsdsp",
333 (uint16_t) 0xa002,
334 (uint16_t) 0xe003,
335 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
336 {
337
338// -----------------------------------------------------------------------------
339
340// -----------------------------------------------------------------------------
341
342// -----------------------------------------------------------------------------
343etiss_uint8 rs2 = 0;
344static BitArrayRange R_rs2_0(6, 2);
345rs2 += R_rs2_0.read(ba) << 0;
346etiss_uint16 uimm = 0;
347static BitArrayRange R_uimm_6(9, 7);
348uimm += R_uimm_6.read(ba) << 6;
349static BitArrayRange R_uimm_3(12, 10);
350uimm += R_uimm_3.read(ba) << 3;
351
352// -----------------------------------------------------------------------------
353
354 {
355 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
356
357 cp.code() = std::string("//CFSDSP\n");
358
359// -----------------------------------------------------------------------------
360cp.code() += "etiss_coverage_count(1, 147);\n";
361{ // block
362cp.code() += "etiss_coverage_count(1, 1169);\n";
363cp.code() += "{ // block\n";
364cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
365cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
366cp.code() += "} // block\n";
367} // block
368{ // block
369cp.code() += "etiss_coverage_count(1, 6355);\n";
370cp.code() += "{ // block\n";
371cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
372cp.code() += "etiss_coverage_count(5, 6345, 6344, 6342, 6341, 6343);\n";
373cp.code() += "etiss_uint64 mem_val_0;\n";
374cp.code() += "mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
375cp.code() += "etiss_coverage_count(6, 6354, 6348, 6347, 6353, 6351, 6350);\n";
376cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
377cp.code() += "if (cpu->exception) { // conditional\n";
378{ // procedure
379cp.code() += "{ // procedure\n";
380cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
381cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
382cp.code() += "} // procedure\n";
383} // procedure
384cp.code() += "} // conditional\n";
385cp.code() += "} // block\n";
386} // block
387cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
388cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
389// -----------------------------------------------------------------------------
390 cp.getAffectedRegisters().add("instructionPointer", 32);
391 }
392 {
393 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
394
395 cp.code() = std::string("//CFSDSP\n");
396
397// -----------------------------------------------------------------------------
398cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
399// -----------------------------------------------------------------------------
400 }
401
402 return true;
403 },
404 0,
405 [] (BitArray & ba, Instruction & instr)
406 {
407// -----------------------------------------------------------------------------
408etiss_uint8 rs2 = 0;
409static BitArrayRange R_rs2_0(6, 2);
410rs2 += R_rs2_0.read(ba) << 0;
411etiss_uint16 uimm = 0;
412static BitArrayRange R_uimm_6(9, 7);
413uimm += R_uimm_6.read(ba) << 6;
414static BitArrayRange R_uimm_3(12, 10);
415uimm += R_uimm_3.read(ba) << 3;
416
417// -----------------------------------------------------------------------------
418
419 std::stringstream ss;
420// -----------------------------------------------------------------------------
421ss << "cfsdsp" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | uimm=" + std::to_string(uimm) + "]");
422// -----------------------------------------------------------------------------
423 return ss.str();
424 }
425);
ISA16_RV64IMACFD
etiss::instr::InstructionGroup ISA16_RV64IMACFD("ISA16_RV64IMACFD", 16)
cfsdsp_rs2_uimm
static InstructionDefinition cfsdsp_rs2_uimm(ISA16_RV64IMACFD, "cfsdsp",(uint16_t) 0xa002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint16 uimm=0;static BitArrayRange R_uimm_6(9, 7);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CFSDSP\n");cp.code()+="etiss_coverage_count(1, 147);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6355);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 6345, 6344, 6342, 6341, 6343);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(6, 6354, 6348, 6347, 6353, 6351, 6350);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CFSDSP\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint16 uimm=0;static BitArrayRange R_uimm_6(9, 7);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;std::stringstream ss;ss<< "cfsdsp"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | uimm="+std::to_string(uimm)+"]");return ss.str();})
cfld_rd_uimm_rs1
static InstructionDefinition cfld_rd_uimm_rs1(ISA16_RV64IMACFD, "cfld",(uint16_t) 0x2000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(6, 5);uimm+=R_uimm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CFLD\n");cp.code()+="etiss_coverage_count(1, 144);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6281);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(7, 6248, 6247, 6245, 6244, 6242, 6243, 6246);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 6255, 6254, 6252, 6251);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd+8ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(6, 6266, 6264, 6263, 6261, 6262, 6265);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CFLD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(6, 5);uimm+=R_uimm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;std::stringstream ss;ss<< "cfld"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | uimm="+std::to_string(uimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
cfldsp_uimm_rd
static InstructionDefinition cfldsp_uimm_rd(ISA16_RV64IMACFD, "cfldsp",(uint16_t) 0x2002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 uimm=0;static BitArrayRange R_uimm_6(4, 2);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_3(6, 5);uimm+=R_uimm_3.read(ba)<< 3;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_uimm_5(12, 12);uimm+=R_uimm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CFLDSP\n");cp.code()+="etiss_coverage_count(1, 146);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6338);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 6309, 6308, 6306, 6305, 6307);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 6316, 6315, 6313, 6312);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 6325, 6323, 6322, 6324);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CFLDSP\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 uimm=0;static BitArrayRange R_uimm_6(4, 2);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_3(6, 5);uimm+=R_uimm_3.read(ba)<< 3;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_uimm_5(12, 12);uimm+=R_uimm_5.read(ba)<< 5;std::stringstream ss;ss<< "cfldsp"<< " # "<< ba<<(" [uimm="+std::to_string(uimm)+" | rd="+std::to_string(rd)+"]");return ss.str();})
cfsd_rs2_uimm_rs1
static InstructionDefinition cfsd_rs2_uimm_rs1(ISA16_RV64IMACFD, "cfsd",(uint16_t) 0xa000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(6, 5);uimm+=R_uimm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CFSD\n");cp.code()+="etiss_coverage_count(1, 145);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6302);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(7, 6290, 6289, 6287, 6286, 6284, 6285, 6288);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2+8ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(8, 6301, 6293, 6292, 6300, 6298, 6297, 6295, 6296);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CFSD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(6, 5);uimm+=R_uimm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;std::stringstream ss;ss<< "cfsd"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | uimm="+std::to_string(uimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
etiss_uint8
uint8_t etiss_uint8
Definition types.h:87
etiss_uint16
uint16_t etiss_uint16
Definition types.h:90
etiss::CodePart
Contains a small code snipped.
Definition CodePart.h:386
etiss::CodePart::APPENDEDRETURNINGREQUIRED
@ APPENDEDRETURNINGREQUIRED
Definition CodePart.h:402
etiss::CodePart::code
std::string & code()
Definition CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition Benchmark.h:53
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