ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV64IMACFD_RV32DCInstr.cpp
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1 
8 #include "RV64IMACFDArch.h"
9 #include "RV64IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // CFLD ------------------------------------------------------------------------
16 static InstructionDefinition cfld_rd_uimm_rs1 (
17  ISA16_RV64IMACFD,
18  "cfld",
19  (uint16_t) 0x2000,
20  (uint16_t) 0xe003,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 etiss_uint8 rd = 0;
30 static BitArrayRange R_rd_0(4, 2);
31 rd += R_rd_0.read(ba) << 0;
32 etiss_uint8 uimm = 0;
33 static BitArrayRange R_uimm_6(6, 5);
34 uimm += R_uimm_6.read(ba) << 6;
35 etiss_uint8 rs1 = 0;
36 static BitArrayRange R_rs1_0(9, 7);
37 rs1 += R_rs1_0.read(ba) << 0;
38 static BitArrayRange R_uimm_3(12, 10);
39 uimm += R_uimm_3.read(ba) << 3;
40 
41 // -----------------------------------------------------------------------------
42 
43  {
44  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
45 
46  cp.code() = std::string("//CFLD\n");
47 
48 // -----------------------------------------------------------------------------
49 cp.code() += "etiss_coverage_count(1, 144);\n";
50 { // block
51 cp.code() += "etiss_coverage_count(1, 1169);\n";
52 cp.code() += "{ // block\n";
53 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
54 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
55 cp.code() += "} // block\n";
56 } // block
57 { // block
58 cp.code() += "etiss_coverage_count(1, 6281);\n";
59 cp.code() += "{ // block\n";
60 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
61 cp.code() += "etiss_coverage_count(7, 6248, 6247, 6245, 6244, 6242, 6243, 6246);\n";
62 cp.code() += "etiss_uint64 mem_val_0;\n";
63 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
64 cp.code() += "if (cpu->exception) { // conditional\n";
65 { // procedure
66 cp.code() += "{ // procedure\n";
67 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
68 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
69 cp.code() += "} // procedure\n";
70 } // procedure
71 cp.code() += "} // conditional\n";
72 cp.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
73 cp.code() += "etiss_coverage_count(4, 6255, 6254, 6252, 6251);\n";
74 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd + 8ULL) + "ULL] = res;\n";
75 cp.code() += "etiss_coverage_count(6, 6266, 6264, 6263, 6261, 6262, 6265);\n";
76 cp.code() += "} // block\n";
77 } // block
78 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
79 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
80 // -----------------------------------------------------------------------------
81  cp.getAffectedRegisters().add("instructionPointer", 32);
82  }
83  {
84  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
85 
86  cp.code() = std::string("//CFLD\n");
87 
88 // -----------------------------------------------------------------------------
89 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
90 // -----------------------------------------------------------------------------
91  }
92 
93  return true;
94  },
95  0,
96  [] (BitArray & ba, Instruction & instr)
97  {
98 // -----------------------------------------------------------------------------
99 etiss_uint8 rd = 0;
100 static BitArrayRange R_rd_0(4, 2);
101 rd += R_rd_0.read(ba) << 0;
102 etiss_uint8 uimm = 0;
103 static BitArrayRange R_uimm_6(6, 5);
104 uimm += R_uimm_6.read(ba) << 6;
105 etiss_uint8 rs1 = 0;
106 static BitArrayRange R_rs1_0(9, 7);
107 rs1 += R_rs1_0.read(ba) << 0;
108 static BitArrayRange R_uimm_3(12, 10);
109 uimm += R_uimm_3.read(ba) << 3;
110 
111 // -----------------------------------------------------------------------------
112 
113  std::stringstream ss;
114 // -----------------------------------------------------------------------------
115 ss << "cfld" << " # " << ba << (" [rd=" + std::to_string(rd) + " | uimm=" + std::to_string(uimm) + " | rs1=" + std::to_string(rs1) + "]");
116 // -----------------------------------------------------------------------------
117  return ss.str();
118  }
119 );
120 
121 // CFSD ------------------------------------------------------------------------
122 static InstructionDefinition cfsd_rs2_uimm_rs1 (
123  ISA16_RV64IMACFD,
124  "cfsd",
125  (uint16_t) 0xa000,
126  (uint16_t) 0xe003,
127  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
128  {
129 
130 // -----------------------------------------------------------------------------
131 
132 // -----------------------------------------------------------------------------
133 
134 // -----------------------------------------------------------------------------
135 etiss_uint8 rs2 = 0;
136 static BitArrayRange R_rs2_0(4, 2);
137 rs2 += R_rs2_0.read(ba) << 0;
138 etiss_uint8 uimm = 0;
139 static BitArrayRange R_uimm_6(6, 5);
140 uimm += R_uimm_6.read(ba) << 6;
141 etiss_uint8 rs1 = 0;
142 static BitArrayRange R_rs1_0(9, 7);
143 rs1 += R_rs1_0.read(ba) << 0;
144 static BitArrayRange R_uimm_3(12, 10);
145 uimm += R_uimm_3.read(ba) << 3;
146 
147 // -----------------------------------------------------------------------------
148 
149  {
150  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
151 
152  cp.code() = std::string("//CFSD\n");
153 
154 // -----------------------------------------------------------------------------
155 cp.code() += "etiss_coverage_count(1, 145);\n";
156 { // block
157 cp.code() += "etiss_coverage_count(1, 1169);\n";
158 cp.code() += "{ // block\n";
159 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
160 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
161 cp.code() += "} // block\n";
162 } // block
163 { // block
164 cp.code() += "etiss_coverage_count(1, 6302);\n";
165 cp.code() += "{ // block\n";
166 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
167 cp.code() += "etiss_coverage_count(7, 6290, 6289, 6287, 6286, 6284, 6285, 6288);\n";
168 cp.code() += "etiss_uint64 mem_val_0;\n";
169 cp.code() += "mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2 + 8ULL) + "ULL]);\n";
170 cp.code() += "etiss_coverage_count(8, 6301, 6293, 6292, 6300, 6298, 6297, 6295, 6296);\n";
171 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
172 cp.code() += "if (cpu->exception) { // conditional\n";
173 { // procedure
174 cp.code() += "{ // procedure\n";
175 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
176 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
177 cp.code() += "} // procedure\n";
178 } // procedure
179 cp.code() += "} // conditional\n";
180 cp.code() += "} // block\n";
181 } // block
182 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
183 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
184 // -----------------------------------------------------------------------------
185  cp.getAffectedRegisters().add("instructionPointer", 32);
186  }
187  {
188  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
189 
190  cp.code() = std::string("//CFSD\n");
191 
192 // -----------------------------------------------------------------------------
193 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
194 // -----------------------------------------------------------------------------
195  }
196 
197  return true;
198  },
199  0,
200  [] (BitArray & ba, Instruction & instr)
201  {
202 // -----------------------------------------------------------------------------
203 etiss_uint8 rs2 = 0;
204 static BitArrayRange R_rs2_0(4, 2);
205 rs2 += R_rs2_0.read(ba) << 0;
206 etiss_uint8 uimm = 0;
207 static BitArrayRange R_uimm_6(6, 5);
208 uimm += R_uimm_6.read(ba) << 6;
209 etiss_uint8 rs1 = 0;
210 static BitArrayRange R_rs1_0(9, 7);
211 rs1 += R_rs1_0.read(ba) << 0;
212 static BitArrayRange R_uimm_3(12, 10);
213 uimm += R_uimm_3.read(ba) << 3;
214 
215 // -----------------------------------------------------------------------------
216 
217  std::stringstream ss;
218 // -----------------------------------------------------------------------------
219 ss << "cfsd" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | uimm=" + std::to_string(uimm) + " | rs1=" + std::to_string(rs1) + "]");
220 // -----------------------------------------------------------------------------
221  return ss.str();
222  }
223 );
224 
225 // CFLDSP ----------------------------------------------------------------------
226 static InstructionDefinition cfldsp_uimm_rd (
227  ISA16_RV64IMACFD,
228  "cfldsp",
229  (uint16_t) 0x2002,
230  (uint16_t) 0xe003,
231  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
232  {
233 
234 // -----------------------------------------------------------------------------
235 
236 // -----------------------------------------------------------------------------
237 
238 // -----------------------------------------------------------------------------
239 etiss_uint16 uimm = 0;
240 static BitArrayRange R_uimm_6(4, 2);
241 uimm += R_uimm_6.read(ba) << 6;
242 static BitArrayRange R_uimm_3(6, 5);
243 uimm += R_uimm_3.read(ba) << 3;
244 etiss_uint8 rd = 0;
245 static BitArrayRange R_rd_0(11, 7);
246 rd += R_rd_0.read(ba) << 0;
247 static BitArrayRange R_uimm_5(12, 12);
248 uimm += R_uimm_5.read(ba) << 5;
249 
250 // -----------------------------------------------------------------------------
251 
252  {
253  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
254 
255  cp.code() = std::string("//CFLDSP\n");
256 
257 // -----------------------------------------------------------------------------
258 cp.code() += "etiss_coverage_count(1, 146);\n";
259 { // block
260 cp.code() += "etiss_coverage_count(1, 1169);\n";
261 cp.code() += "{ // block\n";
262 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
263 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
264 cp.code() += "} // block\n";
265 } // block
266 { // block
267 cp.code() += "etiss_coverage_count(1, 6338);\n";
268 cp.code() += "{ // block\n";
269 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
270 cp.code() += "etiss_coverage_count(5, 6309, 6308, 6306, 6305, 6307);\n";
271 cp.code() += "etiss_uint64 mem_val_0;\n";
272 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
273 cp.code() += "if (cpu->exception) { // conditional\n";
274 { // procedure
275 cp.code() += "{ // procedure\n";
276 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
277 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
278 cp.code() += "} // procedure\n";
279 } // procedure
280 cp.code() += "} // conditional\n";
281 cp.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
282 cp.code() += "etiss_coverage_count(4, 6316, 6315, 6313, 6312);\n";
283 cp.code() += "((RV64IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
284 cp.code() += "etiss_coverage_count(4, 6325, 6323, 6322, 6324);\n";
285 cp.code() += "} // block\n";
286 } // block
287 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
288 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
289 // -----------------------------------------------------------------------------
290  cp.getAffectedRegisters().add("instructionPointer", 32);
291  }
292  {
293  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
294 
295  cp.code() = std::string("//CFLDSP\n");
296 
297 // -----------------------------------------------------------------------------
298 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
299 // -----------------------------------------------------------------------------
300  }
301 
302  return true;
303  },
304  0,
305  [] (BitArray & ba, Instruction & instr)
306  {
307 // -----------------------------------------------------------------------------
308 etiss_uint16 uimm = 0;
309 static BitArrayRange R_uimm_6(4, 2);
310 uimm += R_uimm_6.read(ba) << 6;
311 static BitArrayRange R_uimm_3(6, 5);
312 uimm += R_uimm_3.read(ba) << 3;
313 etiss_uint8 rd = 0;
314 static BitArrayRange R_rd_0(11, 7);
315 rd += R_rd_0.read(ba) << 0;
316 static BitArrayRange R_uimm_5(12, 12);
317 uimm += R_uimm_5.read(ba) << 5;
318 
319 // -----------------------------------------------------------------------------
320 
321  std::stringstream ss;
322 // -----------------------------------------------------------------------------
323 ss << "cfldsp" << " # " << ba << (" [uimm=" + std::to_string(uimm) + " | rd=" + std::to_string(rd) + "]");
324 // -----------------------------------------------------------------------------
325  return ss.str();
326  }
327 );
328 
329 // CFSDSP ----------------------------------------------------------------------
330 static InstructionDefinition cfsdsp_rs2_uimm (
331  ISA16_RV64IMACFD,
332  "cfsdsp",
333  (uint16_t) 0xa002,
334  (uint16_t) 0xe003,
335  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
336  {
337 
338 // -----------------------------------------------------------------------------
339 
340 // -----------------------------------------------------------------------------
341 
342 // -----------------------------------------------------------------------------
343 etiss_uint8 rs2 = 0;
344 static BitArrayRange R_rs2_0(6, 2);
345 rs2 += R_rs2_0.read(ba) << 0;
346 etiss_uint16 uimm = 0;
347 static BitArrayRange R_uimm_6(9, 7);
348 uimm += R_uimm_6.read(ba) << 6;
349 static BitArrayRange R_uimm_3(12, 10);
350 uimm += R_uimm_3.read(ba) << 3;
351 
352 // -----------------------------------------------------------------------------
353 
354  {
355  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
356 
357  cp.code() = std::string("//CFSDSP\n");
358 
359 // -----------------------------------------------------------------------------
360 cp.code() += "etiss_coverage_count(1, 147);\n";
361 { // block
362 cp.code() += "etiss_coverage_count(1, 1169);\n";
363 cp.code() += "{ // block\n";
364 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
365 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
366 cp.code() += "} // block\n";
367 } // block
368 { // block
369 cp.code() += "etiss_coverage_count(1, 6355);\n";
370 cp.code() += "{ // block\n";
371 cp.code() += "etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
372 cp.code() += "etiss_coverage_count(5, 6345, 6344, 6342, 6341, 6343);\n";
373 cp.code() += "etiss_uint64 mem_val_0;\n";
374 cp.code() += "mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
375 cp.code() += "etiss_coverage_count(6, 6354, 6348, 6347, 6353, 6351, 6350);\n";
376 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
377 cp.code() += "if (cpu->exception) { // conditional\n";
378 { // procedure
379 cp.code() += "{ // procedure\n";
380 cp.code() += "RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
381 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
382 cp.code() += "} // procedure\n";
383 } // procedure
384 cp.code() += "} // conditional\n";
385 cp.code() += "} // block\n";
386 } // block
387 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
388 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
389 // -----------------------------------------------------------------------------
390  cp.getAffectedRegisters().add("instructionPointer", 32);
391  }
392  {
393  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
394 
395  cp.code() = std::string("//CFSDSP\n");
396 
397 // -----------------------------------------------------------------------------
398 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
399 // -----------------------------------------------------------------------------
400  }
401 
402  return true;
403  },
404  0,
405  [] (BitArray & ba, Instruction & instr)
406  {
407 // -----------------------------------------------------------------------------
408 etiss_uint8 rs2 = 0;
409 static BitArrayRange R_rs2_0(6, 2);
410 rs2 += R_rs2_0.read(ba) << 0;
411 etiss_uint16 uimm = 0;
412 static BitArrayRange R_uimm_6(9, 7);
413 uimm += R_uimm_6.read(ba) << 6;
414 static BitArrayRange R_uimm_3(12, 10);
415 uimm += R_uimm_3.read(ba) << 3;
416 
417 // -----------------------------------------------------------------------------
418 
419  std::stringstream ss;
420 // -----------------------------------------------------------------------------
421 ss << "cfsdsp" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | uimm=" + std::to_string(uimm) + "]");
422 // -----------------------------------------------------------------------------
423  return ss.str();
424  }
425 );
ISA16_RV64IMACFD
etiss::instr::InstructionGroup ISA16_RV64IMACFD("ISA16_RV64IMACFD", 16)
cfsdsp_rs2_uimm
static InstructionDefinition cfsdsp_rs2_uimm(ISA16_RV64IMACFD, "cfsdsp",(uint16_t) 0xa002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint16 uimm=0;static BitArrayRange R_uimm_6(9, 7);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CFSDSP\n");cp.code()+="etiss_coverage_count(1, 147);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6355);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 6345, 6344, 6342, 6341, 6343);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(6, 6354, 6348, 6347, 6353, 6351, 6350);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CFSDSP\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint16 uimm=0;static BitArrayRange R_uimm_6(9, 7);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;std::stringstream ss;ss<< "cfsdsp"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | uimm="+std::to_string(uimm)+"]");return ss.str();})
cfld_rd_uimm_rs1
static InstructionDefinition cfld_rd_uimm_rs1(ISA16_RV64IMACFD, "cfld",(uint16_t) 0x2000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(6, 5);uimm+=R_uimm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CFLD\n");cp.code()+="etiss_coverage_count(1, 144);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6281);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(7, 6248, 6247, 6245, 6244, 6242, 6243, 6246);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 6255, 6254, 6252, 6251);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd+8ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(6, 6266, 6264, 6263, 6261, 6262, 6265);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CFLD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(6, 5);uimm+=R_uimm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;std::stringstream ss;ss<< "cfld"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | uimm="+std::to_string(uimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
cfldsp_uimm_rd
static InstructionDefinition cfldsp_uimm_rd(ISA16_RV64IMACFD, "cfldsp",(uint16_t) 0x2002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 uimm=0;static BitArrayRange R_uimm_6(4, 2);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_3(6, 5);uimm+=R_uimm_3.read(ba)<< 3;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_uimm_5(12, 12);uimm+=R_uimm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CFLDSP\n");cp.code()+="etiss_coverage_count(1, 146);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6338);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[2ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 6309, 6308, 6306, 6305, 6307);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 6316, 6315, 6313, 6312);\n";cp.code()+="((RV64IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(4, 6325, 6323, 6322, 6324);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CFLDSP\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 uimm=0;static BitArrayRange R_uimm_6(4, 2);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_3(6, 5);uimm+=R_uimm_3.read(ba)<< 3;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_uimm_5(12, 12);uimm+=R_uimm_5.read(ba)<< 5;std::stringstream ss;ss<< "cfldsp"<< " # "<< ba<<(" [uimm="+std::to_string(uimm)+" | rd="+std::to_string(rd)+"]");return ss.str();})
cfsd_rs2_uimm_rs1
static InstructionDefinition cfsd_rs2_uimm_rs1(ISA16_RV64IMACFD, "cfsd",(uint16_t) 0xa000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(6, 5);uimm+=R_uimm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CFSD\n");cp.code()+="etiss_coverage_count(1, 145);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6302);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(7, 6290, 6289, 6287, 6286, 6284, 6285, 6288);\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_uint64)(((RV64IMACFD*)cpu)->F["+std::to_string(rs2+8ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(8, 6301, 6293, 6292, 6300, 6298, 6297, 6295, 6296);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CFSD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(6, 5);uimm+=R_uimm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;std::stringstream ss;ss<< "cfsd"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | uimm="+std::to_string(uimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
uint16_t
static __inline__ uint16_t
Definition: arm_mve.h:315
etiss_uint8
uint8_t etiss_uint8
Definition: types.h:87
etiss_uint16
uint16_t etiss_uint16
Definition: types.h:90
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:386
etiss::CodePart::APPENDEDRETURNINGREQUIRED
@ APPENDEDRETURNINGREQUIRED
Definition: CodePart.h:402
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition: Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition: Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
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