11 using namespace etiss;
31 rd += R_rd_0.
read(ba) << 0;
34 rs1 += R_rs1_0.
read(ba) << 0;
37 rs2 += R_rs2_0.
read(ba) << 0;
40 rl += R_rl_0.
read(ba) << 0;
43 aq += R_aq_0.
read(ba) << 0;
50 cp.
code() = std::string(
"//AMOSWAPW\n");
54 cp.
code() +=
"{ // block\n";
56 cp.
code() +=
"} // block\n";
59 cp.
code() +=
"{ // block\n";
60 cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
61 if ((rd % 32ULL) != 0LL) {
62 cp.
code() +=
"etiss_uint32 mem_val_0;\n";
63 cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
64 cp.
code() +=
"if (cpu->exception) { // conditional\n";
66 cp.
code() +=
"{ // procedure\n";
67 cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
69 cp.
code() +=
"} // procedure\n";
71 cp.
code() +=
"} // conditional\n";
72 cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = (etiss_int64)(((etiss_int32)(mem_val_0)));\n";
74 cp.
code() +=
"etiss_uint32 mem_val_1;\n";
75 cp.
code() +=
"mem_val_1 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL]);\n";
76 cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
77 cp.
code() +=
"if (cpu->exception) { // conditional\n";
79 cp.
code() +=
"{ // procedure\n";
80 cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
82 cp.
code() +=
"} // procedure\n";
84 cp.
code() +=
"} // conditional\n";
85 cp.
code() +=
"} // block\n";
88 cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
95 cp.
code() = std::string(
"//AMOSWAPW\n");
98 cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
110 rd += R_rd_0.read(ba) << 0;
113 rs1 += R_rs1_0.read(ba) << 0;
116 rs2 += R_rs2_0.read(ba) << 0;
119 rl += R_rl_0.read(ba) << 0;
122 aq += R_aq_0.read(ba) << 0;
126 std::stringstream ss;
128 ss <<
"amoswapw" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
150 rd += R_rd_0.
read(ba) << 0;
153 rs1 += R_rs1_0.
read(ba) << 0;
156 rs2 += R_rs2_0.
read(ba) << 0;
159 rl += R_rl_0.
read(ba) << 0;
162 aq += R_aq_0.
read(ba) << 0;
169 cp.
code() = std::string(
"//AMOADDW\n");
173 cp.
code() +=
"{ // block\n";
175 cp.
code() +=
"} // block\n";
178 cp.
code() +=
"{ // block\n";
179 cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
180 cp.
code() +=
"etiss_uint32 mem_val_0;\n";
181 cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
182 cp.
code() +=
"if (cpu->exception) { // conditional\n";
184 cp.
code() +=
"{ // procedure\n";
185 cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
187 cp.
code() +=
"} // procedure\n";
189 cp.
code() +=
"} // conditional\n";
190 cp.
code() +=
"etiss_int32 res1 = mem_val_0;\n";
191 if ((rd % 32ULL) != 0LL) {
192 cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = res1;\n";
194 cp.
code() +=
"etiss_uint32 res2 = res1 + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL];\n";
195 cp.
code() +=
"etiss_uint32 mem_val_1;\n";
196 cp.
code() +=
"mem_val_1 = res2;\n";
197 cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
198 cp.
code() +=
"if (cpu->exception) { // conditional\n";
200 cp.
code() +=
"{ // procedure\n";
201 cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
203 cp.
code() +=
"} // procedure\n";
205 cp.
code() +=
"} // conditional\n";
206 cp.
code() +=
"} // block\n";
209 cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
216 cp.
code() = std::string(
"//AMOADDW\n");
219 cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
231 rd += R_rd_0.read(ba) << 0;
234 rs1 += R_rs1_0.read(ba) << 0;
237 rs2 += R_rs2_0.read(ba) << 0;
240 rl += R_rl_0.read(ba) << 0;
243 aq += R_aq_0.read(ba) << 0;
247 std::stringstream ss;
249 ss <<
"amoaddw" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
271 rd += R_rd_0.
read(ba) << 0;
274 rs1 += R_rs1_0.
read(ba) << 0;
277 rs2 += R_rs2_0.
read(ba) << 0;
280 rl += R_rl_0.
read(ba) << 0;
283 aq += R_aq_0.
read(ba) << 0;
290 cp.
code() = std::string(
"//AMOXORW\n");
294 cp.
code() +=
"{ // block\n";
296 cp.
code() +=
"} // block\n";
299 cp.
code() +=
"{ // block\n";
300 cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
301 cp.
code() +=
"etiss_uint32 mem_val_0;\n";
302 cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
303 cp.
code() +=
"if (cpu->exception) { // conditional\n";
305 cp.
code() +=
"{ // procedure\n";
306 cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
308 cp.
code() +=
"} // procedure\n";
310 cp.
code() +=
"} // conditional\n";
311 cp.
code() +=
"etiss_int32 res1 = mem_val_0;\n";
312 if ((rd % 32ULL) != 0LL) {
313 cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = res1;\n";
315 cp.
code() +=
"etiss_uint32 res2 = res1 ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL];\n";
316 cp.
code() +=
"etiss_uint32 mem_val_1;\n";
317 cp.
code() +=
"mem_val_1 = res2;\n";
318 cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
319 cp.
code() +=
"if (cpu->exception) { // conditional\n";
321 cp.
code() +=
"{ // procedure\n";
322 cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
324 cp.
code() +=
"} // procedure\n";
326 cp.
code() +=
"} // conditional\n";
327 cp.
code() +=
"} // block\n";
330 cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
337 cp.
code() = std::string(
"//AMOXORW\n");
340 cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
352 rd += R_rd_0.read(ba) << 0;
355 rs1 += R_rs1_0.read(ba) << 0;
358 rs2 += R_rs2_0.read(ba) << 0;
361 rl += R_rl_0.read(ba) << 0;
364 aq += R_aq_0.read(ba) << 0;
368 std::stringstream ss;
370 ss <<
"amoxorw" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
392 rd += R_rd_0.
read(ba) << 0;
395 rs1 += R_rs1_0.
read(ba) << 0;
398 rs2 += R_rs2_0.
read(ba) << 0;
401 rl += R_rl_0.
read(ba) << 0;
404 aq += R_aq_0.
read(ba) << 0;
411 cp.
code() = std::string(
"//AMOANDW\n");
415 cp.
code() +=
"{ // block\n";
417 cp.
code() +=
"} // block\n";
420 cp.
code() +=
"{ // block\n";
421 cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
422 cp.
code() +=
"etiss_uint32 mem_val_0;\n";
423 cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
424 cp.
code() +=
"if (cpu->exception) { // conditional\n";
426 cp.
code() +=
"{ // procedure\n";
427 cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
429 cp.
code() +=
"} // procedure\n";
431 cp.
code() +=
"} // conditional\n";
432 cp.
code() +=
"etiss_int32 res1 = mem_val_0;\n";
433 if ((rd % 32ULL) != 0LL) {
434 cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = res1;\n";
436 cp.
code() +=
"etiss_uint32 res2 = res1 & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL];\n";
437 cp.
code() +=
"etiss_uint32 mem_val_1;\n";
438 cp.
code() +=
"mem_val_1 = res2;\n";
439 cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
440 cp.
code() +=
"if (cpu->exception) { // conditional\n";
442 cp.
code() +=
"{ // procedure\n";
443 cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
445 cp.
code() +=
"} // procedure\n";
447 cp.
code() +=
"} // conditional\n";
448 cp.
code() +=
"} // block\n";
451 cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
458 cp.
code() = std::string(
"//AMOANDW\n");
461 cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
473 rd += R_rd_0.read(ba) << 0;
476 rs1 += R_rs1_0.read(ba) << 0;
479 rs2 += R_rs2_0.read(ba) << 0;
482 rl += R_rl_0.read(ba) << 0;
485 aq += R_aq_0.read(ba) << 0;
489 std::stringstream ss;
491 ss <<
"amoandw" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
513 rd += R_rd_0.
read(ba) << 0;
516 rs1 += R_rs1_0.
read(ba) << 0;
519 rs2 += R_rs2_0.
read(ba) << 0;
522 rl += R_rl_0.
read(ba) << 0;
525 aq += R_aq_0.
read(ba) << 0;
532 cp.
code() = std::string(
"//AMOORW\n");
536 cp.
code() +=
"{ // block\n";
538 cp.
code() +=
"} // block\n";
541 cp.
code() +=
"{ // block\n";
542 cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
543 cp.
code() +=
"etiss_uint32 mem_val_0;\n";
544 cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
545 cp.
code() +=
"if (cpu->exception) { // conditional\n";
547 cp.
code() +=
"{ // procedure\n";
548 cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
550 cp.
code() +=
"} // procedure\n";
552 cp.
code() +=
"} // conditional\n";
553 cp.
code() +=
"etiss_int32 res1 = mem_val_0;\n";
554 if ((rd % 32ULL) != 0LL) {
555 cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = res1;\n";
557 cp.
code() +=
"etiss_uint32 res2 = res1 | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL];\n";
558 cp.
code() +=
"etiss_uint32 mem_val_1;\n";
559 cp.
code() +=
"mem_val_1 = res2;\n";
560 cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
561 cp.
code() +=
"if (cpu->exception) { // conditional\n";
563 cp.
code() +=
"{ // procedure\n";
564 cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
566 cp.
code() +=
"} // procedure\n";
568 cp.
code() +=
"} // conditional\n";
569 cp.
code() +=
"} // block\n";
572 cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
579 cp.
code() = std::string(
"//AMOORW\n");
582 cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
594 rd += R_rd_0.read(ba) << 0;
597 rs1 += R_rs1_0.read(ba) << 0;
600 rs2 += R_rs2_0.read(ba) << 0;
603 rl += R_rl_0.read(ba) << 0;
606 aq += R_aq_0.read(ba) << 0;
610 std::stringstream ss;
612 ss <<
"amoorw" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
634 rd += R_rd_0.
read(ba) << 0;
637 rs1 += R_rs1_0.
read(ba) << 0;
640 rs2 += R_rs2_0.
read(ba) << 0;
643 rl += R_rl_0.
read(ba) << 0;
646 aq += R_aq_0.
read(ba) << 0;
653 cp.
code() = std::string(
"//AMOMINW\n");
657 cp.
code() +=
"{ // block\n";
659 cp.
code() +=
"} // block\n";
662 cp.
code() +=
"{ // block\n";
663 cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
664 cp.
code() +=
"etiss_uint32 mem_val_0;\n";
665 cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
666 cp.
code() +=
"if (cpu->exception) { // conditional\n";
668 cp.
code() +=
"{ // procedure\n";
669 cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
671 cp.
code() +=
"} // procedure\n";
673 cp.
code() +=
"} // conditional\n";
674 cp.
code() +=
"etiss_int32 res1 = mem_val_0;\n";
675 if ((rd % 32ULL) != 0LL) {
676 cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = res1;\n";
678 cp.
code() +=
"etiss_uint32 res2 = (res1 > (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL]) : (res1);\n";
679 cp.
code() +=
"etiss_uint32 mem_val_1;\n";
680 cp.
code() +=
"mem_val_1 = res2;\n";
681 cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
682 cp.
code() +=
"if (cpu->exception) { // conditional\n";
684 cp.
code() +=
"{ // procedure\n";
685 cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
687 cp.
code() +=
"} // procedure\n";
689 cp.
code() +=
"} // conditional\n";
690 cp.
code() +=
"} // block\n";
693 cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
700 cp.
code() = std::string(
"//AMOMINW\n");
703 cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
715 rd += R_rd_0.read(ba) << 0;
718 rs1 += R_rs1_0.read(ba) << 0;
721 rs2 += R_rs2_0.read(ba) << 0;
724 rl += R_rl_0.read(ba) << 0;
727 aq += R_aq_0.read(ba) << 0;
731 std::stringstream ss;
733 ss <<
"amominw" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
755 rd += R_rd_0.
read(ba) << 0;
758 rs1 += R_rs1_0.
read(ba) << 0;
761 rs2 += R_rs2_0.
read(ba) << 0;
764 rl += R_rl_0.
read(ba) << 0;
767 aq += R_aq_0.
read(ba) << 0;
774 cp.
code() = std::string(
"//AMOMAXW\n");
778 cp.
code() +=
"{ // block\n";
780 cp.
code() +=
"} // block\n";
783 cp.
code() +=
"{ // block\n";
784 cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
785 cp.
code() +=
"etiss_uint32 mem_val_0;\n";
786 cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
787 cp.
code() +=
"if (cpu->exception) { // conditional\n";
789 cp.
code() +=
"{ // procedure\n";
790 cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
792 cp.
code() +=
"} // procedure\n";
794 cp.
code() +=
"} // conditional\n";
795 cp.
code() +=
"etiss_int32 res1 = mem_val_0;\n";
796 if ((rd % 32ULL) != 0LL) {
797 cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = res1;\n";
799 cp.
code() +=
"etiss_uint32 res2 = (res1 < (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL]) : (res1);\n";
800 cp.
code() +=
"etiss_uint32 mem_val_1;\n";
801 cp.
code() +=
"mem_val_1 = res2;\n";
802 cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
803 cp.
code() +=
"if (cpu->exception) { // conditional\n";
805 cp.
code() +=
"{ // procedure\n";
806 cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
808 cp.
code() +=
"} // procedure\n";
810 cp.
code() +=
"} // conditional\n";
811 cp.
code() +=
"} // block\n";
814 cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
821 cp.
code() = std::string(
"//AMOMAXW\n");
824 cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
836 rd += R_rd_0.read(ba) << 0;
839 rs1 += R_rs1_0.read(ba) << 0;
842 rs2 += R_rs2_0.read(ba) << 0;
845 rl += R_rl_0.read(ba) << 0;
848 aq += R_aq_0.read(ba) << 0;
852 std::stringstream ss;
854 ss <<
"amomaxw" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
876 rd += R_rd_0.
read(ba) << 0;
879 rs1 += R_rs1_0.
read(ba) << 0;
882 rs2 += R_rs2_0.
read(ba) << 0;
885 rl += R_rl_0.
read(ba) << 0;
888 aq += R_aq_0.
read(ba) << 0;
895 cp.
code() = std::string(
"//AMOMINUW\n");
899 cp.
code() +=
"{ // block\n";
901 cp.
code() +=
"} // block\n";
904 cp.
code() +=
"{ // block\n";
905 cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
906 cp.
code() +=
"etiss_uint32 mem_val_0;\n";
907 cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
908 cp.
code() +=
"if (cpu->exception) { // conditional\n";
910 cp.
code() +=
"{ // procedure\n";
911 cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
913 cp.
code() +=
"} // procedure\n";
915 cp.
code() +=
"} // conditional\n";
916 cp.
code() +=
"etiss_uint32 res1 = mem_val_0;\n";
917 if ((rd % 32ULL) != 0LL) {
918 cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = (etiss_int32)(res1);\n";
920 cp.
code() +=
"etiss_uint32 res2 = (res1 > (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL]) : (res1);\n";
921 cp.
code() +=
"etiss_uint32 mem_val_1;\n";
922 cp.
code() +=
"mem_val_1 = res2;\n";
923 cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
924 cp.
code() +=
"if (cpu->exception) { // conditional\n";
926 cp.
code() +=
"{ // procedure\n";
927 cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
929 cp.
code() +=
"} // procedure\n";
931 cp.
code() +=
"} // conditional\n";
932 cp.
code() +=
"} // block\n";
935 cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
942 cp.
code() = std::string(
"//AMOMINUW\n");
945 cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
957 rd += R_rd_0.read(ba) << 0;
960 rs1 += R_rs1_0.read(ba) << 0;
963 rs2 += R_rs2_0.read(ba) << 0;
966 rl += R_rl_0.read(ba) << 0;
969 aq += R_aq_0.read(ba) << 0;
973 std::stringstream ss;
975 ss <<
"amominuw" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
997 rd += R_rd_0.
read(ba) << 0;
1000 rs1 += R_rs1_0.
read(ba) << 0;
1003 rs2 += R_rs2_0.
read(ba) << 0;
1006 rl += R_rl_0.
read(ba) << 0;
1009 aq += R_aq_0.
read(ba) << 0;
1016 cp.
code() = std::string(
"//AMOMAXUW\n");
1020 cp.
code() +=
"{ // block\n";
1022 cp.
code() +=
"} // block\n";
1025 cp.
code() +=
"{ // block\n";
1026 cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
1027 cp.
code() +=
"etiss_uint32 mem_val_0;\n";
1028 cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
1029 cp.
code() +=
"if (cpu->exception) { // conditional\n";
1031 cp.
code() +=
"{ // procedure\n";
1032 cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1034 cp.
code() +=
"} // procedure\n";
1036 cp.
code() +=
"} // conditional\n";
1037 cp.
code() +=
"etiss_uint32 res1 = mem_val_0;\n";
1038 if ((rd % 32ULL) != 0LL) {
1039 cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = (etiss_int32)(res1);\n";
1041 cp.
code() +=
"etiss_uint32 res2 = (res1 < (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL]) : (res1);\n";
1042 cp.
code() +=
"etiss_uint32 mem_val_1;\n";
1043 cp.
code() +=
"mem_val_1 = res2;\n";
1044 cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
1045 cp.
code() +=
"if (cpu->exception) { // conditional\n";
1047 cp.
code() +=
"{ // procedure\n";
1048 cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1050 cp.
code() +=
"} // procedure\n";
1052 cp.
code() +=
"} // conditional\n";
1053 cp.
code() +=
"} // block\n";
1056 cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
1063 cp.
code() = std::string(
"//AMOMAXUW\n");
1066 cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1078 rd += R_rd_0.read(ba) << 0;
1081 rs1 += R_rs1_0.read(ba) << 0;
1084 rs2 += R_rs2_0.read(ba) << 0;
1087 rl += R_rl_0.read(ba) << 0;
1090 aq += R_aq_0.read(ba) << 0;
1094 std::stringstream ss;
1096 ss <<
"amomaxuw" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
static InstructionDefinition amoandw_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoandw",(uint32_t) 0x6000202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOANDW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int32 res1 = mem_val_0;\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res1;\n";} cp.code()+="etiss_uint32 res2 = res1 & *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_uint32 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOANDW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoandw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amomaxw_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amomaxw",(uint32_t) 0xa000202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOMAXW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int32 res1 = mem_val_0;\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res1;\n";} cp.code()+="etiss_uint32 res2 = (res1 < (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) ? (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) : (res1);\n";cp.code()+="etiss_uint32 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOMAXW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amomaxw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amominw_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amominw",(uint32_t) 0x8000202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOMINW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int32 res1 = mem_val_0;\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res1;\n";} cp.code()+="etiss_uint32 res2 = (res1 > (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) ? (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) : (res1);\n";cp.code()+="etiss_uint32 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOMINW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amominw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amomaxuw_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amomaxuw",(uint32_t) 0xe000202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOMAXUW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint32 res1 = mem_val_0;\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int32)(res1);\n";} cp.code()+="etiss_uint32 res2 = (res1 < (etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) ? (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) : (res1);\n";cp.code()+="etiss_uint32 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOMAXUW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amomaxuw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amoswapw_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoswapw",(uint32_t) 0x800202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOSWAPW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(((etiss_int32)(mem_val_0)));\n";} cp.code()+="etiss_uint32 mem_val_1;\n";cp.code()+="mem_val_1 = (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOSWAPW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoswapw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amoaddw_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoaddw",(uint32_t) 0x00202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOADDW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int32 res1 = mem_val_0;\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res1;\n";} cp.code()+="etiss_uint32 res2 = res1 + *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_uint32 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOADDW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoaddw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amoorw_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoorw",(uint32_t) 0x4000202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOORW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int32 res1 = mem_val_0;\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res1;\n";} cp.code()+="etiss_uint32 res2 = res1 | *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_uint32 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOORW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoorw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amominuw_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amominuw",(uint32_t) 0xc000202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOMINUW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint32 res1 = mem_val_0;\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int32)(res1);\n";} cp.code()+="etiss_uint32 res2 = (res1 > (etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) ? (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) : (res1);\n";cp.code()+="etiss_uint32 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOMINUW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amominuw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amoxorw_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoxorw",(uint32_t) 0x2000202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOXORW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int32 res1 = mem_val_0;\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res1;\n";} cp.code()+="etiss_uint32 res2 = res1 ^ *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_uint32 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOXORW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoxorw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static __inline__ uint32_t
Contains a small code snipped.
@ APPENDEDRETURNINGREQUIRED
RegisterSet & getAffectedRegisters()
void append(const CodePart &part, CodePart::TYPE type)
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Reading through it will only return bits within the range.
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
this class contains parameters that persist in between instruction lookpus/translation within a trans...
uint64_t current_address_
start address of current instruction
holds information and translation callbacks for an instruction.
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.