20 (uint32_t) 0xf800707f,
32rd += R_rd_0.
read(ba) << 0;
35rs1 += R_rs1_0.
read(ba) << 0;
38rs2 += R_rs2_0.
read(ba) << 0;
41rl += R_rl_0.
read(ba) << 0;
44aq += R_aq_0.
read(ba) << 0;
52 cp.
code() = std::string(
"//AMOSWAPW\n");
55cp.
code() +=
"etiss_coverage_count(1, 172);\n";
57cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
58cp.
code() +=
"{ // block\n";
60cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
61cp.
code() +=
"} // block\n";
64cp.
code() +=
"etiss_coverage_count(1, 6522);\n";
65cp.
code() +=
"{ // block\n";
66cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
67cp.
code() +=
"etiss_coverage_count(4, 6489, 6488, 6487, 6485);\n";
68cp.
code() +=
"etiss_coverage_count(1, 6490);\n";
69if ((rd % 32ULL) != 0LL) {
70cp.
code() +=
"etiss_coverage_count(5, 6496, 6493, 6491, 6494, 6495);\n";
71cp.
code() +=
"etiss_uint32 mem_val_0;\n";
72cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
73cp.
code() +=
"if (cpu->exception) { // conditional\n";
75cp.
code() +=
"{ // procedure\n";
76cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
78cp.
code() +=
"} // procedure\n";
80cp.
code() +=
"} // conditional\n";
81cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = (etiss_int64)(((etiss_int32)(mem_val_0)));\n";
82cp.
code() +=
"etiss_coverage_count(9, 6510, 6501, 6500, 6498, 6509, 6506, 6504, 6503, 6507);\n";
84cp.
code() +=
"etiss_uint32 mem_val_1;\n";
85cp.
code() +=
"mem_val_1 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL]);\n";
86cp.
code() +=
"etiss_coverage_count(7, 6521, 6513, 6512, 6520, 6518, 6517, 6515);\n";
87cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
88cp.
code() +=
"if (cpu->exception) { // conditional\n";
90cp.
code() +=
"{ // procedure\n";
91cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
93cp.
code() +=
"} // procedure\n";
95cp.
code() +=
"} // conditional\n";
96cp.
code() +=
"} // block\n";
99cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
106 cp.
code() = std::string(
"//AMOSWAPW\n");
109cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
121rd += R_rd_0.read(ba) << 0;
124rs1 += R_rs1_0.read(ba) << 0;
127rs2 += R_rs2_0.read(ba) << 0;
130rl += R_rl_0.read(ba) << 0;
133aq += R_aq_0.read(ba) << 0;
137 std::stringstream ss;
139ss <<
"amoswapw" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
150 (uint32_t) 0xf800707f,
162rd += R_rd_0.
read(ba) << 0;
165rs1 += R_rs1_0.
read(ba) << 0;
168rs2 += R_rs2_0.
read(ba) << 0;
171rl += R_rl_0.
read(ba) << 0;
174aq += R_aq_0.
read(ba) << 0;
182 cp.
code() = std::string(
"//AMOADDW\n");
185cp.
code() +=
"etiss_coverage_count(1, 173);\n";
187cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
188cp.
code() +=
"{ // block\n";
190cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
191cp.
code() +=
"} // block\n";
194cp.
code() +=
"etiss_coverage_count(1, 6563);\n";
195cp.
code() +=
"{ // block\n";
196cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
197cp.
code() +=
"etiss_coverage_count(4, 6529, 6528, 6527, 6525);\n";
198cp.
code() +=
"etiss_uint32 mem_val_0;\n";
199cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
200cp.
code() +=
"if (cpu->exception) { // conditional\n";
202cp.
code() +=
"{ // procedure\n";
203cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
205cp.
code() +=
"} // procedure\n";
207cp.
code() +=
"} // conditional\n";
208cp.
code() +=
"etiss_int32 res1 = mem_val_0;\n";
209cp.
code() +=
"etiss_coverage_count(3, 6534, 6533, 6532);\n";
210cp.
code() +=
"etiss_coverage_count(1, 6535);\n";
211if ((rd % 32ULL) != 0LL) {
212cp.
code() +=
"etiss_coverage_count(5, 6541, 6538, 6536, 6539, 6540);\n";
213cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = res1;\n";
214cp.
code() +=
"etiss_coverage_count(5, 6548, 6546, 6545, 6543, 6547);\n";
216cp.
code() +=
"etiss_uint32 res2 = res1 + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL];\n";
217cp.
code() +=
"etiss_coverage_count(6, 6557, 6556, 6550, 6555, 6554, 6552);\n";
218cp.
code() +=
"etiss_uint32 mem_val_1;\n";
219cp.
code() +=
"mem_val_1 = res2;\n";
220cp.
code() +=
"etiss_coverage_count(4, 6562, 6560, 6559, 6561);\n";
221cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
222cp.
code() +=
"if (cpu->exception) { // conditional\n";
224cp.
code() +=
"{ // procedure\n";
225cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
227cp.
code() +=
"} // procedure\n";
229cp.
code() +=
"} // conditional\n";
230cp.
code() +=
"} // block\n";
233cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
240 cp.
code() = std::string(
"//AMOADDW\n");
243cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
255rd += R_rd_0.read(ba) << 0;
258rs1 += R_rs1_0.read(ba) << 0;
261rs2 += R_rs2_0.read(ba) << 0;
264rl += R_rl_0.read(ba) << 0;
267aq += R_aq_0.read(ba) << 0;
271 std::stringstream ss;
273ss <<
"amoaddw" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
283 (uint32_t) 0x2000202f,
284 (uint32_t) 0xf800707f,
296rd += R_rd_0.
read(ba) << 0;
299rs1 += R_rs1_0.
read(ba) << 0;
302rs2 += R_rs2_0.
read(ba) << 0;
305rl += R_rl_0.
read(ba) << 0;
308aq += R_aq_0.
read(ba) << 0;
316 cp.
code() = std::string(
"//AMOXORW\n");
319cp.
code() +=
"etiss_coverage_count(1, 174);\n";
321cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
322cp.
code() +=
"{ // block\n";
324cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
325cp.
code() +=
"} // block\n";
328cp.
code() +=
"etiss_coverage_count(1, 6604);\n";
329cp.
code() +=
"{ // block\n";
330cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
331cp.
code() +=
"etiss_coverage_count(4, 6570, 6569, 6568, 6566);\n";
332cp.
code() +=
"etiss_uint32 mem_val_0;\n";
333cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
334cp.
code() +=
"if (cpu->exception) { // conditional\n";
336cp.
code() +=
"{ // procedure\n";
337cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
339cp.
code() +=
"} // procedure\n";
341cp.
code() +=
"} // conditional\n";
342cp.
code() +=
"etiss_int32 res1 = mem_val_0;\n";
343cp.
code() +=
"etiss_coverage_count(3, 6575, 6574, 6573);\n";
344cp.
code() +=
"etiss_coverage_count(1, 6576);\n";
345if ((rd % 32ULL) != 0LL) {
346cp.
code() +=
"etiss_coverage_count(5, 6582, 6579, 6577, 6580, 6581);\n";
347cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = res1;\n";
348cp.
code() +=
"etiss_coverage_count(5, 6589, 6587, 6586, 6584, 6588);\n";
350cp.
code() +=
"etiss_uint32 res2 = res1 ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL];\n";
351cp.
code() +=
"etiss_coverage_count(6, 6598, 6597, 6591, 6596, 6595, 6593);\n";
352cp.
code() +=
"etiss_uint32 mem_val_1;\n";
353cp.
code() +=
"mem_val_1 = res2;\n";
354cp.
code() +=
"etiss_coverage_count(4, 6603, 6601, 6600, 6602);\n";
355cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
356cp.
code() +=
"if (cpu->exception) { // conditional\n";
358cp.
code() +=
"{ // procedure\n";
359cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
361cp.
code() +=
"} // procedure\n";
363cp.
code() +=
"} // conditional\n";
364cp.
code() +=
"} // block\n";
367cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
374 cp.
code() = std::string(
"//AMOXORW\n");
377cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
389rd += R_rd_0.read(ba) << 0;
392rs1 += R_rs1_0.read(ba) << 0;
395rs2 += R_rs2_0.read(ba) << 0;
398rl += R_rl_0.read(ba) << 0;
401aq += R_aq_0.read(ba) << 0;
405 std::stringstream ss;
407ss <<
"amoxorw" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
417 (uint32_t) 0x6000202f,
418 (uint32_t) 0xf800707f,
430rd += R_rd_0.
read(ba) << 0;
433rs1 += R_rs1_0.
read(ba) << 0;
436rs2 += R_rs2_0.
read(ba) << 0;
439rl += R_rl_0.
read(ba) << 0;
442aq += R_aq_0.
read(ba) << 0;
450 cp.
code() = std::string(
"//AMOANDW\n");
453cp.
code() +=
"etiss_coverage_count(1, 175);\n";
455cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
456cp.
code() +=
"{ // block\n";
458cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
459cp.
code() +=
"} // block\n";
462cp.
code() +=
"etiss_coverage_count(1, 6645);\n";
463cp.
code() +=
"{ // block\n";
464cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
465cp.
code() +=
"etiss_coverage_count(4, 6611, 6610, 6609, 6607);\n";
466cp.
code() +=
"etiss_uint32 mem_val_0;\n";
467cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
468cp.
code() +=
"if (cpu->exception) { // conditional\n";
470cp.
code() +=
"{ // procedure\n";
471cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
473cp.
code() +=
"} // procedure\n";
475cp.
code() +=
"} // conditional\n";
476cp.
code() +=
"etiss_int32 res1 = mem_val_0;\n";
477cp.
code() +=
"etiss_coverage_count(3, 6616, 6615, 6614);\n";
478cp.
code() +=
"etiss_coverage_count(1, 6617);\n";
479if ((rd % 32ULL) != 0LL) {
480cp.
code() +=
"etiss_coverage_count(5, 6623, 6620, 6618, 6621, 6622);\n";
481cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = res1;\n";
482cp.
code() +=
"etiss_coverage_count(5, 6630, 6628, 6627, 6625, 6629);\n";
484cp.
code() +=
"etiss_uint32 res2 = res1 & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL];\n";
485cp.
code() +=
"etiss_coverage_count(6, 6639, 6638, 6632, 6637, 6636, 6634);\n";
486cp.
code() +=
"etiss_uint32 mem_val_1;\n";
487cp.
code() +=
"mem_val_1 = res2;\n";
488cp.
code() +=
"etiss_coverage_count(4, 6644, 6642, 6641, 6643);\n";
489cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
490cp.
code() +=
"if (cpu->exception) { // conditional\n";
492cp.
code() +=
"{ // procedure\n";
493cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
495cp.
code() +=
"} // procedure\n";
497cp.
code() +=
"} // conditional\n";
498cp.
code() +=
"} // block\n";
501cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
508 cp.
code() = std::string(
"//AMOANDW\n");
511cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
523rd += R_rd_0.read(ba) << 0;
526rs1 += R_rs1_0.read(ba) << 0;
529rs2 += R_rs2_0.read(ba) << 0;
532rl += R_rl_0.read(ba) << 0;
535aq += R_aq_0.read(ba) << 0;
539 std::stringstream ss;
541ss <<
"amoandw" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
551 (uint32_t) 0x4000202f,
552 (uint32_t) 0xf800707f,
564rd += R_rd_0.
read(ba) << 0;
567rs1 += R_rs1_0.
read(ba) << 0;
570rs2 += R_rs2_0.
read(ba) << 0;
573rl += R_rl_0.
read(ba) << 0;
576aq += R_aq_0.
read(ba) << 0;
584 cp.
code() = std::string(
"//AMOORW\n");
587cp.
code() +=
"etiss_coverage_count(1, 176);\n";
589cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
590cp.
code() +=
"{ // block\n";
592cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
593cp.
code() +=
"} // block\n";
596cp.
code() +=
"etiss_coverage_count(1, 6686);\n";
597cp.
code() +=
"{ // block\n";
598cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
599cp.
code() +=
"etiss_coverage_count(4, 6652, 6651, 6650, 6648);\n";
600cp.
code() +=
"etiss_uint32 mem_val_0;\n";
601cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
602cp.
code() +=
"if (cpu->exception) { // conditional\n";
604cp.
code() +=
"{ // procedure\n";
605cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
607cp.
code() +=
"} // procedure\n";
609cp.
code() +=
"} // conditional\n";
610cp.
code() +=
"etiss_int32 res1 = mem_val_0;\n";
611cp.
code() +=
"etiss_coverage_count(3, 6657, 6656, 6655);\n";
612cp.
code() +=
"etiss_coverage_count(1, 6658);\n";
613if ((rd % 32ULL) != 0LL) {
614cp.
code() +=
"etiss_coverage_count(5, 6664, 6661, 6659, 6662, 6663);\n";
615cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = res1;\n";
616cp.
code() +=
"etiss_coverage_count(5, 6671, 6669, 6668, 6666, 6670);\n";
618cp.
code() +=
"etiss_uint32 res2 = res1 | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL];\n";
619cp.
code() +=
"etiss_coverage_count(6, 6680, 6679, 6673, 6678, 6677, 6675);\n";
620cp.
code() +=
"etiss_uint32 mem_val_1;\n";
621cp.
code() +=
"mem_val_1 = res2;\n";
622cp.
code() +=
"etiss_coverage_count(4, 6685, 6683, 6682, 6684);\n";
623cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
624cp.
code() +=
"if (cpu->exception) { // conditional\n";
626cp.
code() +=
"{ // procedure\n";
627cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
629cp.
code() +=
"} // procedure\n";
631cp.
code() +=
"} // conditional\n";
632cp.
code() +=
"} // block\n";
635cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
642 cp.
code() = std::string(
"//AMOORW\n");
645cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
657rd += R_rd_0.read(ba) << 0;
660rs1 += R_rs1_0.read(ba) << 0;
663rs2 += R_rs2_0.read(ba) << 0;
666rl += R_rl_0.read(ba) << 0;
669aq += R_aq_0.read(ba) << 0;
673 std::stringstream ss;
675ss <<
"amoorw" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
685 (uint32_t) 0x8000202f,
686 (uint32_t) 0xf800707f,
698rd += R_rd_0.
read(ba) << 0;
701rs1 += R_rs1_0.
read(ba) << 0;
704rs2 += R_rs2_0.
read(ba) << 0;
707rl += R_rl_0.
read(ba) << 0;
710aq += R_aq_0.
read(ba) << 0;
718 cp.
code() = std::string(
"//AMOMINW\n");
721cp.
code() +=
"etiss_coverage_count(1, 177);\n";
723cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
724cp.
code() +=
"{ // block\n";
726cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
727cp.
code() +=
"} // block\n";
730cp.
code() +=
"etiss_coverage_count(1, 6736);\n";
731cp.
code() +=
"{ // block\n";
732cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
733cp.
code() +=
"etiss_coverage_count(4, 6693, 6692, 6691, 6689);\n";
734cp.
code() +=
"etiss_uint32 mem_val_0;\n";
735cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
736cp.
code() +=
"if (cpu->exception) { // conditional\n";
738cp.
code() +=
"{ // procedure\n";
739cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
741cp.
code() +=
"} // procedure\n";
743cp.
code() +=
"} // conditional\n";
744cp.
code() +=
"etiss_int32 res1 = mem_val_0;\n";
745cp.
code() +=
"etiss_coverage_count(3, 6698, 6697, 6696);\n";
746cp.
code() +=
"etiss_coverage_count(1, 6699);\n";
747if ((rd % 32ULL) != 0LL) {
748cp.
code() +=
"etiss_coverage_count(5, 6705, 6702, 6700, 6703, 6704);\n";
749cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = res1;\n";
750cp.
code() +=
"etiss_coverage_count(5, 6712, 6710, 6709, 6707, 6711);\n";
752cp.
code() +=
"etiss_uint32 res2 = (res1 > (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL]) : (res1);\n";
753cp.
code() +=
"etiss_coverage_count(12, 6730, 6729, 6722, 6714, 6721, 6719, 6718, 6716, 6727, 6726, 6724, 6728);\n";
754cp.
code() +=
"etiss_uint32 mem_val_1;\n";
755cp.
code() +=
"mem_val_1 = res2;\n";
756cp.
code() +=
"etiss_coverage_count(4, 6735, 6733, 6732, 6734);\n";
757cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
758cp.
code() +=
"if (cpu->exception) { // conditional\n";
760cp.
code() +=
"{ // procedure\n";
761cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
763cp.
code() +=
"} // procedure\n";
765cp.
code() +=
"} // conditional\n";
766cp.
code() +=
"} // block\n";
769cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
776 cp.
code() = std::string(
"//AMOMINW\n");
779cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
791rd += R_rd_0.read(ba) << 0;
794rs1 += R_rs1_0.read(ba) << 0;
797rs2 += R_rs2_0.read(ba) << 0;
800rl += R_rl_0.read(ba) << 0;
803aq += R_aq_0.read(ba) << 0;
807 std::stringstream ss;
809ss <<
"amominw" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
819 (uint32_t) 0xa000202f,
820 (uint32_t) 0xf800707f,
832rd += R_rd_0.
read(ba) << 0;
835rs1 += R_rs1_0.
read(ba) << 0;
838rs2 += R_rs2_0.
read(ba) << 0;
841rl += R_rl_0.
read(ba) << 0;
844aq += R_aq_0.
read(ba) << 0;
852 cp.
code() = std::string(
"//AMOMAXW\n");
855cp.
code() +=
"etiss_coverage_count(1, 178);\n";
857cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
858cp.
code() +=
"{ // block\n";
860cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
861cp.
code() +=
"} // block\n";
864cp.
code() +=
"etiss_coverage_count(1, 6786);\n";
865cp.
code() +=
"{ // block\n";
866cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
867cp.
code() +=
"etiss_coverage_count(4, 6743, 6742, 6741, 6739);\n";
868cp.
code() +=
"etiss_uint32 mem_val_0;\n";
869cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
870cp.
code() +=
"if (cpu->exception) { // conditional\n";
872cp.
code() +=
"{ // procedure\n";
873cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
875cp.
code() +=
"} // procedure\n";
877cp.
code() +=
"} // conditional\n";
878cp.
code() +=
"etiss_int32 res1 = mem_val_0;\n";
879cp.
code() +=
"etiss_coverage_count(3, 6748, 6747, 6746);\n";
880cp.
code() +=
"etiss_coverage_count(1, 6749);\n";
881if ((rd % 32ULL) != 0LL) {
882cp.
code() +=
"etiss_coverage_count(5, 6755, 6752, 6750, 6753, 6754);\n";
883cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = res1;\n";
884cp.
code() +=
"etiss_coverage_count(5, 6762, 6760, 6759, 6757, 6761);\n";
886cp.
code() +=
"etiss_uint32 res2 = (res1 < (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL]) : (res1);\n";
887cp.
code() +=
"etiss_coverage_count(12, 6780, 6779, 6772, 6764, 6771, 6769, 6768, 6766, 6777, 6776, 6774, 6778);\n";
888cp.
code() +=
"etiss_uint32 mem_val_1;\n";
889cp.
code() +=
"mem_val_1 = res2;\n";
890cp.
code() +=
"etiss_coverage_count(4, 6785, 6783, 6782, 6784);\n";
891cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
892cp.
code() +=
"if (cpu->exception) { // conditional\n";
894cp.
code() +=
"{ // procedure\n";
895cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
897cp.
code() +=
"} // procedure\n";
899cp.
code() +=
"} // conditional\n";
900cp.
code() +=
"} // block\n";
903cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
910 cp.
code() = std::string(
"//AMOMAXW\n");
913cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
925rd += R_rd_0.read(ba) << 0;
928rs1 += R_rs1_0.read(ba) << 0;
931rs2 += R_rs2_0.read(ba) << 0;
934rl += R_rl_0.read(ba) << 0;
937aq += R_aq_0.read(ba) << 0;
941 std::stringstream ss;
943ss <<
"amomaxw" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
953 (uint32_t) 0xc000202f,
954 (uint32_t) 0xf800707f,
966rd += R_rd_0.
read(ba) << 0;
969rs1 += R_rs1_0.
read(ba) << 0;
972rs2 += R_rs2_0.
read(ba) << 0;
975rl += R_rl_0.
read(ba) << 0;
978aq += R_aq_0.
read(ba) << 0;
986 cp.
code() = std::string(
"//AMOMINUW\n");
989cp.
code() +=
"etiss_coverage_count(1, 179);\n";
991cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
992cp.
code() +=
"{ // block\n";
994cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
995cp.
code() +=
"} // block\n";
998cp.
code() +=
"etiss_coverage_count(1, 6838);\n";
999cp.
code() +=
"{ // block\n";
1000cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
1001cp.
code() +=
"etiss_coverage_count(4, 6793, 6792, 6791, 6789);\n";
1002cp.
code() +=
"etiss_uint32 mem_val_0;\n";
1003cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
1004cp.
code() +=
"if (cpu->exception) { // conditional\n";
1006cp.
code() +=
"{ // procedure\n";
1007cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1009cp.
code() +=
"} // procedure\n";
1011cp.
code() +=
"} // conditional\n";
1012cp.
code() +=
"etiss_uint32 res1 = mem_val_0;\n";
1013cp.
code() +=
"etiss_coverage_count(3, 6798, 6797, 6796);\n";
1014cp.
code() +=
"etiss_coverage_count(1, 6799);\n";
1015if ((rd % 32ULL) != 0LL) {
1016cp.
code() +=
"etiss_coverage_count(5, 6805, 6802, 6800, 6803, 6804);\n";
1017cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = (etiss_int32)(res1);\n";
1018cp.
code() +=
"etiss_coverage_count(6, 6814, 6810, 6809, 6807, 6813, 6811);\n";
1020cp.
code() +=
"etiss_uint32 res2 = (res1 > (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL]) : (res1);\n";
1021cp.
code() +=
"etiss_coverage_count(12, 6832, 6831, 6824, 6816, 6823, 6821, 6820, 6818, 6829, 6828, 6826, 6830);\n";
1022cp.
code() +=
"etiss_uint32 mem_val_1;\n";
1023cp.
code() +=
"mem_val_1 = res2;\n";
1024cp.
code() +=
"etiss_coverage_count(4, 6837, 6835, 6834, 6836);\n";
1025cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
1026cp.
code() +=
"if (cpu->exception) { // conditional\n";
1028cp.
code() +=
"{ // procedure\n";
1029cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1031cp.
code() +=
"} // procedure\n";
1033cp.
code() +=
"} // conditional\n";
1034cp.
code() +=
"} // block\n";
1037cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
1044 cp.
code() = std::string(
"//AMOMINUW\n");
1047cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1059rd += R_rd_0.read(ba) << 0;
1062rs1 += R_rs1_0.read(ba) << 0;
1065rs2 += R_rs2_0.read(ba) << 0;
1068rl += R_rl_0.read(ba) << 0;
1071aq += R_aq_0.read(ba) << 0;
1075 std::stringstream ss;
1077ss <<
"amominuw" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
1087 (uint32_t) 0xe000202f,
1088 (uint32_t) 0xf800707f,
1100rd += R_rd_0.
read(ba) << 0;
1103rs1 += R_rs1_0.
read(ba) << 0;
1106rs2 += R_rs2_0.
read(ba) << 0;
1109rl += R_rl_0.
read(ba) << 0;
1112aq += R_aq_0.
read(ba) << 0;
1120 cp.
code() = std::string(
"//AMOMAXUW\n");
1123cp.
code() +=
"etiss_coverage_count(1, 180);\n";
1125cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
1126cp.
code() +=
"{ // block\n";
1128cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1129cp.
code() +=
"} // block\n";
1132cp.
code() +=
"etiss_coverage_count(1, 6890);\n";
1133cp.
code() +=
"{ // block\n";
1134cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
1135cp.
code() +=
"etiss_coverage_count(4, 6845, 6844, 6843, 6841);\n";
1136cp.
code() +=
"etiss_uint32 mem_val_0;\n";
1137cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
1138cp.
code() +=
"if (cpu->exception) { // conditional\n";
1140cp.
code() +=
"{ // procedure\n";
1141cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1143cp.
code() +=
"} // procedure\n";
1145cp.
code() +=
"} // conditional\n";
1146cp.
code() +=
"etiss_uint32 res1 = mem_val_0;\n";
1147cp.
code() +=
"etiss_coverage_count(3, 6850, 6849, 6848);\n";
1148cp.
code() +=
"etiss_coverage_count(1, 6851);\n";
1149if ((rd % 32ULL) != 0LL) {
1150cp.
code() +=
"etiss_coverage_count(5, 6857, 6854, 6852, 6855, 6856);\n";
1151cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = (etiss_int32)(res1);\n";
1152cp.
code() +=
"etiss_coverage_count(6, 6866, 6862, 6861, 6859, 6865, 6863);\n";
1154cp.
code() +=
"etiss_uint32 res2 = (res1 < (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL]) : (res1);\n";
1155cp.
code() +=
"etiss_coverage_count(12, 6884, 6883, 6876, 6868, 6875, 6873, 6872, 6870, 6881, 6880, 6878, 6882);\n";
1156cp.
code() +=
"etiss_uint32 mem_val_1;\n";
1157cp.
code() +=
"mem_val_1 = res2;\n";
1158cp.
code() +=
"etiss_coverage_count(4, 6889, 6887, 6886, 6888);\n";
1159cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
1160cp.
code() +=
"if (cpu->exception) { // conditional\n";
1162cp.
code() +=
"{ // procedure\n";
1163cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1165cp.
code() +=
"} // procedure\n";
1167cp.
code() +=
"} // conditional\n";
1168cp.
code() +=
"} // block\n";
1171cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
1178 cp.
code() = std::string(
"//AMOMAXUW\n");
1181cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1193rd += R_rd_0.read(ba) << 0;
1196rs1 += R_rs1_0.read(ba) << 0;
1199rs2 += R_rs2_0.read(ba) << 0;
1202rl += R_rl_0.read(ba) << 0;
1205aq += R_aq_0.read(ba) << 0;
1209 std::stringstream ss;
1211ss <<
"amomaxuw" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
static InstructionDefinition amominw_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amominw",(uint32_t) 0x8000202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOMINW\n");cp.code()+="etiss_coverage_count(1, 177);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6736);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 6693, 6692, 6691, 6689);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int32 res1 = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 6698, 6697, 6696);\n";cp.code()+="etiss_coverage_count(1, 6699);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 6705, 6702, 6700, 6703, 6704);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res1;\n";cp.code()+="etiss_coverage_count(5, 6712, 6710, 6709, 6707, 6711);\n";} cp.code()+="etiss_uint32 res2 = (res1 > (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) ? (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) : (res1);\n";cp.code()+="etiss_coverage_count(12, 6730, 6729, 6722, 6714, 6721, 6719, 6718, 6716, 6727, 6726, 6724, 6728);\n";cp.code()+="etiss_uint32 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(4, 6735, 6733, 6732, 6734);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOMINW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amominw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amomaxw_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amomaxw",(uint32_t) 0xa000202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOMAXW\n");cp.code()+="etiss_coverage_count(1, 178);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6786);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 6743, 6742, 6741, 6739);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int32 res1 = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 6748, 6747, 6746);\n";cp.code()+="etiss_coverage_count(1, 6749);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 6755, 6752, 6750, 6753, 6754);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res1;\n";cp.code()+="etiss_coverage_count(5, 6762, 6760, 6759, 6757, 6761);\n";} cp.code()+="etiss_uint32 res2 = (res1 < (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) ? (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) : (res1);\n";cp.code()+="etiss_coverage_count(12, 6780, 6779, 6772, 6764, 6771, 6769, 6768, 6766, 6777, 6776, 6774, 6778);\n";cp.code()+="etiss_uint32 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(4, 6785, 6783, 6782, 6784);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOMAXW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amomaxw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amominuw_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amominuw",(uint32_t) 0xc000202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOMINUW\n");cp.code()+="etiss_coverage_count(1, 179);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6838);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 6793, 6792, 6791, 6789);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint32 res1 = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 6798, 6797, 6796);\n";cp.code()+="etiss_coverage_count(1, 6799);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 6805, 6802, 6800, 6803, 6804);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int32)(res1);\n";cp.code()+="etiss_coverage_count(6, 6814, 6810, 6809, 6807, 6813, 6811);\n";} cp.code()+="etiss_uint32 res2 = (res1 > (etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) ? (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) : (res1);\n";cp.code()+="etiss_coverage_count(12, 6832, 6831, 6824, 6816, 6823, 6821, 6820, 6818, 6829, 6828, 6826, 6830);\n";cp.code()+="etiss_uint32 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(4, 6837, 6835, 6834, 6836);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOMINUW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amominuw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amoswapw_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoswapw",(uint32_t) 0x800202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOSWAPW\n");cp.code()+="etiss_coverage_count(1, 172);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6522);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 6489, 6488, 6487, 6485);\n";cp.code()+="etiss_coverage_count(1, 6490);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 6496, 6493, 6491, 6494, 6495);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(((etiss_int32)(mem_val_0)));\n";cp.code()+="etiss_coverage_count(9, 6510, 6501, 6500, 6498, 6509, 6506, 6504, 6503, 6507);\n";} cp.code()+="etiss_uint32 mem_val_1;\n";cp.code()+="mem_val_1 = (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(7, 6521, 6513, 6512, 6520, 6518, 6517, 6515);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOSWAPW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoswapw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amoorw_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoorw",(uint32_t) 0x4000202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOORW\n");cp.code()+="etiss_coverage_count(1, 176);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6686);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 6652, 6651, 6650, 6648);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int32 res1 = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 6657, 6656, 6655);\n";cp.code()+="etiss_coverage_count(1, 6658);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 6664, 6661, 6659, 6662, 6663);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res1;\n";cp.code()+="etiss_coverage_count(5, 6671, 6669, 6668, 6666, 6670);\n";} cp.code()+="etiss_uint32 res2 = res1 | *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(6, 6680, 6679, 6673, 6678, 6677, 6675);\n";cp.code()+="etiss_uint32 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(4, 6685, 6683, 6682, 6684);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOORW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoorw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amomaxuw_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amomaxuw",(uint32_t) 0xe000202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOMAXUW\n");cp.code()+="etiss_coverage_count(1, 180);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6890);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 6845, 6844, 6843, 6841);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint32 res1 = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 6850, 6849, 6848);\n";cp.code()+="etiss_coverage_count(1, 6851);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 6857, 6854, 6852, 6855, 6856);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int32)(res1);\n";cp.code()+="etiss_coverage_count(6, 6866, 6862, 6861, 6859, 6865, 6863);\n";} cp.code()+="etiss_uint32 res2 = (res1 < (etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) ? (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) : (res1);\n";cp.code()+="etiss_coverage_count(12, 6884, 6883, 6876, 6868, 6875, 6873, 6872, 6870, 6881, 6880, 6878, 6882);\n";cp.code()+="etiss_uint32 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(4, 6889, 6887, 6886, 6888);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOMAXUW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amomaxuw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amoandw_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoandw",(uint32_t) 0x6000202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOANDW\n");cp.code()+="etiss_coverage_count(1, 175);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6645);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 6611, 6610, 6609, 6607);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int32 res1 = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 6616, 6615, 6614);\n";cp.code()+="etiss_coverage_count(1, 6617);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 6623, 6620, 6618, 6621, 6622);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res1;\n";cp.code()+="etiss_coverage_count(5, 6630, 6628, 6627, 6625, 6629);\n";} cp.code()+="etiss_uint32 res2 = res1 & *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(6, 6639, 6638, 6632, 6637, 6636, 6634);\n";cp.code()+="etiss_uint32 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(4, 6644, 6642, 6641, 6643);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOANDW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoandw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amoaddw_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoaddw",(uint32_t) 0x00202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOADDW\n");cp.code()+="etiss_coverage_count(1, 173);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6563);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 6529, 6528, 6527, 6525);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int32 res1 = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 6534, 6533, 6532);\n";cp.code()+="etiss_coverage_count(1, 6535);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 6541, 6538, 6536, 6539, 6540);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res1;\n";cp.code()+="etiss_coverage_count(5, 6548, 6546, 6545, 6543, 6547);\n";} cp.code()+="etiss_uint32 res2 = res1 + *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(6, 6557, 6556, 6550, 6555, 6554, 6552);\n";cp.code()+="etiss_uint32 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(4, 6562, 6560, 6559, 6561);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOADDW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoaddw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amoxorw_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoxorw",(uint32_t) 0x2000202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOXORW\n");cp.code()+="etiss_coverage_count(1, 174);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6604);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 6570, 6569, 6568, 6566);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int32 res1 = mem_val_0;\n";cp.code()+="etiss_coverage_count(3, 6575, 6574, 6573);\n";cp.code()+="etiss_coverage_count(1, 6576);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 6582, 6579, 6577, 6580, 6581);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res1;\n";cp.code()+="etiss_coverage_count(5, 6589, 6587, 6586, 6584, 6588);\n";} cp.code()+="etiss_uint32 res2 = res1 ^ *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(6, 6598, 6597, 6591, 6596, 6595, 6593);\n";cp.code()+="etiss_uint32 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(4, 6603, 6601, 6600, 6602);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOXORW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoxorw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
Contains a small code snipped.
@ APPENDEDRETURNINGREQUIRED
RegisterSet & getAffectedRegisters()
void append(const CodePart &part, CodePart::TYPE type)
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Reading through it will only return bits within the range.
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
this class contains parameters that persist in between instruction lookpus/translation within a trans...
uint64_t current_address_
start address of current instruction
holds information and translation callbacks for an instruction.