20 (uint64_t) 0xf800707f,
32rd += R_rd_0.
read(ba) << 0;
35rs1 += R_rs1_0.
read(ba) << 0;
38rs2 += R_rs2_0.
read(ba) << 0;
41rl += R_rl_0.
read(ba) << 0;
44aq += R_aq_0.
read(ba) << 0;
52 cp.
code() = std::string(
"//AMOSWAPW\n");
55cp.
code() +=
"etiss_coverage_count(1, 172);\n";
57cp.
code() +=
"etiss_coverage_count(1, 1189);\n";
58cp.
code() +=
"{ // block\n";
60cp.
code() +=
"etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
61cp.
code() +=
"} // block\n";
64cp.
code() +=
"etiss_coverage_count(1, 6829);\n";
65cp.
code() +=
"{ // block\n";
66cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
67cp.
code() +=
"etiss_coverage_count(4, 6790, 6789, 6788, 6786);\n";
68cp.
code() +=
"etiss_coverage_count(1, 6791);\n";
69if ((rd % 32ULL) != 0LL) {
70cp.
code() +=
"etiss_coverage_count(5, 6797, 6794, 6792, 6795, 6796);\n";
71cp.
code() +=
"etiss_uint32 mem_val_0;\n";
72cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
73cp.
code() +=
"if (cpu->exception) { // conditional\n";
75cp.
code() +=
"{ // procedure\n";
76cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
78cp.
code() +=
"} // procedure\n";
80cp.
code() +=
"} // conditional\n";
81cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = (etiss_int64)(((etiss_int32)(mem_val_0)));\n";
82cp.
code() +=
"etiss_coverage_count(11, 6814, 6802, 6801, 6799, 6813, 6810, 6808, 6806, 6804, 6805, 6811);\n";
84cp.
code() +=
"etiss_uint32 mem_val_1;\n";
85cp.
code() +=
"mem_val_1 = (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL]);\n";
86cp.
code() +=
"etiss_coverage_count(9, 6828, 6820, 6818, 6816, 6817, 6827, 6825, 6824, 6822);\n";
87cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
88cp.
code() +=
"if (cpu->exception) { // conditional\n";
90cp.
code() +=
"{ // procedure\n";
91cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
93cp.
code() +=
"} // procedure\n";
95cp.
code() +=
"} // conditional\n";
96cp.
code() +=
"} // block\n";
99cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
106 cp.
code() = std::string(
"//AMOSWAPW\n");
109cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
121rd += R_rd_0.read(ba) << 0;
124rs1 += R_rs1_0.read(ba) << 0;
127rs2 += R_rs2_0.read(ba) << 0;
130rl += R_rl_0.read(ba) << 0;
133aq += R_aq_0.read(ba) << 0;
137 std::stringstream ss;
139ss <<
"amoswapw" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
150 (uint64_t) 0xf800707f,
162rd += R_rd_0.
read(ba) << 0;
165rs1 += R_rs1_0.
read(ba) << 0;
168rs2 += R_rs2_0.
read(ba) << 0;
171rl += R_rl_0.
read(ba) << 0;
174aq += R_aq_0.
read(ba) << 0;
182 cp.
code() = std::string(
"//AMOADDW\n");
185cp.
code() +=
"etiss_coverage_count(1, 173);\n";
187cp.
code() +=
"etiss_coverage_count(1, 1189);\n";
188cp.
code() +=
"{ // block\n";
190cp.
code() +=
"etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
191cp.
code() +=
"} // block\n";
194cp.
code() +=
"etiss_coverage_count(1, 6876);\n";
195cp.
code() +=
"{ // block\n";
196cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
197cp.
code() +=
"etiss_coverage_count(4, 6836, 6835, 6834, 6832);\n";
198cp.
code() +=
"etiss_uint32 mem_val_0;\n";
199cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
200cp.
code() +=
"if (cpu->exception) { // conditional\n";
202cp.
code() +=
"{ // procedure\n";
203cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
205cp.
code() +=
"} // procedure\n";
207cp.
code() +=
"} // conditional\n";
208cp.
code() +=
"etiss_int32 res1 = mem_val_0;\n";
209cp.
code() +=
"etiss_coverage_count(5, 6844, 6843, 6841, 6839, 6840);\n";
210cp.
code() +=
"etiss_coverage_count(1, 6845);\n";
211if ((rd % 32ULL) != 0LL) {
212cp.
code() +=
"etiss_coverage_count(5, 6851, 6848, 6846, 6849, 6850);\n";
213cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = res1;\n";
214cp.
code() +=
"etiss_coverage_count(5, 6858, 6856, 6855, 6853, 6857);\n";
216cp.
code() +=
"etiss_uint32 res2 = res1 + *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL];\n";
217cp.
code() +=
"etiss_coverage_count(6, 6867, 6866, 6860, 6865, 6864, 6862);\n";
218cp.
code() +=
"etiss_uint32 mem_val_1;\n";
219cp.
code() +=
"mem_val_1 = res2;\n";
220cp.
code() +=
"etiss_coverage_count(6, 6875, 6873, 6871, 6869, 6870, 6874);\n";
221cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
222cp.
code() +=
"if (cpu->exception) { // conditional\n";
224cp.
code() +=
"{ // procedure\n";
225cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
227cp.
code() +=
"} // procedure\n";
229cp.
code() +=
"} // conditional\n";
230cp.
code() +=
"} // block\n";
233cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
240 cp.
code() = std::string(
"//AMOADDW\n");
243cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
255rd += R_rd_0.read(ba) << 0;
258rs1 += R_rs1_0.read(ba) << 0;
261rs2 += R_rs2_0.read(ba) << 0;
264rl += R_rl_0.read(ba) << 0;
267aq += R_aq_0.read(ba) << 0;
271 std::stringstream ss;
273ss <<
"amoaddw" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
283 (uint64_t) 0x2000202f,
284 (uint64_t) 0xf800707f,
296rd += R_rd_0.
read(ba) << 0;
299rs1 += R_rs1_0.
read(ba) << 0;
302rs2 += R_rs2_0.
read(ba) << 0;
305rl += R_rl_0.
read(ba) << 0;
308aq += R_aq_0.
read(ba) << 0;
316 cp.
code() = std::string(
"//AMOXORW\n");
319cp.
code() +=
"etiss_coverage_count(1, 174);\n";
321cp.
code() +=
"etiss_coverage_count(1, 1189);\n";
322cp.
code() +=
"{ // block\n";
324cp.
code() +=
"etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
325cp.
code() +=
"} // block\n";
328cp.
code() +=
"etiss_coverage_count(1, 6923);\n";
329cp.
code() +=
"{ // block\n";
330cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
331cp.
code() +=
"etiss_coverage_count(4, 6883, 6882, 6881, 6879);\n";
332cp.
code() +=
"etiss_uint32 mem_val_0;\n";
333cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
334cp.
code() +=
"if (cpu->exception) { // conditional\n";
336cp.
code() +=
"{ // procedure\n";
337cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
339cp.
code() +=
"} // procedure\n";
341cp.
code() +=
"} // conditional\n";
342cp.
code() +=
"etiss_int32 res1 = mem_val_0;\n";
343cp.
code() +=
"etiss_coverage_count(5, 6891, 6890, 6888, 6886, 6887);\n";
344cp.
code() +=
"etiss_coverage_count(1, 6892);\n";
345if ((rd % 32ULL) != 0LL) {
346cp.
code() +=
"etiss_coverage_count(5, 6898, 6895, 6893, 6896, 6897);\n";
347cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = res1;\n";
348cp.
code() +=
"etiss_coverage_count(5, 6905, 6903, 6902, 6900, 6904);\n";
350cp.
code() +=
"etiss_uint32 res2 = res1 ^ *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL];\n";
351cp.
code() +=
"etiss_coverage_count(6, 6914, 6913, 6907, 6912, 6911, 6909);\n";
352cp.
code() +=
"etiss_uint32 mem_val_1;\n";
353cp.
code() +=
"mem_val_1 = res2;\n";
354cp.
code() +=
"etiss_coverage_count(6, 6922, 6920, 6918, 6916, 6917, 6921);\n";
355cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
356cp.
code() +=
"if (cpu->exception) { // conditional\n";
358cp.
code() +=
"{ // procedure\n";
359cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
361cp.
code() +=
"} // procedure\n";
363cp.
code() +=
"} // conditional\n";
364cp.
code() +=
"} // block\n";
367cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
374 cp.
code() = std::string(
"//AMOXORW\n");
377cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
389rd += R_rd_0.read(ba) << 0;
392rs1 += R_rs1_0.read(ba) << 0;
395rs2 += R_rs2_0.read(ba) << 0;
398rl += R_rl_0.read(ba) << 0;
401aq += R_aq_0.read(ba) << 0;
405 std::stringstream ss;
407ss <<
"amoxorw" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
417 (uint64_t) 0x6000202f,
418 (uint64_t) 0xf800707f,
430rd += R_rd_0.
read(ba) << 0;
433rs1 += R_rs1_0.
read(ba) << 0;
436rs2 += R_rs2_0.
read(ba) << 0;
439rl += R_rl_0.
read(ba) << 0;
442aq += R_aq_0.
read(ba) << 0;
450 cp.
code() = std::string(
"//AMOANDW\n");
453cp.
code() +=
"etiss_coverage_count(1, 175);\n";
455cp.
code() +=
"etiss_coverage_count(1, 1189);\n";
456cp.
code() +=
"{ // block\n";
458cp.
code() +=
"etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
459cp.
code() +=
"} // block\n";
462cp.
code() +=
"etiss_coverage_count(1, 6970);\n";
463cp.
code() +=
"{ // block\n";
464cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
465cp.
code() +=
"etiss_coverage_count(4, 6930, 6929, 6928, 6926);\n";
466cp.
code() +=
"etiss_uint32 mem_val_0;\n";
467cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
468cp.
code() +=
"if (cpu->exception) { // conditional\n";
470cp.
code() +=
"{ // procedure\n";
471cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
473cp.
code() +=
"} // procedure\n";
475cp.
code() +=
"} // conditional\n";
476cp.
code() +=
"etiss_int32 res1 = mem_val_0;\n";
477cp.
code() +=
"etiss_coverage_count(5, 6938, 6937, 6935, 6933, 6934);\n";
478cp.
code() +=
"etiss_coverage_count(1, 6939);\n";
479if ((rd % 32ULL) != 0LL) {
480cp.
code() +=
"etiss_coverage_count(5, 6945, 6942, 6940, 6943, 6944);\n";
481cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = res1;\n";
482cp.
code() +=
"etiss_coverage_count(5, 6952, 6950, 6949, 6947, 6951);\n";
484cp.
code() +=
"etiss_uint32 res2 = res1 & *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL];\n";
485cp.
code() +=
"etiss_coverage_count(6, 6961, 6960, 6954, 6959, 6958, 6956);\n";
486cp.
code() +=
"etiss_uint32 mem_val_1;\n";
487cp.
code() +=
"mem_val_1 = res2;\n";
488cp.
code() +=
"etiss_coverage_count(6, 6969, 6967, 6965, 6963, 6964, 6968);\n";
489cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
490cp.
code() +=
"if (cpu->exception) { // conditional\n";
492cp.
code() +=
"{ // procedure\n";
493cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
495cp.
code() +=
"} // procedure\n";
497cp.
code() +=
"} // conditional\n";
498cp.
code() +=
"} // block\n";
501cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
508 cp.
code() = std::string(
"//AMOANDW\n");
511cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
523rd += R_rd_0.read(ba) << 0;
526rs1 += R_rs1_0.read(ba) << 0;
529rs2 += R_rs2_0.read(ba) << 0;
532rl += R_rl_0.read(ba) << 0;
535aq += R_aq_0.read(ba) << 0;
539 std::stringstream ss;
541ss <<
"amoandw" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
551 (uint64_t) 0x4000202f,
552 (uint64_t) 0xf800707f,
564rd += R_rd_0.
read(ba) << 0;
567rs1 += R_rs1_0.
read(ba) << 0;
570rs2 += R_rs2_0.
read(ba) << 0;
573rl += R_rl_0.
read(ba) << 0;
576aq += R_aq_0.
read(ba) << 0;
584 cp.
code() = std::string(
"//AMOORW\n");
587cp.
code() +=
"etiss_coverage_count(1, 176);\n";
589cp.
code() +=
"etiss_coverage_count(1, 1189);\n";
590cp.
code() +=
"{ // block\n";
592cp.
code() +=
"etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
593cp.
code() +=
"} // block\n";
596cp.
code() +=
"etiss_coverage_count(1, 7017);\n";
597cp.
code() +=
"{ // block\n";
598cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
599cp.
code() +=
"etiss_coverage_count(4, 6977, 6976, 6975, 6973);\n";
600cp.
code() +=
"etiss_uint32 mem_val_0;\n";
601cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
602cp.
code() +=
"if (cpu->exception) { // conditional\n";
604cp.
code() +=
"{ // procedure\n";
605cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
607cp.
code() +=
"} // procedure\n";
609cp.
code() +=
"} // conditional\n";
610cp.
code() +=
"etiss_int32 res1 = mem_val_0;\n";
611cp.
code() +=
"etiss_coverage_count(5, 6985, 6984, 6982, 6980, 6981);\n";
612cp.
code() +=
"etiss_coverage_count(1, 6986);\n";
613if ((rd % 32ULL) != 0LL) {
614cp.
code() +=
"etiss_coverage_count(5, 6992, 6989, 6987, 6990, 6991);\n";
615cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = res1;\n";
616cp.
code() +=
"etiss_coverage_count(5, 6999, 6997, 6996, 6994, 6998);\n";
618cp.
code() +=
"etiss_uint32 res2 = res1 | *((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL];\n";
619cp.
code() +=
"etiss_coverage_count(6, 7008, 7007, 7001, 7006, 7005, 7003);\n";
620cp.
code() +=
"etiss_uint32 mem_val_1;\n";
621cp.
code() +=
"mem_val_1 = res2;\n";
622cp.
code() +=
"etiss_coverage_count(6, 7016, 7014, 7012, 7010, 7011, 7015);\n";
623cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
624cp.
code() +=
"if (cpu->exception) { // conditional\n";
626cp.
code() +=
"{ // procedure\n";
627cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
629cp.
code() +=
"} // procedure\n";
631cp.
code() +=
"} // conditional\n";
632cp.
code() +=
"} // block\n";
635cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
642 cp.
code() = std::string(
"//AMOORW\n");
645cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
657rd += R_rd_0.read(ba) << 0;
660rs1 += R_rs1_0.read(ba) << 0;
663rs2 += R_rs2_0.read(ba) << 0;
666rl += R_rl_0.read(ba) << 0;
669aq += R_aq_0.read(ba) << 0;
673 std::stringstream ss;
675ss <<
"amoorw" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
685 (uint64_t) 0x8000202f,
686 (uint64_t) 0xf800707f,
698rd += R_rd_0.
read(ba) << 0;
701rs1 += R_rs1_0.
read(ba) << 0;
704rs2 += R_rs2_0.
read(ba) << 0;
707rl += R_rl_0.
read(ba) << 0;
710aq += R_aq_0.
read(ba) << 0;
718 cp.
code() = std::string(
"//AMOMINW\n");
721cp.
code() +=
"etiss_coverage_count(1, 177);\n";
723cp.
code() +=
"etiss_coverage_count(1, 1189);\n";
724cp.
code() +=
"{ // block\n";
726cp.
code() +=
"etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
727cp.
code() +=
"} // block\n";
730cp.
code() +=
"etiss_coverage_count(1, 7073);\n";
731cp.
code() +=
"{ // block\n";
732cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
733cp.
code() +=
"etiss_coverage_count(4, 7024, 7023, 7022, 7020);\n";
734cp.
code() +=
"etiss_uint32 mem_val_0;\n";
735cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
736cp.
code() +=
"if (cpu->exception) { // conditional\n";
738cp.
code() +=
"{ // procedure\n";
739cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
741cp.
code() +=
"} // procedure\n";
743cp.
code() +=
"} // conditional\n";
744cp.
code() +=
"etiss_int32 res1 = mem_val_0;\n";
745cp.
code() +=
"etiss_coverage_count(5, 7032, 7031, 7029, 7027, 7028);\n";
746cp.
code() +=
"etiss_coverage_count(1, 7033);\n";
747if ((rd % 32ULL) != 0LL) {
748cp.
code() +=
"etiss_coverage_count(5, 7039, 7036, 7034, 7037, 7038);\n";
749cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = res1;\n";
750cp.
code() +=
"etiss_coverage_count(5, 7046, 7044, 7043, 7041, 7045);\n";
752cp.
code() +=
"etiss_uint32 res2 = (res1 > (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL]) : (res1);\n";
753cp.
code() +=
"etiss_coverage_count(12, 7064, 7063, 7056, 7048, 7055, 7053, 7052, 7050, 7061, 7060, 7058, 7062);\n";
754cp.
code() +=
"etiss_uint32 mem_val_1;\n";
755cp.
code() +=
"mem_val_1 = res2;\n";
756cp.
code() +=
"etiss_coverage_count(6, 7072, 7070, 7068, 7066, 7067, 7071);\n";
757cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
758cp.
code() +=
"if (cpu->exception) { // conditional\n";
760cp.
code() +=
"{ // procedure\n";
761cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
763cp.
code() +=
"} // procedure\n";
765cp.
code() +=
"} // conditional\n";
766cp.
code() +=
"} // block\n";
769cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
776 cp.
code() = std::string(
"//AMOMINW\n");
779cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
791rd += R_rd_0.read(ba) << 0;
794rs1 += R_rs1_0.read(ba) << 0;
797rs2 += R_rs2_0.read(ba) << 0;
800rl += R_rl_0.read(ba) << 0;
803aq += R_aq_0.read(ba) << 0;
807 std::stringstream ss;
809ss <<
"amominw" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
819 (uint64_t) 0xa000202f,
820 (uint64_t) 0xf800707f,
832rd += R_rd_0.
read(ba) << 0;
835rs1 += R_rs1_0.
read(ba) << 0;
838rs2 += R_rs2_0.
read(ba) << 0;
841rl += R_rl_0.
read(ba) << 0;
844aq += R_aq_0.
read(ba) << 0;
852 cp.
code() = std::string(
"//AMOMAXW\n");
855cp.
code() +=
"etiss_coverage_count(1, 178);\n";
857cp.
code() +=
"etiss_coverage_count(1, 1189);\n";
858cp.
code() +=
"{ // block\n";
860cp.
code() +=
"etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
861cp.
code() +=
"} // block\n";
864cp.
code() +=
"etiss_coverage_count(1, 7129);\n";
865cp.
code() +=
"{ // block\n";
866cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
867cp.
code() +=
"etiss_coverage_count(4, 7080, 7079, 7078, 7076);\n";
868cp.
code() +=
"etiss_uint32 mem_val_0;\n";
869cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
870cp.
code() +=
"if (cpu->exception) { // conditional\n";
872cp.
code() +=
"{ // procedure\n";
873cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
875cp.
code() +=
"} // procedure\n";
877cp.
code() +=
"} // conditional\n";
878cp.
code() +=
"etiss_int32 res1 = mem_val_0;\n";
879cp.
code() +=
"etiss_coverage_count(5, 7088, 7087, 7085, 7083, 7084);\n";
880cp.
code() +=
"etiss_coverage_count(1, 7089);\n";
881if ((rd % 32ULL) != 0LL) {
882cp.
code() +=
"etiss_coverage_count(5, 7095, 7092, 7090, 7093, 7094);\n";
883cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = res1;\n";
884cp.
code() +=
"etiss_coverage_count(5, 7102, 7100, 7099, 7097, 7101);\n";
886cp.
code() +=
"etiss_uint32 res2 = (res1 < (etiss_int32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL]) : (res1);\n";
887cp.
code() +=
"etiss_coverage_count(12, 7120, 7119, 7112, 7104, 7111, 7109, 7108, 7106, 7117, 7116, 7114, 7118);\n";
888cp.
code() +=
"etiss_uint32 mem_val_1;\n";
889cp.
code() +=
"mem_val_1 = res2;\n";
890cp.
code() +=
"etiss_coverage_count(6, 7128, 7126, 7124, 7122, 7123, 7127);\n";
891cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
892cp.
code() +=
"if (cpu->exception) { // conditional\n";
894cp.
code() +=
"{ // procedure\n";
895cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
897cp.
code() +=
"} // procedure\n";
899cp.
code() +=
"} // conditional\n";
900cp.
code() +=
"} // block\n";
903cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
910 cp.
code() = std::string(
"//AMOMAXW\n");
913cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
925rd += R_rd_0.read(ba) << 0;
928rs1 += R_rs1_0.read(ba) << 0;
931rs2 += R_rs2_0.read(ba) << 0;
934rl += R_rl_0.read(ba) << 0;
937aq += R_aq_0.read(ba) << 0;
941 std::stringstream ss;
943ss <<
"amomaxw" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
953 (uint64_t) 0xc000202f,
954 (uint64_t) 0xf800707f,
966rd += R_rd_0.
read(ba) << 0;
969rs1 += R_rs1_0.
read(ba) << 0;
972rs2 += R_rs2_0.
read(ba) << 0;
975rl += R_rl_0.
read(ba) << 0;
978aq += R_aq_0.
read(ba) << 0;
986 cp.
code() = std::string(
"//AMOMINUW\n");
989cp.
code() +=
"etiss_coverage_count(1, 179);\n";
991cp.
code() +=
"etiss_coverage_count(1, 1189);\n";
992cp.
code() +=
"{ // block\n";
994cp.
code() +=
"etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
995cp.
code() +=
"} // block\n";
998cp.
code() +=
"etiss_coverage_count(1, 7187);\n";
999cp.
code() +=
"{ // block\n";
1000cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
1001cp.
code() +=
"etiss_coverage_count(4, 7136, 7135, 7134, 7132);\n";
1002cp.
code() +=
"etiss_uint32 mem_val_0;\n";
1003cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
1004cp.
code() +=
"if (cpu->exception) { // conditional\n";
1006cp.
code() +=
"{ // procedure\n";
1007cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1009cp.
code() +=
"} // procedure\n";
1011cp.
code() +=
"} // conditional\n";
1012cp.
code() +=
"etiss_uint32 res1 = mem_val_0;\n";
1013cp.
code() +=
"etiss_coverage_count(5, 7144, 7143, 7141, 7139, 7140);\n";
1014cp.
code() +=
"etiss_coverage_count(1, 7145);\n";
1015if ((rd % 32ULL) != 0LL) {
1016cp.
code() +=
"etiss_coverage_count(5, 7151, 7148, 7146, 7149, 7150);\n";
1017cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = (etiss_int32)(res1);\n";
1018cp.
code() +=
"etiss_coverage_count(6, 7160, 7156, 7155, 7153, 7159, 7157);\n";
1020cp.
code() +=
"etiss_uint32 res2 = (res1 > (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL]) : (res1);\n";
1021cp.
code() +=
"etiss_coverage_count(12, 7178, 7177, 7170, 7162, 7169, 7167, 7166, 7164, 7175, 7174, 7172, 7176);\n";
1022cp.
code() +=
"etiss_uint32 mem_val_1;\n";
1023cp.
code() +=
"mem_val_1 = res2;\n";
1024cp.
code() +=
"etiss_coverage_count(6, 7186, 7184, 7182, 7180, 7181, 7185);\n";
1025cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
1026cp.
code() +=
"if (cpu->exception) { // conditional\n";
1028cp.
code() +=
"{ // procedure\n";
1029cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1031cp.
code() +=
"} // procedure\n";
1033cp.
code() +=
"} // conditional\n";
1034cp.
code() +=
"} // block\n";
1037cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
1044 cp.
code() = std::string(
"//AMOMINUW\n");
1047cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1059rd += R_rd_0.read(ba) << 0;
1062rs1 += R_rs1_0.read(ba) << 0;
1065rs2 += R_rs2_0.read(ba) << 0;
1068rl += R_rl_0.read(ba) << 0;
1071aq += R_aq_0.read(ba) << 0;
1075 std::stringstream ss;
1077ss <<
"amominuw" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
1087 (uint64_t) 0xe000202f,
1088 (uint64_t) 0xf800707f,
1100rd += R_rd_0.
read(ba) << 0;
1103rs1 += R_rs1_0.
read(ba) << 0;
1106rs2 += R_rs2_0.
read(ba) << 0;
1109rl += R_rl_0.
read(ba) << 0;
1112aq += R_aq_0.
read(ba) << 0;
1120 cp.
code() = std::string(
"//AMOMAXUW\n");
1123cp.
code() +=
"etiss_coverage_count(1, 180);\n";
1125cp.
code() +=
"etiss_coverage_count(1, 1189);\n";
1126cp.
code() +=
"{ // block\n";
1128cp.
code() +=
"etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
1129cp.
code() +=
"} // block\n";
1132cp.
code() +=
"etiss_coverage_count(1, 7245);\n";
1133cp.
code() +=
"{ // block\n";
1134cp.
code() +=
"etiss_uint64 offs = *((RV64IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) +
"ULL];\n";
1135cp.
code() +=
"etiss_coverage_count(4, 7194, 7193, 7192, 7190);\n";
1136cp.
code() +=
"etiss_uint32 mem_val_0;\n";
1137cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
1138cp.
code() +=
"if (cpu->exception) { // conditional\n";
1140cp.
code() +=
"{ // procedure\n";
1141cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1143cp.
code() +=
"} // procedure\n";
1145cp.
code() +=
"} // conditional\n";
1146cp.
code() +=
"etiss_uint32 res1 = mem_val_0;\n";
1147cp.
code() +=
"etiss_coverage_count(5, 7202, 7201, 7199, 7197, 7198);\n";
1148cp.
code() +=
"etiss_coverage_count(1, 7203);\n";
1149if ((rd % 32ULL) != 0LL) {
1150cp.
code() +=
"etiss_coverage_count(5, 7209, 7206, 7204, 7207, 7208);\n";
1151cp.
code() +=
"*((RV64IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) +
"ULL] = (etiss_int32)(res1);\n";
1152cp.
code() +=
"etiss_coverage_count(6, 7218, 7214, 7213, 7211, 7217, 7215);\n";
1154cp.
code() +=
"etiss_uint32 res2 = (res1 < (etiss_uint32)(*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL])) ? (*((RV64IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) +
"ULL]) : (res1);\n";
1155cp.
code() +=
"etiss_coverage_count(12, 7236, 7235, 7228, 7220, 7227, 7225, 7224, 7222, 7233, 7232, 7230, 7234);\n";
1156cp.
code() +=
"etiss_uint32 mem_val_1;\n";
1157cp.
code() +=
"mem_val_1 = res2;\n";
1158cp.
code() +=
"etiss_coverage_count(6, 7244, 7242, 7240, 7238, 7239, 7243);\n";
1159cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";
1160cp.
code() +=
"if (cpu->exception) { // conditional\n";
1162cp.
code() +=
"{ // procedure\n";
1163cp.
code() +=
"RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1165cp.
code() +=
"} // procedure\n";
1167cp.
code() +=
"} // conditional\n";
1168cp.
code() +=
"} // block\n";
1171cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
1178 cp.
code() = std::string(
"//AMOMAXUW\n");
1181cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1193rd += R_rd_0.read(ba) << 0;
1196rs1 += R_rs1_0.read(ba) << 0;
1199rs2 += R_rs2_0.read(ba) << 0;
1202rl += R_rl_0.read(ba) << 0;
1205aq += R_aq_0.read(ba) << 0;
1209 std::stringstream ss;
1211ss <<
"amomaxuw" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | rs1=" + std::to_string(rs1) +
" | rs2=" + std::to_string(rs2) +
" | rl=" + std::to_string(rl) +
" | aq=" + std::to_string(aq) +
"]");
etiss::instr::InstructionGroup ISA32_RV64IMACFD("ISA32_RV64IMACFD", 32)
static InstructionDefinition amomaxw_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amomaxw",(uint64_t) 0xa000202f,(uint64_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOMAXW\n");cp.code()+="etiss_coverage_count(1, 178);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7129);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 7080, 7079, 7078, 7076);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int32 res1 = mem_val_0;\n";cp.code()+="etiss_coverage_count(5, 7088, 7087, 7085, 7083, 7084);\n";cp.code()+="etiss_coverage_count(1, 7089);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 7095, 7092, 7090, 7093, 7094);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res1;\n";cp.code()+="etiss_coverage_count(5, 7102, 7100, 7099, 7097, 7101);\n";} cp.code()+="etiss_uint32 res2 = (res1 < (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) ? (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) : (res1);\n";cp.code()+="etiss_coverage_count(12, 7120, 7119, 7112, 7104, 7111, 7109, 7108, 7106, 7117, 7116, 7114, 7118);\n";cp.code()+="etiss_uint32 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(6, 7128, 7126, 7124, 7122, 7123, 7127);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOMAXW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amomaxw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amoswapw_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoswapw",(uint64_t) 0x800202f,(uint64_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOSWAPW\n");cp.code()+="etiss_coverage_count(1, 172);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6829);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 6790, 6789, 6788, 6786);\n";cp.code()+="etiss_coverage_count(1, 6791);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 6797, 6794, 6792, 6795, 6796);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int64)(((etiss_int32)(mem_val_0)));\n";cp.code()+="etiss_coverage_count(11, 6814, 6802, 6801, 6799, 6813, 6810, 6808, 6806, 6804, 6805, 6811);\n";} cp.code()+="etiss_uint32 mem_val_1;\n";cp.code()+="mem_val_1 = (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(9, 6828, 6820, 6818, 6816, 6817, 6827, 6825, 6824, 6822);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOSWAPW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoswapw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amomaxuw_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amomaxuw",(uint64_t) 0xe000202f,(uint64_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOMAXUW\n");cp.code()+="etiss_coverage_count(1, 180);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7245);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 7194, 7193, 7192, 7190);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint32 res1 = mem_val_0;\n";cp.code()+="etiss_coverage_count(5, 7202, 7201, 7199, 7197, 7198);\n";cp.code()+="etiss_coverage_count(1, 7203);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 7209, 7206, 7204, 7207, 7208);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int32)(res1);\n";cp.code()+="etiss_coverage_count(6, 7218, 7214, 7213, 7211, 7217, 7215);\n";} cp.code()+="etiss_uint32 res2 = (res1 < (etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) ? (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) : (res1);\n";cp.code()+="etiss_coverage_count(12, 7236, 7235, 7228, 7220, 7227, 7225, 7224, 7222, 7233, 7232, 7230, 7234);\n";cp.code()+="etiss_uint32 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(6, 7244, 7242, 7240, 7238, 7239, 7243);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOMAXUW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amomaxuw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amoaddw_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoaddw",(uint64_t) 0x00202f,(uint64_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOADDW\n");cp.code()+="etiss_coverage_count(1, 173);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6876);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 6836, 6835, 6834, 6832);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int32 res1 = mem_val_0;\n";cp.code()+="etiss_coverage_count(5, 6844, 6843, 6841, 6839, 6840);\n";cp.code()+="etiss_coverage_count(1, 6845);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 6851, 6848, 6846, 6849, 6850);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res1;\n";cp.code()+="etiss_coverage_count(5, 6858, 6856, 6855, 6853, 6857);\n";} cp.code()+="etiss_uint32 res2 = res1 + *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(6, 6867, 6866, 6860, 6865, 6864, 6862);\n";cp.code()+="etiss_uint32 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(6, 6875, 6873, 6871, 6869, 6870, 6874);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOADDW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoaddw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amominw_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amominw",(uint64_t) 0x8000202f,(uint64_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOMINW\n");cp.code()+="etiss_coverage_count(1, 177);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7073);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 7024, 7023, 7022, 7020);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int32 res1 = mem_val_0;\n";cp.code()+="etiss_coverage_count(5, 7032, 7031, 7029, 7027, 7028);\n";cp.code()+="etiss_coverage_count(1, 7033);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 7039, 7036, 7034, 7037, 7038);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res1;\n";cp.code()+="etiss_coverage_count(5, 7046, 7044, 7043, 7041, 7045);\n";} cp.code()+="etiss_uint32 res2 = (res1 > (etiss_int32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) ? (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) : (res1);\n";cp.code()+="etiss_coverage_count(12, 7064, 7063, 7056, 7048, 7055, 7053, 7052, 7050, 7061, 7060, 7058, 7062);\n";cp.code()+="etiss_uint32 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(6, 7072, 7070, 7068, 7066, 7067, 7071);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOMINW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amominw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amoandw_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoandw",(uint64_t) 0x6000202f,(uint64_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOANDW\n");cp.code()+="etiss_coverage_count(1, 175);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6970);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 6930, 6929, 6928, 6926);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int32 res1 = mem_val_0;\n";cp.code()+="etiss_coverage_count(5, 6938, 6937, 6935, 6933, 6934);\n";cp.code()+="etiss_coverage_count(1, 6939);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 6945, 6942, 6940, 6943, 6944);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res1;\n";cp.code()+="etiss_coverage_count(5, 6952, 6950, 6949, 6947, 6951);\n";} cp.code()+="etiss_uint32 res2 = res1 & *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(6, 6961, 6960, 6954, 6959, 6958, 6956);\n";cp.code()+="etiss_uint32 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(6, 6969, 6967, 6965, 6963, 6964, 6968);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOANDW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoandw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amoxorw_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoxorw",(uint64_t) 0x2000202f,(uint64_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOXORW\n");cp.code()+="etiss_coverage_count(1, 174);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6923);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 6883, 6882, 6881, 6879);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int32 res1 = mem_val_0;\n";cp.code()+="etiss_coverage_count(5, 6891, 6890, 6888, 6886, 6887);\n";cp.code()+="etiss_coverage_count(1, 6892);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 6898, 6895, 6893, 6896, 6897);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res1;\n";cp.code()+="etiss_coverage_count(5, 6905, 6903, 6902, 6900, 6904);\n";} cp.code()+="etiss_uint32 res2 = res1 ^ *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(6, 6914, 6913, 6907, 6912, 6911, 6909);\n";cp.code()+="etiss_uint32 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(6, 6922, 6920, 6918, 6916, 6917, 6921);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOXORW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoxorw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amominuw_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amominuw",(uint64_t) 0xc000202f,(uint64_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOMINUW\n");cp.code()+="etiss_coverage_count(1, 179);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7187);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 7136, 7135, 7134, 7132);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint32 res1 = mem_val_0;\n";cp.code()+="etiss_coverage_count(5, 7144, 7143, 7141, 7139, 7140);\n";cp.code()+="etiss_coverage_count(1, 7145);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 7151, 7148, 7146, 7149, 7150);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int32)(res1);\n";cp.code()+="etiss_coverage_count(6, 7160, 7156, 7155, 7153, 7159, 7157);\n";} cp.code()+="etiss_uint32 res2 = (res1 > (etiss_uint32)(*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL])) ? (*((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) : (res1);\n";cp.code()+="etiss_coverage_count(12, 7178, 7177, 7170, 7162, 7169, 7167, 7166, 7164, 7175, 7174, 7172, 7176);\n";cp.code()+="etiss_uint32 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(6, 7186, 7184, 7182, 7180, 7181, 7185);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOMINUW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amominuw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
static InstructionDefinition amoorw_rd_rs1_rs2_rl_aq(ISA32_RV64IMACFD, "amoorw",(uint64_t) 0x4000202f,(uint64_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//AMOORW\n");cp.code()+="etiss_coverage_count(1, 176);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint64)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 7017);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 offs = *((RV64IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 6977, 6976, 6975, 6973);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int32 res1 = mem_val_0;\n";cp.code()+="etiss_coverage_count(5, 6985, 6984, 6982, 6980, 6981);\n";cp.code()+="etiss_coverage_count(1, 6986);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 6992, 6989, 6987, 6990, 6991);\n";cp.code()+="*((RV64IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res1;\n";cp.code()+="etiss_coverage_count(5, 6999, 6997, 6996, 6994, 6998);\n";} cp.code()+="etiss_uint32 res2 = res1 | *((RV64IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(6, 7008, 7007, 7001, 7006, 7005, 7003);\n";cp.code()+="etiss_uint32 mem_val_1;\n";cp.code()+="mem_val_1 = res2;\n";cp.code()+="etiss_coverage_count(6, 7016, 7014, 7012, 7010, 7011, 7015);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_1, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV64IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//AMOORW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "amoorw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
Contains a small code snipped.
@ APPENDEDRETURNINGREQUIRED
RegisterSet & getAffectedRegisters()
void append(const CodePart &part, CodePart::TYPE type)
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Reading through it will only return bits within the range.
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
this class contains parameters that persist in between instruction lookpus/translation within a trans...
uint64_t current_address_
start address of current instruction
holds information and translation callbacks for an instruction.