ETISS 0.11.2
ExtendableTranslatingInstructionSetSimulator(version0.11.2)
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RV32IMACFD_tum_rvaInstr.cpp
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1// clang-format off
9#include "RV32IMACFDArch.h"
10#include "RV32IMACFDFuncs.h"
11
12using namespace etiss;
13using namespace etiss::instr;
14
15// LRW -------------------------------------------------------------------------
16static InstructionDefinition lrw_rd_rs1_rl_aq (
17 ISA32_RV32IMACFD,
18 "lrw",
19 (uint32_t) 0x1000202f,
20 (uint32_t) 0xf9f0707f,
21 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22 {
23
24// -----------------------------------------------------------------------------
25
26// -----------------------------------------------------------------------------
27
28// -----------------------------------------------------------------------------
29// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
30etiss_uint8 rd = 0;
31static BitArrayRange R_rd_0(11, 7);
32rd += R_rd_0.read(ba) << 0;
33etiss_uint8 rs1 = 0;
34static BitArrayRange R_rs1_0(19, 15);
35rs1 += R_rs1_0.read(ba) << 0;
36etiss_uint8 rl = 0;
37static BitArrayRange R_rl_0(25, 25);
38rl += R_rl_0.read(ba) << 0;
39etiss_uint8 aq = 0;
40static BitArrayRange R_aq_0(26, 26);
41aq += R_aq_0.read(ba) << 0;
42
43// NOLINTEND(clang-diagnostic-unused-but-set-variable)
44// -----------------------------------------------------------------------------
45
46 {
47 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
48
49 cp.code() = std::string("//LRW\n");
50
51// -----------------------------------------------------------------------------
52cp.code() += "etiss_coverage_count(1, 181);\n";
53{ // block
54cp.code() += "etiss_coverage_count(1, 1169);\n";
55cp.code() += "{ // block\n";
56cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
57cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
58cp.code() += "} // block\n";
59} // block
60{ // block
61cp.code() += "etiss_coverage_count(1, 6444);\n";
62cp.code() += "{ // block\n";
63cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
64cp.code() += "etiss_coverage_count(4, 6422, 6421, 6420, 6418);\n";
65cp.code() += "etiss_uint32 mem_val_0;\n";
66cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
67cp.code() += "if (cpu->exception) { // conditional\n";
68{ // procedure
69cp.code() += "{ // procedure\n";
70cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
71cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
72cp.code() += "} // procedure\n";
73} // procedure
74cp.code() += "} // conditional\n";
75cp.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
76cp.code() += "etiss_coverage_count(4, 6429, 6428, 6426, 6425);\n";
77cp.code() += "((RV32IMACFD*)cpu)->RES_ADDR = offs;\n";
78cp.code() += "etiss_coverage_count(3, 6432, 6430, 6431);\n";
79cp.code() += "etiss_coverage_count(1, 6433);\n";
80if (rd) { // conditional
81cp.code() += "etiss_coverage_count(1, 6434);\n";
82cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(res);\n";
83cp.code() += "etiss_coverage_count(6, 6443, 6439, 6438, 6436, 6442, 6440);\n";
84} // conditional
85cp.code() += "} // block\n";
86} // block
87cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
88cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
89// -----------------------------------------------------------------------------
90 cp.getAffectedRegisters().add("instructionPointer", 32);
91 }
92 {
93 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
94
95 cp.code() = std::string("//LRW\n");
96
97// -----------------------------------------------------------------------------
98cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
99// -----------------------------------------------------------------------------
100 }
101
102 return true;
103 },
104 0,
105 [] (BitArray & ba, Instruction & instr)
106 {
107// -----------------------------------------------------------------------------
108etiss_uint8 rd = 0;
109static BitArrayRange R_rd_0(11, 7);
110rd += R_rd_0.read(ba) << 0;
111etiss_uint8 rs1 = 0;
112static BitArrayRange R_rs1_0(19, 15);
113rs1 += R_rs1_0.read(ba) << 0;
114etiss_uint8 rl = 0;
115static BitArrayRange R_rl_0(25, 25);
116rl += R_rl_0.read(ba) << 0;
117etiss_uint8 aq = 0;
118static BitArrayRange R_aq_0(26, 26);
119aq += R_aq_0.read(ba) << 0;
120
121// -----------------------------------------------------------------------------
122
123 std::stringstream ss;
124// -----------------------------------------------------------------------------
125ss << "lrw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
126// -----------------------------------------------------------------------------
127 return ss.str();
128 }
129);
130
131// SCW -------------------------------------------------------------------------
132static InstructionDefinition scw_rd_rs1_rs2_rl_aq (
133 ISA32_RV32IMACFD,
134 "scw",
135 (uint32_t) 0x1800202f,
136 (uint32_t) 0xf800707f,
137 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
138 {
139
140// -----------------------------------------------------------------------------
141
142// -----------------------------------------------------------------------------
143
144// -----------------------------------------------------------------------------
145// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
146etiss_uint8 rd = 0;
147static BitArrayRange R_rd_0(11, 7);
148rd += R_rd_0.read(ba) << 0;
149etiss_uint8 rs1 = 0;
150static BitArrayRange R_rs1_0(19, 15);
151rs1 += R_rs1_0.read(ba) << 0;
152etiss_uint8 rs2 = 0;
153static BitArrayRange R_rs2_0(24, 20);
154rs2 += R_rs2_0.read(ba) << 0;
155etiss_uint8 rl = 0;
156static BitArrayRange R_rl_0(25, 25);
157rl += R_rl_0.read(ba) << 0;
158etiss_uint8 aq = 0;
159static BitArrayRange R_aq_0(26, 26);
160aq += R_aq_0.read(ba) << 0;
161
162// NOLINTEND(clang-diagnostic-unused-but-set-variable)
163// -----------------------------------------------------------------------------
164
165 {
166 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
167
168 cp.code() = std::string("//SCW\n");
169
170// -----------------------------------------------------------------------------
171cp.code() += "etiss_coverage_count(1, 182);\n";
172{ // block
173cp.code() += "etiss_coverage_count(1, 1169);\n";
174cp.code() += "{ // block\n";
175cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
176cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
177cp.code() += "} // block\n";
178} // block
179{ // block
180cp.code() += "etiss_coverage_count(1, 6482);\n";
181cp.code() += "{ // block\n";
182cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
183cp.code() += "etiss_coverage_count(4, 6451, 6450, 6449, 6447);\n";
184cp.code() += "etiss_coverage_count(1, 6452);\n";
185cp.code() += "if (((RV32IMACFD*)cpu)->RES_ADDR == offs) { // conditional\n";
186cp.code() += "etiss_coverage_count(3, 6455, 6453, 6454);\n";
187cp.code() += "etiss_uint32 mem_val_0;\n";
188cp.code() += "mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
189cp.code() += "etiss_coverage_count(7, 6466, 6458, 6457, 6465, 6463, 6462, 6460);\n";
190cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
191cp.code() += "if (cpu->exception) { // conditional\n";
192{ // procedure
193cp.code() += "{ // procedure\n";
194cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
195cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
196cp.code() += "} // procedure\n";
197} // procedure
198cp.code() += "} // conditional\n";
199cp.code() += "} // conditional\n";
200cp.code() += "etiss_coverage_count(1, 6467);\n";
201if (rd) { // conditional
202cp.code() += "etiss_coverage_count(1, 6468);\n";
203cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((RV32IMACFD*)cpu)->RES_ADDR != offs;\n";
204cp.code() += "etiss_coverage_count(7, 6477, 6473, 6472, 6470, 6476, 6474, 6475);\n";
205} // conditional
206cp.code() += "((RV32IMACFD*)cpu)->RES_ADDR = -1LL;\n";
207cp.code() += "etiss_coverage_count(2, 6481, 6478);\n";
208cp.code() += "} // block\n";
209} // block
210cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
211cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
212// -----------------------------------------------------------------------------
213 cp.getAffectedRegisters().add("instructionPointer", 32);
214 }
215 {
216 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
217
218 cp.code() = std::string("//SCW\n");
219
220// -----------------------------------------------------------------------------
221cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
222// -----------------------------------------------------------------------------
223 }
224
225 return true;
226 },
227 0,
228 [] (BitArray & ba, Instruction & instr)
229 {
230// -----------------------------------------------------------------------------
231etiss_uint8 rd = 0;
232static BitArrayRange R_rd_0(11, 7);
233rd += R_rd_0.read(ba) << 0;
234etiss_uint8 rs1 = 0;
235static BitArrayRange R_rs1_0(19, 15);
236rs1 += R_rs1_0.read(ba) << 0;
237etiss_uint8 rs2 = 0;
238static BitArrayRange R_rs2_0(24, 20);
239rs2 += R_rs2_0.read(ba) << 0;
240etiss_uint8 rl = 0;
241static BitArrayRange R_rl_0(25, 25);
242rl += R_rl_0.read(ba) << 0;
243etiss_uint8 aq = 0;
244static BitArrayRange R_aq_0(26, 26);
245aq += R_aq_0.read(ba) << 0;
246
247// -----------------------------------------------------------------------------
248
249 std::stringstream ss;
250// -----------------------------------------------------------------------------
251ss << "scw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
252// -----------------------------------------------------------------------------
253 return ss.str();
254 }
255);
256// clang-format on
ISA32_RV32IMACFD
etiss::instr::InstructionGroup ISA32_RV32IMACFD("ISA32_RV32IMACFD", 32)
lrw_rd_rs1_rl_aq
static InstructionDefinition lrw_rd_rs1_rl_aq(ISA32_RV32IMACFD, "lrw",(uint32_t) 0x1000202f,(uint32_t) 0xf9f0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//LRW\n");cp.code()+="etiss_coverage_count(1, 181);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6444);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 offs = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 6422, 6421, 6420, 6418);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int32 res = (etiss_int32)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 6429, 6428, 6426, 6425);\n";cp.code()+="((RV32IMACFD*)cpu)->RES_ADDR = offs;\n";cp.code()+="etiss_coverage_count(3, 6432, 6430, 6431);\n";cp.code()+="etiss_coverage_count(1, 6433);\n";if(rd) { cp.code()+="etiss_coverage_count(1, 6434);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int32)(res);\n";cp.code()+="etiss_coverage_count(6, 6443, 6439, 6438, 6436, 6442, 6440);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//LRW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "lrw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
scw_rd_rs1_rs2_rl_aq
static InstructionDefinition scw_rd_rs1_rs2_rl_aq(ISA32_RV32IMACFD, "scw",(uint32_t) 0x1800202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SCW\n");cp.code()+="etiss_coverage_count(1, 182);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 6482);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 offs = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 6451, 6450, 6449, 6447);\n";cp.code()+="etiss_coverage_count(1, 6452);\n";cp.code()+="if (((RV32IMACFD*)cpu)->RES_ADDR == offs) { // conditional\n";cp.code()+="etiss_coverage_count(3, 6455, 6453, 6454);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(7, 6466, 6458, 6457, 6465, 6463, 6462, 6460);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // conditional\n";cp.code()+="etiss_coverage_count(1, 6467);\n";if(rd) { cp.code()+="etiss_coverage_count(1, 6468);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = ((RV32IMACFD*)cpu)->RES_ADDR != offs;\n";cp.code()+="etiss_coverage_count(7, 6477, 6473, 6472, 6470, 6476, 6474, 6475);\n";} cp.code()+="((RV32IMACFD*)cpu)->RES_ADDR = -1LL;\n";cp.code()+="etiss_coverage_count(2, 6481, 6478);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//SCW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "scw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
etiss_uint8
uint8_t etiss_uint8
Definition types.h:49
etiss::CodePart
Contains a small code snipped.
Definition CodePart.h:348
etiss::CodePart::APPENDEDRETURNINGREQUIRED
@ APPENDEDRETURNINGREQUIRED
Definition CodePart.h:364
etiss::CodePart::code
std::string & code()
Definition CodePart.h:378
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition CodePart.h:376
etiss::CodeSet
A set of CodeParts.
Definition CodePart.h:399
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition CodePart.h:412
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition CodePart.h:184
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition Instruction.h:162
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition Instruction.cpp:171
etiss::instr::BitArray
stores a bit vector
Definition Instruction.h:114
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition Instruction.h:290
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition Instruction.h:319
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition Instruction.h:346
etiss
forwards: include/jit/*
Definition Benchmark.h:17
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