ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV32IMACFD_tum_rvaInstr.cpp
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1 
8 #include "RV32IMACFDArch.h"
9 #include "RV32IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // LRW -------------------------------------------------------------------------
16 static InstructionDefinition lrw_rd_rs1_rl_aq (
17  ISA32_RV32IMACFD,
18  "lrw",
19  (uint32_t) 0x1000202f,
20  (uint32_t) 0xf9f0707f,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 etiss_uint8 rd = 0;
30 static BitArrayRange R_rd_0(11, 7);
31 rd += R_rd_0.read(ba) << 0;
32 etiss_uint8 rs1 = 0;
33 static BitArrayRange R_rs1_0(19, 15);
34 rs1 += R_rs1_0.read(ba) << 0;
35 etiss_uint8 rl = 0;
36 static BitArrayRange R_rl_0(25, 25);
37 rl += R_rl_0.read(ba) << 0;
38 etiss_uint8 aq = 0;
39 static BitArrayRange R_aq_0(26, 26);
40 aq += R_aq_0.read(ba) << 0;
41 
42 // -----------------------------------------------------------------------------
43 
44  {
45  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
46 
47  cp.code() = std::string("//LRW\n");
48 
49 // -----------------------------------------------------------------------------
50 { // block
51 cp.code() += "{ // block\n";
52 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
53 cp.code() += "} // block\n";
54 } // block
55 { // block
56 cp.code() += "{ // block\n";
57 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
58 cp.code() += "etiss_uint32 mem_val_0;\n";
59 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
60 cp.code() += "if (cpu->exception) { // conditional\n";
61 { // procedure
62 cp.code() += "{ // procedure\n";
63 cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
64 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
65 cp.code() += "} // procedure\n";
66 } // procedure
67 cp.code() += "} // conditional\n";
68 cp.code() += "etiss_int32 res = (etiss_int32)(mem_val_0);\n";
69 cp.code() += "((RV32IMACFD*)cpu)->RES_ADDR = offs;\n";
70 if (rd) { // conditional
71 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(res);\n";
72 } // conditional
73 cp.code() += "} // block\n";
74 } // block
75 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
76 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
77 // -----------------------------------------------------------------------------
78  cp.getAffectedRegisters().add("instructionPointer", 32);
79  }
80  {
81  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
82 
83  cp.code() = std::string("//LRW\n");
84 
85 // -----------------------------------------------------------------------------
86 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
87 // -----------------------------------------------------------------------------
88  }
89 
90  return true;
91  },
92  0,
93  [] (BitArray & ba, Instruction & instr)
94  {
95 // -----------------------------------------------------------------------------
96 etiss_uint8 rd = 0;
97 static BitArrayRange R_rd_0(11, 7);
98 rd += R_rd_0.read(ba) << 0;
99 etiss_uint8 rs1 = 0;
100 static BitArrayRange R_rs1_0(19, 15);
101 rs1 += R_rs1_0.read(ba) << 0;
102 etiss_uint8 rl = 0;
103 static BitArrayRange R_rl_0(25, 25);
104 rl += R_rl_0.read(ba) << 0;
105 etiss_uint8 aq = 0;
106 static BitArrayRange R_aq_0(26, 26);
107 aq += R_aq_0.read(ba) << 0;
108 
109 // -----------------------------------------------------------------------------
110 
111  std::stringstream ss;
112 // -----------------------------------------------------------------------------
113 ss << "lrw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
114 // -----------------------------------------------------------------------------
115  return ss.str();
116  }
117 );
118 
119 // SCW -------------------------------------------------------------------------
120 static InstructionDefinition scw_rd_rs1_rs2_rl_aq (
121  ISA32_RV32IMACFD,
122  "scw",
123  (uint32_t) 0x1800202f,
124  (uint32_t) 0xf800707f,
125  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
126  {
127 
128 // -----------------------------------------------------------------------------
129 
130 // -----------------------------------------------------------------------------
131 
132 // -----------------------------------------------------------------------------
133 etiss_uint8 rd = 0;
134 static BitArrayRange R_rd_0(11, 7);
135 rd += R_rd_0.read(ba) << 0;
136 etiss_uint8 rs1 = 0;
137 static BitArrayRange R_rs1_0(19, 15);
138 rs1 += R_rs1_0.read(ba) << 0;
139 etiss_uint8 rs2 = 0;
140 static BitArrayRange R_rs2_0(24, 20);
141 rs2 += R_rs2_0.read(ba) << 0;
142 etiss_uint8 rl = 0;
143 static BitArrayRange R_rl_0(25, 25);
144 rl += R_rl_0.read(ba) << 0;
145 etiss_uint8 aq = 0;
146 static BitArrayRange R_aq_0(26, 26);
147 aq += R_aq_0.read(ba) << 0;
148 
149 // -----------------------------------------------------------------------------
150 
151  {
152  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
153 
154  cp.code() = std::string("//SCW\n");
155 
156 // -----------------------------------------------------------------------------
157 { // block
158 cp.code() += "{ // block\n";
159 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
160 cp.code() += "} // block\n";
161 } // block
162 { // block
163 cp.code() += "{ // block\n";
164 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
165 cp.code() += "if (((RV32IMACFD*)cpu)->RES_ADDR == offs) { // conditional\n";
166 cp.code() += "etiss_uint32 mem_val_0;\n";
167 cp.code() += "mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
168 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
169 cp.code() += "if (cpu->exception) { // conditional\n";
170 { // procedure
171 cp.code() += "{ // procedure\n";
172 cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
173 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
174 cp.code() += "} // procedure\n";
175 } // procedure
176 cp.code() += "} // conditional\n";
177 cp.code() += "} // conditional\n";
178 if (rd) { // conditional
179 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = ((RV32IMACFD*)cpu)->RES_ADDR != offs;\n";
180 } // conditional
181 cp.code() += "((RV32IMACFD*)cpu)->RES_ADDR = -1LL;\n";
182 cp.code() += "} // block\n";
183 } // block
184 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
185 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
186 // -----------------------------------------------------------------------------
187  cp.getAffectedRegisters().add("instructionPointer", 32);
188  }
189  {
190  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
191 
192  cp.code() = std::string("//SCW\n");
193 
194 // -----------------------------------------------------------------------------
195 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
196 // -----------------------------------------------------------------------------
197  }
198 
199  return true;
200  },
201  0,
202  [] (BitArray & ba, Instruction & instr)
203  {
204 // -----------------------------------------------------------------------------
205 etiss_uint8 rd = 0;
206 static BitArrayRange R_rd_0(11, 7);
207 rd += R_rd_0.read(ba) << 0;
208 etiss_uint8 rs1 = 0;
209 static BitArrayRange R_rs1_0(19, 15);
210 rs1 += R_rs1_0.read(ba) << 0;
211 etiss_uint8 rs2 = 0;
212 static BitArrayRange R_rs2_0(24, 20);
213 rs2 += R_rs2_0.read(ba) << 0;
214 etiss_uint8 rl = 0;
215 static BitArrayRange R_rl_0(25, 25);
216 rl += R_rl_0.read(ba) << 0;
217 etiss_uint8 aq = 0;
218 static BitArrayRange R_aq_0(26, 26);
219 aq += R_aq_0.read(ba) << 0;
220 
221 // -----------------------------------------------------------------------------
222 
223  std::stringstream ss;
224 // -----------------------------------------------------------------------------
225 ss << "scw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rl=" + std::to_string(rl) + " | aq=" + std::to_string(aq) + "]");
226 // -----------------------------------------------------------------------------
227  return ss.str();
228  }
229 );
ISA32_RV32IMACFD
etiss::instr::InstructionGroup ISA32_RV32IMACFD("ISA32_RV32IMACFD", 32)
scw_rd_rs1_rs2_rl_aq
static InstructionDefinition scw_rd_rs1_rs2_rl_aq(ISA32_RV32IMACFD, "scw",(uint32_t) 0x1800202f,(uint32_t) 0xf800707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//SCW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint32 offs = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="if (((RV32IMACFD*)cpu)->RES_ADDR == offs) { // conditional\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // conditional\n";if(rd) { cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = ((RV32IMACFD*)cpu)->RES_ADDR != offs;\n";} cp.code()+="((RV32IMACFD*)cpu)->RES_ADDR = -1LL;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//SCW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "scw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
lrw_rd_rs1_rl_aq
static InstructionDefinition lrw_rd_rs1_rl_aq(ISA32_RV32IMACFD, "lrw",(uint32_t) 0x1000202f,(uint32_t) 0xf9f0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//LRW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint32 offs = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int32 res = (etiss_int32)(mem_val_0);\n";cp.code()+="((RV32IMACFD*)cpu)->RES_ADDR = offs;\n";if(rd) { cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int32)(res);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//LRW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rl=0;static BitArrayRange R_rl_0(25, 25);rl+=R_rl_0.read(ba)<< 0;etiss_uint8 aq=0;static BitArrayRange R_aq_0(26, 26);aq+=R_aq_0.read(ba)<< 0;std::stringstream ss;ss<< "lrw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rl="+std::to_string(rl)+" | aq="+std::to_string(aq)+"]");return ss.str();})
uint32_t
static __inline__ uint32_t
Definition: arm_cde.h:25
etiss_uint8
uint8_t etiss_uint8
Definition: types.h:87
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:386
etiss::CodePart::APPENDEDRETURNINGREQUIRED
@ APPENDEDRETURNINGREQUIRED
Definition: CodePart.h:402
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition: Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition: Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
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