ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV32IMACFD_ZifenceiInstr.cpp
Go to the documentation of this file.
1 
8 #include "RV32IMACFDArch.h"
9 #include "RV32IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // FENCE_I ---------------------------------------------------------------------
18  "fence_i",
19  (uint32_t) 0x00100f,
20  (uint32_t) 0x00707f,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 etiss_uint8 rd = 0;
30 static BitArrayRange R_rd_0(11, 7);
31 rd += R_rd_0.read(ba) << 0;
32 etiss_uint8 rs1 = 0;
33 static BitArrayRange R_rs1_0(19, 15);
34 rs1 += R_rs1_0.read(ba) << 0;
35 etiss_uint16 imm = 0;
36 static BitArrayRange R_imm_0(31, 20);
37 imm += R_imm_0.read(ba) << 0;
38 
39 // -----------------------------------------------------------------------------
40 
41  {
43 
44  cp.code() = std::string("//FENCE_I\n");
45 
46 // -----------------------------------------------------------------------------
47 cp.code() += "cpu->exception = ETISS_RETURNCODE_RELOADBLOCKS;\n";
48 { // block
49 cp.code() += "{ // block\n";
50 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
51 cp.code() += "} // block\n";
52 } // block
53 cp.code() += "((RV32IMACFD*)cpu)->FENCE[1ULL] = " + std::to_string(imm) + "ULL;\n";
54 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
55 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
56 // -----------------------------------------------------------------------------
57  cp.getAffectedRegisters().add("instructionPointer", 32);
58  }
59  {
61 
62  cp.code() = std::string("//FENCE_I\n");
63 
64 // -----------------------------------------------------------------------------
65 cp.code() += "return cpu->exception;\n";
66 // -----------------------------------------------------------------------------
67  }
68 
69  return true;
70  },
71  0,
72  [] (BitArray & ba, Instruction & instr)
73  {
74 // -----------------------------------------------------------------------------
75 etiss_uint8 rd = 0;
76 static BitArrayRange R_rd_0(11, 7);
77 rd += R_rd_0.read(ba) << 0;
78 etiss_uint8 rs1 = 0;
79 static BitArrayRange R_rs1_0(19, 15);
80 rs1 += R_rs1_0.read(ba) << 0;
81 etiss_uint16 imm = 0;
82 static BitArrayRange R_imm_0(31, 20);
83 imm += R_imm_0.read(ba) << 0;
84 
85 // -----------------------------------------------------------------------------
86 
87  std::stringstream ss;
88 // -----------------------------------------------------------------------------
89 ss << "fence_i" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
90 // -----------------------------------------------------------------------------
91  return ss.str();
92  }
93 );
etiss::instr::InstructionGroup ISA32_RV32IMACFD("ISA32_RV32IMACFD", 32)
static InstructionDefinition fence_i_rd_rs1_imm(ISA32_RV32IMACFD, "fence_i",(uint32_t) 0x00100f,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FENCE_I\n");cp.code()+="cpu->exception = ETISS_RETURNCODE_RELOADBLOCKS;\n";{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} cp.code()+="((RV32IMACFD*)cpu)->FENCE[1ULL] = "+std::to_string(imm)+"ULL;\n";cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//FENCE_I\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "fence_i"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
static __inline__ uint32_t
Definition: arm_cde.h:25
uint8_t etiss_uint8
Definition: types.h:87
uint16_t etiss_uint16
Definition: types.h:90
Contains a small code snipped.
Definition: CodePart.h:386
@ APPENDEDRETURNINGREQUIRED
Definition: CodePart.h:402
std::string & code()
Definition: CodePart.h:416
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
A set of CodeParts.
Definition: CodePart.h:437
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
Reading through it will only return bits within the range.
Definition: Instruction.h:208
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
stores a bit vector
Definition: Instruction.h:161
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53