ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
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RV32IMACFD_RV32MInstr.cpp
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1
8#include "RV32IMACFDArch.h"
9#include "RV32IMACFDFuncs.h"
10
11using namespace etiss;
12using namespace etiss::instr;
13
14
15// MUL -------------------------------------------------------------------------
16static InstructionDefinition mul_rd_rs1_rs2 (
17 ISA32_RV32IMACFD,
18 "mul",
19 (uint32_t) 0x2000033,
20 (uint32_t) 0xfe00707f,
21 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22 {
23
24// -----------------------------------------------------------------------------
25
26// -----------------------------------------------------------------------------
27
28// -----------------------------------------------------------------------------
29etiss_uint8 rd = 0;
30static BitArrayRange R_rd_0(11, 7);
31rd += R_rd_0.read(ba) << 0;
32etiss_uint8 rs1 = 0;
33static BitArrayRange R_rs1_0(19, 15);
34rs1 += R_rs1_0.read(ba) << 0;
35etiss_uint8 rs2 = 0;
36static BitArrayRange R_rs2_0(24, 20);
37rs2 += R_rs2_0.read(ba) << 0;
38
39// -----------------------------------------------------------------------------
40
41 {
42 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
43
44 cp.code() = std::string("//MUL\n");
45
46// -----------------------------------------------------------------------------
47cp.code() += "etiss_coverage_count(1, 72);\n";
48{ // block
49cp.code() += "etiss_coverage_count(1, 1169);\n";
50cp.code() += "{ // block\n";
51cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
52cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
53cp.code() += "} // block\n";
54} // block
55{ // block
56cp.code() += "etiss_coverage_count(1, 2846);\n";
57cp.code() += "{ // block\n";
58cp.code() += "etiss_coverage_count(1, 2810);\n";
59if ((rd % 32ULL) != 0LL) { // conditional
60cp.code() += "etiss_coverage_count(5, 2816, 2813, 2811, 2814, 2815);\n";
61{ // block
62cp.code() += "etiss_coverage_count(1, 2845);\n";
63cp.code() += "{ // block\n";
64cp.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) * (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]));\n";
65cp.code() += "etiss_coverage_count(12, 2835, 2834, 2825, 2823, 2822, 2821, 2819, 2833, 2831, 2830, 2829, 2827);\n";
66cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)(res);\n";
67cp.code() += "etiss_coverage_count(6, 2844, 2840, 2839, 2837, 2843, 2841);\n";
68cp.code() += "} // block\n";
69} // block
70} // conditional
71cp.code() += "} // block\n";
72} // block
73cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
74cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
75// -----------------------------------------------------------------------------
76 cp.getAffectedRegisters().add("instructionPointer", 32);
77 }
78
79 return true;
80 },
81 0,
82 [] (BitArray & ba, Instruction & instr)
83 {
84// -----------------------------------------------------------------------------
85etiss_uint8 rd = 0;
86static BitArrayRange R_rd_0(11, 7);
87rd += R_rd_0.read(ba) << 0;
88etiss_uint8 rs1 = 0;
89static BitArrayRange R_rs1_0(19, 15);
90rs1 += R_rs1_0.read(ba) << 0;
91etiss_uint8 rs2 = 0;
92static BitArrayRange R_rs2_0(24, 20);
93rs2 += R_rs2_0.read(ba) << 0;
94
95// -----------------------------------------------------------------------------
96
97 std::stringstream ss;
98// -----------------------------------------------------------------------------
99ss << "mul" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
100// -----------------------------------------------------------------------------
101 return ss.str();
102 }
103);
104
105// MULH ------------------------------------------------------------------------
106static InstructionDefinition mulh_rd_rs1_rs2 (
107 ISA32_RV32IMACFD,
108 "mulh",
109 (uint32_t) 0x2001033,
110 (uint32_t) 0xfe00707f,
111 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
112 {
113
114// -----------------------------------------------------------------------------
115
116// -----------------------------------------------------------------------------
117
118// -----------------------------------------------------------------------------
119etiss_uint8 rd = 0;
120static BitArrayRange R_rd_0(11, 7);
121rd += R_rd_0.read(ba) << 0;
122etiss_uint8 rs1 = 0;
123static BitArrayRange R_rs1_0(19, 15);
124rs1 += R_rs1_0.read(ba) << 0;
125etiss_uint8 rs2 = 0;
126static BitArrayRange R_rs2_0(24, 20);
127rs2 += R_rs2_0.read(ba) << 0;
128
129// -----------------------------------------------------------------------------
130
131 {
132 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
133
134 cp.code() = std::string("//MULH\n");
135
136// -----------------------------------------------------------------------------
137cp.code() += "etiss_coverage_count(1, 73);\n";
138{ // block
139cp.code() += "etiss_coverage_count(1, 1169);\n";
140cp.code() += "{ // block\n";
141cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
142cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
143cp.code() += "} // block\n";
144} // block
145{ // block
146cp.code() += "etiss_coverage_count(1, 2886);\n";
147cp.code() += "{ // block\n";
148cp.code() += "etiss_coverage_count(1, 2847);\n";
149if ((rd % 32ULL) != 0LL) { // conditional
150cp.code() += "etiss_coverage_count(5, 2853, 2850, 2848, 2851, 2852);\n";
151{ // block
152cp.code() += "etiss_coverage_count(1, 2885);\n";
153cp.code() += "{ // block\n";
154cp.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) * (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]));\n";
155cp.code() += "etiss_coverage_count(12, 2872, 2871, 2862, 2860, 2859, 2858, 2856, 2870, 2868, 2867, 2866, 2864);\n";
156cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)((res >> 32ULL));\n";
157cp.code() += "etiss_coverage_count(8, 2884, 2877, 2876, 2874, 2883, 2880, 2878, 2881);\n";
158cp.code() += "} // block\n";
159} // block
160} // conditional
161cp.code() += "} // block\n";
162} // block
163cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
164cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
165// -----------------------------------------------------------------------------
166 cp.getAffectedRegisters().add("instructionPointer", 32);
167 }
168
169 return true;
170 },
171 0,
172 [] (BitArray & ba, Instruction & instr)
173 {
174// -----------------------------------------------------------------------------
175etiss_uint8 rd = 0;
176static BitArrayRange R_rd_0(11, 7);
177rd += R_rd_0.read(ba) << 0;
178etiss_uint8 rs1 = 0;
179static BitArrayRange R_rs1_0(19, 15);
180rs1 += R_rs1_0.read(ba) << 0;
181etiss_uint8 rs2 = 0;
182static BitArrayRange R_rs2_0(24, 20);
183rs2 += R_rs2_0.read(ba) << 0;
184
185// -----------------------------------------------------------------------------
186
187 std::stringstream ss;
188// -----------------------------------------------------------------------------
189ss << "mulh" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
190// -----------------------------------------------------------------------------
191 return ss.str();
192 }
193);
194
195// MULHSU ----------------------------------------------------------------------
196static InstructionDefinition mulhsu_rd_rs1_rs2 (
197 ISA32_RV32IMACFD,
198 "mulhsu",
199 (uint32_t) 0x2002033,
200 (uint32_t) 0xfe00707f,
201 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
202 {
203
204// -----------------------------------------------------------------------------
205
206// -----------------------------------------------------------------------------
207
208// -----------------------------------------------------------------------------
209etiss_uint8 rd = 0;
210static BitArrayRange R_rd_0(11, 7);
211rd += R_rd_0.read(ba) << 0;
212etiss_uint8 rs1 = 0;
213static BitArrayRange R_rs1_0(19, 15);
214rs1 += R_rs1_0.read(ba) << 0;
215etiss_uint8 rs2 = 0;
216static BitArrayRange R_rs2_0(24, 20);
217rs2 += R_rs2_0.read(ba) << 0;
218
219// -----------------------------------------------------------------------------
220
221 {
222 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
223
224 cp.code() = std::string("//MULHSU\n");
225
226// -----------------------------------------------------------------------------
227cp.code() += "etiss_coverage_count(1, 74);\n";
228{ // block
229cp.code() += "etiss_coverage_count(1, 1169);\n";
230cp.code() += "{ // block\n";
231cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
232cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
233cp.code() += "} // block\n";
234} // block
235{ // block
236cp.code() += "etiss_coverage_count(1, 2925);\n";
237cp.code() += "{ // block\n";
238cp.code() += "etiss_coverage_count(1, 2887);\n";
239if ((rd % 32ULL) != 0LL) { // conditional
240cp.code() += "etiss_coverage_count(5, 2893, 2890, 2888, 2891, 2892);\n";
241{ // block
242cp.code() += "etiss_coverage_count(1, 2924);\n";
243cp.code() += "{ // block\n";
244cp.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) * (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
245cp.code() += "etiss_coverage_count(11, 2911, 2910, 2902, 2900, 2899, 2898, 2896, 2909, 2907, 2906, 2904);\n";
246cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)((res >> 32ULL));\n";
247cp.code() += "etiss_coverage_count(8, 2923, 2916, 2915, 2913, 2922, 2919, 2917, 2920);\n";
248cp.code() += "} // block\n";
249} // block
250} // conditional
251cp.code() += "} // block\n";
252} // block
253cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
254cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
255// -----------------------------------------------------------------------------
256 cp.getAffectedRegisters().add("instructionPointer", 32);
257 }
258
259 return true;
260 },
261 0,
262 [] (BitArray & ba, Instruction & instr)
263 {
264// -----------------------------------------------------------------------------
265etiss_uint8 rd = 0;
266static BitArrayRange R_rd_0(11, 7);
267rd += R_rd_0.read(ba) << 0;
268etiss_uint8 rs1 = 0;
269static BitArrayRange R_rs1_0(19, 15);
270rs1 += R_rs1_0.read(ba) << 0;
271etiss_uint8 rs2 = 0;
272static BitArrayRange R_rs2_0(24, 20);
273rs2 += R_rs2_0.read(ba) << 0;
274
275// -----------------------------------------------------------------------------
276
277 std::stringstream ss;
278// -----------------------------------------------------------------------------
279ss << "mulhsu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
280// -----------------------------------------------------------------------------
281 return ss.str();
282 }
283);
284
285// MULHU -----------------------------------------------------------------------
286static InstructionDefinition mulhu_rd_rs1_rs2 (
287 ISA32_RV32IMACFD,
288 "mulhu",
289 (uint32_t) 0x2003033,
290 (uint32_t) 0xfe00707f,
291 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
292 {
293
294// -----------------------------------------------------------------------------
295
296// -----------------------------------------------------------------------------
297
298// -----------------------------------------------------------------------------
299etiss_uint8 rd = 0;
300static BitArrayRange R_rd_0(11, 7);
301rd += R_rd_0.read(ba) << 0;
302etiss_uint8 rs1 = 0;
303static BitArrayRange R_rs1_0(19, 15);
304rs1 += R_rs1_0.read(ba) << 0;
305etiss_uint8 rs2 = 0;
306static BitArrayRange R_rs2_0(24, 20);
307rs2 += R_rs2_0.read(ba) << 0;
308
309// -----------------------------------------------------------------------------
310
311 {
312 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
313
314 cp.code() = std::string("//MULHU\n");
315
316// -----------------------------------------------------------------------------
317cp.code() += "etiss_coverage_count(1, 75);\n";
318{ // block
319cp.code() += "etiss_coverage_count(1, 1169);\n";
320cp.code() += "{ // block\n";
321cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
322cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
323cp.code() += "} // block\n";
324} // block
325{ // block
326cp.code() += "etiss_coverage_count(1, 2963);\n";
327cp.code() += "{ // block\n";
328cp.code() += "etiss_coverage_count(1, 2926);\n";
329if ((rd % 32ULL) != 0LL) { // conditional
330cp.code() += "etiss_coverage_count(5, 2932, 2929, 2927, 2930, 2931);\n";
331{ // block
332cp.code() += "etiss_coverage_count(1, 2962);\n";
333cp.code() += "{ // block\n";
334cp.code() += "etiss_uint64 res = (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) * (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
335cp.code() += "etiss_coverage_count(10, 2949, 2948, 2940, 2938, 2937, 2935, 2947, 2945, 2944, 2942);\n";
336cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)((res >> 32ULL));\n";
337cp.code() += "etiss_coverage_count(8, 2961, 2954, 2953, 2951, 2960, 2957, 2955, 2958);\n";
338cp.code() += "} // block\n";
339} // block
340} // conditional
341cp.code() += "} // block\n";
342} // block
343cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
344cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
345// -----------------------------------------------------------------------------
346 cp.getAffectedRegisters().add("instructionPointer", 32);
347 }
348
349 return true;
350 },
351 0,
352 [] (BitArray & ba, Instruction & instr)
353 {
354// -----------------------------------------------------------------------------
355etiss_uint8 rd = 0;
356static BitArrayRange R_rd_0(11, 7);
357rd += R_rd_0.read(ba) << 0;
358etiss_uint8 rs1 = 0;
359static BitArrayRange R_rs1_0(19, 15);
360rs1 += R_rs1_0.read(ba) << 0;
361etiss_uint8 rs2 = 0;
362static BitArrayRange R_rs2_0(24, 20);
363rs2 += R_rs2_0.read(ba) << 0;
364
365// -----------------------------------------------------------------------------
366
367 std::stringstream ss;
368// -----------------------------------------------------------------------------
369ss << "mulhu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
370// -----------------------------------------------------------------------------
371 return ss.str();
372 }
373);
374
375// DIV -------------------------------------------------------------------------
376static InstructionDefinition div_rd_rs1_rs2 (
377 ISA32_RV32IMACFD,
378 "div",
379 (uint32_t) 0x2004033,
380 (uint32_t) 0xfe00707f,
381 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
382 {
383
384// -----------------------------------------------------------------------------
385
386// -----------------------------------------------------------------------------
387
388// -----------------------------------------------------------------------------
389etiss_uint8 rd = 0;
390static BitArrayRange R_rd_0(11, 7);
391rd += R_rd_0.read(ba) << 0;
392etiss_uint8 rs1 = 0;
393static BitArrayRange R_rs1_0(19, 15);
394rs1 += R_rs1_0.read(ba) << 0;
395etiss_uint8 rs2 = 0;
396static BitArrayRange R_rs2_0(24, 20);
397rs2 += R_rs2_0.read(ba) << 0;
398
399// -----------------------------------------------------------------------------
400
401 {
402 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
403
404 cp.code() = std::string("//DIV\n");
405
406// -----------------------------------------------------------------------------
407cp.code() += "etiss_coverage_count(1, 76);\n";
408{ // block
409cp.code() += "etiss_coverage_count(1, 1169);\n";
410cp.code() += "{ // block\n";
411cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
412cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
413cp.code() += "} // block\n";
414} // block
415{ // block
416cp.code() += "etiss_coverage_count(1, 3044);\n";
417cp.code() += "{ // block\n";
418cp.code() += "etiss_coverage_count(1, 2964);\n";
419if ((rd % 32ULL) != 0LL) { // conditional
420cp.code() += "etiss_coverage_count(5, 2970, 2967, 2965, 2968, 2969);\n";
421{ // block
422cp.code() += "etiss_coverage_count(1, 3043);\n";
423cp.code() += "{ // block\n";
424cp.code() += "etiss_coverage_count(1, 2971);\n";
425cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0LL) { // conditional\n";
426cp.code() += "etiss_coverage_count(5, 2978, 2976, 2975, 2973, 2977);\n";
427{ // block
428cp.code() += "etiss_coverage_count(1, 3034);\n";
429cp.code() += "{ // block\n";
430etiss_uint32 MMIN = 2147483648ULL;
431cp.code() += "etiss_coverage_count(1, 2986);\n";
432cp.code() += "etiss_coverage_count(1, 2987);\n";
433cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] == " + std::to_string(MMIN) + "ULL && (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) == -1LL) { // conditional\n";
434cp.code() += "etiss_coverage_count(11, 3005, 2994, 2992, 2991, 2989, 2993, 3004, 3001, 2999, 2998, 2996);\n";
435cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(MMIN) + "ULL;\n";
436cp.code() += "etiss_coverage_count(5, 3012, 3010, 3009, 3007, 3011);\n";
437cp.code() += "} // conditional\n";
438cp.code() += "else { // conditional\n";
439cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) / (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
440cp.code() += "etiss_coverage_count(13, 3033, 3017, 3016, 3014, 3032, 3024, 3022, 3021, 3019, 3031, 3029, 3028, 3026);\n";
441cp.code() += "} // conditional\n";
442cp.code() += "} // block\n";
443} // block
444cp.code() += "} // conditional\n";
445cp.code() += "else { // conditional\n";
446cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -1LL;\n";
447cp.code() += "etiss_coverage_count(4, 3042, 3039, 3038, 3036);\n";
448cp.code() += "} // conditional\n";
449cp.code() += "} // block\n";
450} // block
451} // conditional
452cp.code() += "} // block\n";
453} // block
454cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
455cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
456// -----------------------------------------------------------------------------
457 cp.getAffectedRegisters().add("instructionPointer", 32);
458 }
459
460 return true;
461 },
462 0,
463 [] (BitArray & ba, Instruction & instr)
464 {
465// -----------------------------------------------------------------------------
466etiss_uint8 rd = 0;
467static BitArrayRange R_rd_0(11, 7);
468rd += R_rd_0.read(ba) << 0;
469etiss_uint8 rs1 = 0;
470static BitArrayRange R_rs1_0(19, 15);
471rs1 += R_rs1_0.read(ba) << 0;
472etiss_uint8 rs2 = 0;
473static BitArrayRange R_rs2_0(24, 20);
474rs2 += R_rs2_0.read(ba) << 0;
475
476// -----------------------------------------------------------------------------
477
478 std::stringstream ss;
479// -----------------------------------------------------------------------------
480ss << "div" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
481// -----------------------------------------------------------------------------
482 return ss.str();
483 }
484);
485
486// DIVU ------------------------------------------------------------------------
487static InstructionDefinition divu_rd_rs1_rs2 (
488 ISA32_RV32IMACFD,
489 "divu",
490 (uint32_t) 0x2005033,
491 (uint32_t) 0xfe00707f,
492 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
493 {
494
495// -----------------------------------------------------------------------------
496
497// -----------------------------------------------------------------------------
498
499// -----------------------------------------------------------------------------
500etiss_uint8 rd = 0;
501static BitArrayRange R_rd_0(11, 7);
502rd += R_rd_0.read(ba) << 0;
503etiss_uint8 rs1 = 0;
504static BitArrayRange R_rs1_0(19, 15);
505rs1 += R_rs1_0.read(ba) << 0;
506etiss_uint8 rs2 = 0;
507static BitArrayRange R_rs2_0(24, 20);
508rs2 += R_rs2_0.read(ba) << 0;
509
510// -----------------------------------------------------------------------------
511
512 {
513 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
514
515 cp.code() = std::string("//DIVU\n");
516
517// -----------------------------------------------------------------------------
518cp.code() += "etiss_coverage_count(1, 77);\n";
519{ // block
520cp.code() += "etiss_coverage_count(1, 1169);\n";
521cp.code() += "{ // block\n";
522cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
523cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
524cp.code() += "} // block\n";
525} // block
526{ // block
527cp.code() += "etiss_coverage_count(1, 3086);\n";
528cp.code() += "{ // block\n";
529cp.code() += "etiss_coverage_count(1, 3045);\n";
530if ((rd % 32ULL) != 0LL) { // conditional
531cp.code() += "etiss_coverage_count(5, 3051, 3048, 3046, 3049, 3050);\n";
532{ // block
533cp.code() += "etiss_coverage_count(1, 3085);\n";
534cp.code() += "{ // block\n";
535cp.code() += "etiss_coverage_count(1, 3052);\n";
536cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0LL) { // conditional\n";
537cp.code() += "etiss_coverage_count(5, 3059, 3057, 3056, 3054, 3058);\n";
538cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] / *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
539cp.code() += "etiss_coverage_count(11, 3076, 3064, 3063, 3061, 3075, 3069, 3068, 3066, 3074, 3073, 3071);\n";
540cp.code() += "} // conditional\n";
541cp.code() += "else { // conditional\n";
542cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -1LL;\n";
543cp.code() += "etiss_coverage_count(4, 3084, 3081, 3080, 3078);\n";
544cp.code() += "} // conditional\n";
545cp.code() += "} // block\n";
546} // block
547} // conditional
548cp.code() += "} // block\n";
549} // block
550cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
551cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
552// -----------------------------------------------------------------------------
553 cp.getAffectedRegisters().add("instructionPointer", 32);
554 }
555
556 return true;
557 },
558 0,
559 [] (BitArray & ba, Instruction & instr)
560 {
561// -----------------------------------------------------------------------------
562etiss_uint8 rd = 0;
563static BitArrayRange R_rd_0(11, 7);
564rd += R_rd_0.read(ba) << 0;
565etiss_uint8 rs1 = 0;
566static BitArrayRange R_rs1_0(19, 15);
567rs1 += R_rs1_0.read(ba) << 0;
568etiss_uint8 rs2 = 0;
569static BitArrayRange R_rs2_0(24, 20);
570rs2 += R_rs2_0.read(ba) << 0;
571
572// -----------------------------------------------------------------------------
573
574 std::stringstream ss;
575// -----------------------------------------------------------------------------
576ss << "divu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
577// -----------------------------------------------------------------------------
578 return ss.str();
579 }
580);
581
582// REM -------------------------------------------------------------------------
583static InstructionDefinition rem_rd_rs1_rs2 (
584 ISA32_RV32IMACFD,
585 "rem",
586 (uint32_t) 0x2006033,
587 (uint32_t) 0xfe00707f,
588 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
589 {
590
591// -----------------------------------------------------------------------------
592
593// -----------------------------------------------------------------------------
594
595// -----------------------------------------------------------------------------
596etiss_uint8 rd = 0;
597static BitArrayRange R_rd_0(11, 7);
598rd += R_rd_0.read(ba) << 0;
599etiss_uint8 rs1 = 0;
600static BitArrayRange R_rs1_0(19, 15);
601rs1 += R_rs1_0.read(ba) << 0;
602etiss_uint8 rs2 = 0;
603static BitArrayRange R_rs2_0(24, 20);
604rs2 += R_rs2_0.read(ba) << 0;
605
606// -----------------------------------------------------------------------------
607
608 {
609 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
610
611 cp.code() = std::string("//REM\n");
612
613// -----------------------------------------------------------------------------
614cp.code() += "etiss_coverage_count(1, 78);\n";
615{ // block
616cp.code() += "etiss_coverage_count(1, 1169);\n";
617cp.code() += "{ // block\n";
618cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
619cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
620cp.code() += "} // block\n";
621} // block
622{ // block
623cp.code() += "etiss_coverage_count(1, 3170);\n";
624cp.code() += "{ // block\n";
625cp.code() += "etiss_coverage_count(1, 3087);\n";
626if ((rd % 32ULL) != 0LL) { // conditional
627cp.code() += "etiss_coverage_count(5, 3093, 3090, 3088, 3091, 3092);\n";
628{ // block
629cp.code() += "etiss_coverage_count(1, 3169);\n";
630cp.code() += "{ // block\n";
631cp.code() += "etiss_coverage_count(1, 3094);\n";
632cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0LL) { // conditional\n";
633cp.code() += "etiss_coverage_count(5, 3101, 3099, 3098, 3096, 3100);\n";
634{ // block
635cp.code() += "etiss_coverage_count(1, 3157);\n";
636cp.code() += "{ // block\n";
637etiss_uint32 MMIN = 2147483648ULL;
638cp.code() += "etiss_coverage_count(1, 3109);\n";
639cp.code() += "etiss_coverage_count(1, 3110);\n";
640cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] == " + std::to_string(MMIN) + "ULL && (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) == -1LL) { // conditional\n";
641cp.code() += "etiss_coverage_count(11, 3128, 3117, 3115, 3114, 3112, 3116, 3127, 3124, 3122, 3121, 3119);\n";
642cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = 0LL;\n";
643cp.code() += "etiss_coverage_count(5, 3135, 3133, 3132, 3130, 3134);\n";
644cp.code() += "} // conditional\n";
645cp.code() += "else { // conditional\n";
646cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) % (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
647cp.code() += "etiss_coverage_count(13, 3156, 3140, 3139, 3137, 3155, 3147, 3145, 3144, 3142, 3154, 3152, 3151, 3149);\n";
648cp.code() += "} // conditional\n";
649cp.code() += "} // block\n";
650} // block
651cp.code() += "} // conditional\n";
652cp.code() += "else { // conditional\n";
653cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
654cp.code() += "etiss_coverage_count(7, 3168, 3162, 3161, 3159, 3167, 3166, 3164);\n";
655cp.code() += "} // conditional\n";
656cp.code() += "} // block\n";
657} // block
658} // conditional
659cp.code() += "} // block\n";
660} // block
661cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
662cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
663// -----------------------------------------------------------------------------
664 cp.getAffectedRegisters().add("instructionPointer", 32);
665 }
666
667 return true;
668 },
669 0,
670 [] (BitArray & ba, Instruction & instr)
671 {
672// -----------------------------------------------------------------------------
673etiss_uint8 rd = 0;
674static BitArrayRange R_rd_0(11, 7);
675rd += R_rd_0.read(ba) << 0;
676etiss_uint8 rs1 = 0;
677static BitArrayRange R_rs1_0(19, 15);
678rs1 += R_rs1_0.read(ba) << 0;
679etiss_uint8 rs2 = 0;
680static BitArrayRange R_rs2_0(24, 20);
681rs2 += R_rs2_0.read(ba) << 0;
682
683// -----------------------------------------------------------------------------
684
685 std::stringstream ss;
686// -----------------------------------------------------------------------------
687ss << "rem" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
688// -----------------------------------------------------------------------------
689 return ss.str();
690 }
691);
692
693// REMU ------------------------------------------------------------------------
694static InstructionDefinition remu_rd_rs1_rs2 (
695 ISA32_RV32IMACFD,
696 "remu",
697 (uint32_t) 0x2007033,
698 (uint32_t) 0xfe00707f,
699 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
700 {
701
702// -----------------------------------------------------------------------------
703
704// -----------------------------------------------------------------------------
705
706// -----------------------------------------------------------------------------
707etiss_uint8 rd = 0;
708static BitArrayRange R_rd_0(11, 7);
709rd += R_rd_0.read(ba) << 0;
710etiss_uint8 rs1 = 0;
711static BitArrayRange R_rs1_0(19, 15);
712rs1 += R_rs1_0.read(ba) << 0;
713etiss_uint8 rs2 = 0;
714static BitArrayRange R_rs2_0(24, 20);
715rs2 += R_rs2_0.read(ba) << 0;
716
717// -----------------------------------------------------------------------------
718
719 {
720 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
721
722 cp.code() = std::string("//REMU\n");
723
724// -----------------------------------------------------------------------------
725cp.code() += "etiss_coverage_count(1, 79);\n";
726{ // block
727cp.code() += "etiss_coverage_count(1, 1169);\n";
728cp.code() += "{ // block\n";
729cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
730cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
731cp.code() += "} // block\n";
732} // block
733{ // block
734cp.code() += "etiss_coverage_count(1, 3215);\n";
735cp.code() += "{ // block\n";
736cp.code() += "etiss_coverage_count(1, 3171);\n";
737if ((rd % 32ULL) != 0LL) { // conditional
738cp.code() += "etiss_coverage_count(5, 3177, 3174, 3172, 3175, 3176);\n";
739{ // block
740cp.code() += "etiss_coverage_count(1, 3214);\n";
741cp.code() += "{ // block\n";
742cp.code() += "etiss_coverage_count(1, 3178);\n";
743cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0LL) { // conditional\n";
744cp.code() += "etiss_coverage_count(5, 3185, 3183, 3182, 3180, 3184);\n";
745cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] % *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
746cp.code() += "etiss_coverage_count(11, 3202, 3190, 3189, 3187, 3201, 3195, 3194, 3192, 3200, 3199, 3197);\n";
747cp.code() += "} // conditional\n";
748cp.code() += "else { // conditional\n";
749cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
750cp.code() += "etiss_coverage_count(7, 3213, 3207, 3206, 3204, 3212, 3211, 3209);\n";
751cp.code() += "} // conditional\n";
752cp.code() += "} // block\n";
753} // block
754} // conditional
755cp.code() += "} // block\n";
756} // block
757cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
758cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
759// -----------------------------------------------------------------------------
760 cp.getAffectedRegisters().add("instructionPointer", 32);
761 }
762
763 return true;
764 },
765 0,
766 [] (BitArray & ba, Instruction & instr)
767 {
768// -----------------------------------------------------------------------------
769etiss_uint8 rd = 0;
770static BitArrayRange R_rd_0(11, 7);
771rd += R_rd_0.read(ba) << 0;
772etiss_uint8 rs1 = 0;
773static BitArrayRange R_rs1_0(19, 15);
774rs1 += R_rs1_0.read(ba) << 0;
775etiss_uint8 rs2 = 0;
776static BitArrayRange R_rs2_0(24, 20);
777rs2 += R_rs2_0.read(ba) << 0;
778
779// -----------------------------------------------------------------------------
780
781 std::stringstream ss;
782// -----------------------------------------------------------------------------
783ss << "remu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
784// -----------------------------------------------------------------------------
785 return ss.str();
786 }
787);
ISA32_RV32IMACFD
etiss::instr::InstructionGroup ISA32_RV32IMACFD("ISA32_RV32IMACFD", 32)
divu_rd_rs1_rs2
static InstructionDefinition divu_rd_rs1_rs2(ISA32_RV32IMACFD, "divu",(uint32_t) 0x2005033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//DIVU\n");cp.code()+="etiss_coverage_count(1, 77);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3086);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3045);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3051, 3048, 3046, 3049, 3050);\n";{ cp.code()+="etiss_coverage_count(1, 3085);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3052);\n";cp.code()+="if (*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 3059, 3057, 3056, 3054, 3058);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] / *((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 3076, 3064, 3063, 3061, 3075, 3069, 3068, 3066, 3074, 3073, 3071);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = -1LL;\n";cp.code()+="etiss_coverage_count(4, 3084, 3081, 3080, 3078);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "divu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
mulh_rd_rs1_rs2
static InstructionDefinition mulh_rd_rs1_rs2(ISA32_RV32IMACFD, "mulh",(uint32_t) 0x2001033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MULH\n");cp.code()+="etiss_coverage_count(1, 73);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2886);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2847);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2853, 2850, 2848, 2851, 2852);\n";{ cp.code()+="etiss_coverage_count(1, 2885);\n";cp.code()+="{ // block\n";cp.code()+="etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL])) * (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]));\n";cp.code()+="etiss_coverage_count(12, 2872, 2871, 2862, 2860, 2859, 2858, 2856, 2870, 2868, 2867, 2866, 2864);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint32)((res >> 32ULL));\n";cp.code()+="etiss_coverage_count(8, 2884, 2877, 2876, 2874, 2883, 2880, 2878, 2881);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "mulh"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
rem_rd_rs1_rs2
static InstructionDefinition rem_rd_rs1_rs2(ISA32_RV32IMACFD, "rem",(uint32_t) 0x2006033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//REM\n");cp.code()+="etiss_coverage_count(1, 78);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3170);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3087);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3093, 3090, 3088, 3091, 3092);\n";{ cp.code()+="etiss_coverage_count(1, 3169);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3094);\n";cp.code()+="if (*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 3101, 3099, 3098, 3096, 3100);\n";{ cp.code()+="etiss_coverage_count(1, 3157);\n";cp.code()+="{ // block\n";etiss_uint32 MMIN=2147483648ULL;cp.code()+="etiss_coverage_count(1, 3109);\n";cp.code()+="etiss_coverage_count(1, 3110);\n";cp.code()+="if (*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] == "+std::to_string(MMIN)+"ULL && (etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) == -1LL) { // conditional\n";cp.code()+="etiss_coverage_count(11, 3128, 3117, 3115, 3114, 3112, 3116, 3127, 3124, 3122, 3121, 3119);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = 0LL;\n";cp.code()+="etiss_coverage_count(5, 3135, 3133, 3132, 3130, 3134);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) % (etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(13, 3156, 3140, 3139, 3137, 3155, 3147, 3145, 3144, 3142, 3154, 3152, 3151, 3149);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(7, 3168, 3162, 3161, 3159, 3167, 3166, 3164);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "rem"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
div_rd_rs1_rs2
static InstructionDefinition div_rd_rs1_rs2(ISA32_RV32IMACFD, "div",(uint32_t) 0x2004033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//DIV\n");cp.code()+="etiss_coverage_count(1, 76);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3044);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2964);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2970, 2967, 2965, 2968, 2969);\n";{ cp.code()+="etiss_coverage_count(1, 3043);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2971);\n";cp.code()+="if (*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 2978, 2976, 2975, 2973, 2977);\n";{ cp.code()+="etiss_coverage_count(1, 3034);\n";cp.code()+="{ // block\n";etiss_uint32 MMIN=2147483648ULL;cp.code()+="etiss_coverage_count(1, 2986);\n";cp.code()+="etiss_coverage_count(1, 2987);\n";cp.code()+="if (*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] == "+std::to_string(MMIN)+"ULL && (etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) == -1LL) { // conditional\n";cp.code()+="etiss_coverage_count(11, 3005, 2994, 2992, 2991, 2989, 2993, 3004, 3001, 2999, 2998, 2996);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string(MMIN)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 3012, 3010, 3009, 3007, 3011);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) / (etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(13, 3033, 3017, 3016, 3014, 3032, 3024, 3022, 3021, 3019, 3031, 3029, 3028, 3026);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = -1LL;\n";cp.code()+="etiss_coverage_count(4, 3042, 3039, 3038, 3036);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "div"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
mulhsu_rd_rs1_rs2
static InstructionDefinition mulhsu_rd_rs1_rs2(ISA32_RV32IMACFD, "mulhsu",(uint32_t) 0x2002033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MULHSU\n");cp.code()+="etiss_coverage_count(1, 74);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2925);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2887);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2893, 2890, 2888, 2891, 2892);\n";{ cp.code()+="etiss_coverage_count(1, 2924);\n";cp.code()+="{ // block\n";cp.code()+="etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL])) * (etiss_uint64)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(11, 2911, 2910, 2902, 2900, 2899, 2898, 2896, 2909, 2907, 2906, 2904);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint32)((res >> 32ULL));\n";cp.code()+="etiss_coverage_count(8, 2923, 2916, 2915, 2913, 2922, 2919, 2917, 2920);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "mulhsu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
mulhu_rd_rs1_rs2
static InstructionDefinition mulhu_rd_rs1_rs2(ISA32_RV32IMACFD, "mulhu",(uint32_t) 0x2003033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MULHU\n");cp.code()+="etiss_coverage_count(1, 75);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2963);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2926);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2932, 2929, 2927, 2930, 2931);\n";{ cp.code()+="etiss_coverage_count(1, 2962);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = (etiss_uint64)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) * (etiss_uint64)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(10, 2949, 2948, 2940, 2938, 2937, 2935, 2947, 2945, 2944, 2942);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint32)((res >> 32ULL));\n";cp.code()+="etiss_coverage_count(8, 2961, 2954, 2953, 2951, 2960, 2957, 2955, 2958);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "mulhu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
mul_rd_rs1_rs2
static InstructionDefinition mul_rd_rs1_rs2(ISA32_RV32IMACFD, "mul",(uint32_t) 0x2000033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MUL\n");cp.code()+="etiss_coverage_count(1, 72);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2846);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2810);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2816, 2813, 2811, 2814, 2815);\n";{ cp.code()+="etiss_coverage_count(1, 2845);\n";cp.code()+="{ // block\n";cp.code()+="etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL])) * (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]));\n";cp.code()+="etiss_coverage_count(12, 2835, 2834, 2825, 2823, 2822, 2821, 2819, 2833, 2831, 2830, 2829, 2827);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint32)(res);\n";cp.code()+="etiss_coverage_count(6, 2844, 2840, 2839, 2837, 2843, 2841);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "mul"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
remu_rd_rs1_rs2
static InstructionDefinition remu_rd_rs1_rs2(ISA32_RV32IMACFD, "remu",(uint32_t) 0x2007033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//REMU\n");cp.code()+="etiss_coverage_count(1, 79);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3215);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3171);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3177, 3174, 3172, 3175, 3176);\n";{ cp.code()+="etiss_coverage_count(1, 3214);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3178);\n";cp.code()+="if (*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 3185, 3183, 3182, 3180, 3184);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] % *((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 3202, 3190, 3189, 3187, 3201, 3195, 3194, 3192, 3200, 3199, 3197);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(7, 3213, 3207, 3206, 3204, 3212, 3211, 3209);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "remu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
etiss_uint32
uint32_t etiss_uint32
Definition types.h:93
etiss_uint8
uint8_t etiss_uint8
Definition types.h:87
etiss::CodePart
Contains a small code snipped.
Definition CodePart.h:386
etiss::CodePart::code
std::string & code()
Definition CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition Benchmark.h:53
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