ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV32IMACFD_RV32MInstr.cpp
Go to the documentation of this file.
1 
8 #include "RV32IMACFDArch.h"
9 #include "RV32IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // MUL -------------------------------------------------------------------------
16 static InstructionDefinition mul_rd_rs1_rs2 (
17  ISA32_RV32IMACFD,
18  "mul",
19  (uint32_t) 0x2000033,
20  (uint32_t) 0xfe00707f,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 etiss_uint8 rd = 0;
30 static BitArrayRange R_rd_0(11, 7);
31 rd += R_rd_0.read(ba) << 0;
32 etiss_uint8 rs1 = 0;
33 static BitArrayRange R_rs1_0(19, 15);
34 rs1 += R_rs1_0.read(ba) << 0;
35 etiss_uint8 rs2 = 0;
36 static BitArrayRange R_rs2_0(24, 20);
37 rs2 += R_rs2_0.read(ba) << 0;
38 
39 // -----------------------------------------------------------------------------
40 
41  {
42  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
43 
44  cp.code() = std::string("//MUL\n");
45 
46 // -----------------------------------------------------------------------------
47 cp.code() += "etiss_coverage_count(1, 72);\n";
48 { // block
49 cp.code() += "etiss_coverage_count(1, 1169);\n";
50 cp.code() += "{ // block\n";
51 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
52 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
53 cp.code() += "} // block\n";
54 } // block
55 { // block
56 cp.code() += "etiss_coverage_count(1, 2846);\n";
57 cp.code() += "{ // block\n";
58 cp.code() += "etiss_coverage_count(1, 2810);\n";
59 if ((rd % 32ULL) != 0LL) { // conditional
60 cp.code() += "etiss_coverage_count(5, 2816, 2813, 2811, 2814, 2815);\n";
61 { // block
62 cp.code() += "etiss_coverage_count(1, 2845);\n";
63 cp.code() += "{ // block\n";
64 cp.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) * (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]));\n";
65 cp.code() += "etiss_coverage_count(12, 2835, 2834, 2825, 2823, 2822, 2821, 2819, 2833, 2831, 2830, 2829, 2827);\n";
66 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)(res);\n";
67 cp.code() += "etiss_coverage_count(6, 2844, 2840, 2839, 2837, 2843, 2841);\n";
68 cp.code() += "} // block\n";
69 } // block
70 } // conditional
71 cp.code() += "} // block\n";
72 } // block
73 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
74 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
75 // -----------------------------------------------------------------------------
76  cp.getAffectedRegisters().add("instructionPointer", 32);
77  }
78 
79  return true;
80  },
81  0,
82  [] (BitArray & ba, Instruction & instr)
83  {
84 // -----------------------------------------------------------------------------
85 etiss_uint8 rd = 0;
86 static BitArrayRange R_rd_0(11, 7);
87 rd += R_rd_0.read(ba) << 0;
88 etiss_uint8 rs1 = 0;
89 static BitArrayRange R_rs1_0(19, 15);
90 rs1 += R_rs1_0.read(ba) << 0;
91 etiss_uint8 rs2 = 0;
92 static BitArrayRange R_rs2_0(24, 20);
93 rs2 += R_rs2_0.read(ba) << 0;
94 
95 // -----------------------------------------------------------------------------
96 
97  std::stringstream ss;
98 // -----------------------------------------------------------------------------
99 ss << "mul" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
100 // -----------------------------------------------------------------------------
101  return ss.str();
102  }
103 );
104 
105 // MULH ------------------------------------------------------------------------
106 static InstructionDefinition mulh_rd_rs1_rs2 (
107  ISA32_RV32IMACFD,
108  "mulh",
109  (uint32_t) 0x2001033,
110  (uint32_t) 0xfe00707f,
111  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
112  {
113 
114 // -----------------------------------------------------------------------------
115 
116 // -----------------------------------------------------------------------------
117 
118 // -----------------------------------------------------------------------------
119 etiss_uint8 rd = 0;
120 static BitArrayRange R_rd_0(11, 7);
121 rd += R_rd_0.read(ba) << 0;
122 etiss_uint8 rs1 = 0;
123 static BitArrayRange R_rs1_0(19, 15);
124 rs1 += R_rs1_0.read(ba) << 0;
125 etiss_uint8 rs2 = 0;
126 static BitArrayRange R_rs2_0(24, 20);
127 rs2 += R_rs2_0.read(ba) << 0;
128 
129 // -----------------------------------------------------------------------------
130 
131  {
132  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
133 
134  cp.code() = std::string("//MULH\n");
135 
136 // -----------------------------------------------------------------------------
137 cp.code() += "etiss_coverage_count(1, 73);\n";
138 { // block
139 cp.code() += "etiss_coverage_count(1, 1169);\n";
140 cp.code() += "{ // block\n";
141 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
142 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
143 cp.code() += "} // block\n";
144 } // block
145 { // block
146 cp.code() += "etiss_coverage_count(1, 2886);\n";
147 cp.code() += "{ // block\n";
148 cp.code() += "etiss_coverage_count(1, 2847);\n";
149 if ((rd % 32ULL) != 0LL) { // conditional
150 cp.code() += "etiss_coverage_count(5, 2853, 2850, 2848, 2851, 2852);\n";
151 { // block
152 cp.code() += "etiss_coverage_count(1, 2885);\n";
153 cp.code() += "{ // block\n";
154 cp.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) * (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]));\n";
155 cp.code() += "etiss_coverage_count(12, 2872, 2871, 2862, 2860, 2859, 2858, 2856, 2870, 2868, 2867, 2866, 2864);\n";
156 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)((res >> 32ULL));\n";
157 cp.code() += "etiss_coverage_count(8, 2884, 2877, 2876, 2874, 2883, 2880, 2878, 2881);\n";
158 cp.code() += "} // block\n";
159 } // block
160 } // conditional
161 cp.code() += "} // block\n";
162 } // block
163 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
164 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
165 // -----------------------------------------------------------------------------
166  cp.getAffectedRegisters().add("instructionPointer", 32);
167  }
168 
169  return true;
170  },
171  0,
172  [] (BitArray & ba, Instruction & instr)
173  {
174 // -----------------------------------------------------------------------------
175 etiss_uint8 rd = 0;
176 static BitArrayRange R_rd_0(11, 7);
177 rd += R_rd_0.read(ba) << 0;
178 etiss_uint8 rs1 = 0;
179 static BitArrayRange R_rs1_0(19, 15);
180 rs1 += R_rs1_0.read(ba) << 0;
181 etiss_uint8 rs2 = 0;
182 static BitArrayRange R_rs2_0(24, 20);
183 rs2 += R_rs2_0.read(ba) << 0;
184 
185 // -----------------------------------------------------------------------------
186 
187  std::stringstream ss;
188 // -----------------------------------------------------------------------------
189 ss << "mulh" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
190 // -----------------------------------------------------------------------------
191  return ss.str();
192  }
193 );
194 
195 // MULHSU ----------------------------------------------------------------------
196 static InstructionDefinition mulhsu_rd_rs1_rs2 (
197  ISA32_RV32IMACFD,
198  "mulhsu",
199  (uint32_t) 0x2002033,
200  (uint32_t) 0xfe00707f,
201  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
202  {
203 
204 // -----------------------------------------------------------------------------
205 
206 // -----------------------------------------------------------------------------
207 
208 // -----------------------------------------------------------------------------
209 etiss_uint8 rd = 0;
210 static BitArrayRange R_rd_0(11, 7);
211 rd += R_rd_0.read(ba) << 0;
212 etiss_uint8 rs1 = 0;
213 static BitArrayRange R_rs1_0(19, 15);
214 rs1 += R_rs1_0.read(ba) << 0;
215 etiss_uint8 rs2 = 0;
216 static BitArrayRange R_rs2_0(24, 20);
217 rs2 += R_rs2_0.read(ba) << 0;
218 
219 // -----------------------------------------------------------------------------
220 
221  {
222  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
223 
224  cp.code() = std::string("//MULHSU\n");
225 
226 // -----------------------------------------------------------------------------
227 cp.code() += "etiss_coverage_count(1, 74);\n";
228 { // block
229 cp.code() += "etiss_coverage_count(1, 1169);\n";
230 cp.code() += "{ // block\n";
231 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
232 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
233 cp.code() += "} // block\n";
234 } // block
235 { // block
236 cp.code() += "etiss_coverage_count(1, 2925);\n";
237 cp.code() += "{ // block\n";
238 cp.code() += "etiss_coverage_count(1, 2887);\n";
239 if ((rd % 32ULL) != 0LL) { // conditional
240 cp.code() += "etiss_coverage_count(5, 2893, 2890, 2888, 2891, 2892);\n";
241 { // block
242 cp.code() += "etiss_coverage_count(1, 2924);\n";
243 cp.code() += "{ // block\n";
244 cp.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) * (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
245 cp.code() += "etiss_coverage_count(11, 2911, 2910, 2902, 2900, 2899, 2898, 2896, 2909, 2907, 2906, 2904);\n";
246 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)((res >> 32ULL));\n";
247 cp.code() += "etiss_coverage_count(8, 2923, 2916, 2915, 2913, 2922, 2919, 2917, 2920);\n";
248 cp.code() += "} // block\n";
249 } // block
250 } // conditional
251 cp.code() += "} // block\n";
252 } // block
253 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
254 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
255 // -----------------------------------------------------------------------------
256  cp.getAffectedRegisters().add("instructionPointer", 32);
257  }
258 
259  return true;
260  },
261  0,
262  [] (BitArray & ba, Instruction & instr)
263  {
264 // -----------------------------------------------------------------------------
265 etiss_uint8 rd = 0;
266 static BitArrayRange R_rd_0(11, 7);
267 rd += R_rd_0.read(ba) << 0;
268 etiss_uint8 rs1 = 0;
269 static BitArrayRange R_rs1_0(19, 15);
270 rs1 += R_rs1_0.read(ba) << 0;
271 etiss_uint8 rs2 = 0;
272 static BitArrayRange R_rs2_0(24, 20);
273 rs2 += R_rs2_0.read(ba) << 0;
274 
275 // -----------------------------------------------------------------------------
276 
277  std::stringstream ss;
278 // -----------------------------------------------------------------------------
279 ss << "mulhsu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
280 // -----------------------------------------------------------------------------
281  return ss.str();
282  }
283 );
284 
285 // MULHU -----------------------------------------------------------------------
286 static InstructionDefinition mulhu_rd_rs1_rs2 (
287  ISA32_RV32IMACFD,
288  "mulhu",
289  (uint32_t) 0x2003033,
290  (uint32_t) 0xfe00707f,
291  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
292  {
293 
294 // -----------------------------------------------------------------------------
295 
296 // -----------------------------------------------------------------------------
297 
298 // -----------------------------------------------------------------------------
299 etiss_uint8 rd = 0;
300 static BitArrayRange R_rd_0(11, 7);
301 rd += R_rd_0.read(ba) << 0;
302 etiss_uint8 rs1 = 0;
303 static BitArrayRange R_rs1_0(19, 15);
304 rs1 += R_rs1_0.read(ba) << 0;
305 etiss_uint8 rs2 = 0;
306 static BitArrayRange R_rs2_0(24, 20);
307 rs2 += R_rs2_0.read(ba) << 0;
308 
309 // -----------------------------------------------------------------------------
310 
311  {
312  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
313 
314  cp.code() = std::string("//MULHU\n");
315 
316 // -----------------------------------------------------------------------------
317 cp.code() += "etiss_coverage_count(1, 75);\n";
318 { // block
319 cp.code() += "etiss_coverage_count(1, 1169);\n";
320 cp.code() += "{ // block\n";
321 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
322 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
323 cp.code() += "} // block\n";
324 } // block
325 { // block
326 cp.code() += "etiss_coverage_count(1, 2963);\n";
327 cp.code() += "{ // block\n";
328 cp.code() += "etiss_coverage_count(1, 2926);\n";
329 if ((rd % 32ULL) != 0LL) { // conditional
330 cp.code() += "etiss_coverage_count(5, 2932, 2929, 2927, 2930, 2931);\n";
331 { // block
332 cp.code() += "etiss_coverage_count(1, 2962);\n";
333 cp.code() += "{ // block\n";
334 cp.code() += "etiss_uint64 res = (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) * (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
335 cp.code() += "etiss_coverage_count(10, 2949, 2948, 2940, 2938, 2937, 2935, 2947, 2945, 2944, 2942);\n";
336 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)((res >> 32ULL));\n";
337 cp.code() += "etiss_coverage_count(8, 2961, 2954, 2953, 2951, 2960, 2957, 2955, 2958);\n";
338 cp.code() += "} // block\n";
339 } // block
340 } // conditional
341 cp.code() += "} // block\n";
342 } // block
343 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
344 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
345 // -----------------------------------------------------------------------------
346  cp.getAffectedRegisters().add("instructionPointer", 32);
347  }
348 
349  return true;
350  },
351  0,
352  [] (BitArray & ba, Instruction & instr)
353  {
354 // -----------------------------------------------------------------------------
355 etiss_uint8 rd = 0;
356 static BitArrayRange R_rd_0(11, 7);
357 rd += R_rd_0.read(ba) << 0;
358 etiss_uint8 rs1 = 0;
359 static BitArrayRange R_rs1_0(19, 15);
360 rs1 += R_rs1_0.read(ba) << 0;
361 etiss_uint8 rs2 = 0;
362 static BitArrayRange R_rs2_0(24, 20);
363 rs2 += R_rs2_0.read(ba) << 0;
364 
365 // -----------------------------------------------------------------------------
366 
367  std::stringstream ss;
368 // -----------------------------------------------------------------------------
369 ss << "mulhu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
370 // -----------------------------------------------------------------------------
371  return ss.str();
372  }
373 );
374 
375 // DIV -------------------------------------------------------------------------
376 static InstructionDefinition div_rd_rs1_rs2 (
377  ISA32_RV32IMACFD,
378  "div",
379  (uint32_t) 0x2004033,
380  (uint32_t) 0xfe00707f,
381  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
382  {
383 
384 // -----------------------------------------------------------------------------
385 
386 // -----------------------------------------------------------------------------
387 
388 // -----------------------------------------------------------------------------
389 etiss_uint8 rd = 0;
390 static BitArrayRange R_rd_0(11, 7);
391 rd += R_rd_0.read(ba) << 0;
392 etiss_uint8 rs1 = 0;
393 static BitArrayRange R_rs1_0(19, 15);
394 rs1 += R_rs1_0.read(ba) << 0;
395 etiss_uint8 rs2 = 0;
396 static BitArrayRange R_rs2_0(24, 20);
397 rs2 += R_rs2_0.read(ba) << 0;
398 
399 // -----------------------------------------------------------------------------
400 
401  {
402  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
403 
404  cp.code() = std::string("//DIV\n");
405 
406 // -----------------------------------------------------------------------------
407 cp.code() += "etiss_coverage_count(1, 76);\n";
408 { // block
409 cp.code() += "etiss_coverage_count(1, 1169);\n";
410 cp.code() += "{ // block\n";
411 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
412 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
413 cp.code() += "} // block\n";
414 } // block
415 { // block
416 cp.code() += "etiss_coverage_count(1, 3044);\n";
417 cp.code() += "{ // block\n";
418 cp.code() += "etiss_coverage_count(1, 2964);\n";
419 if ((rd % 32ULL) != 0LL) { // conditional
420 cp.code() += "etiss_coverage_count(5, 2970, 2967, 2965, 2968, 2969);\n";
421 { // block
422 cp.code() += "etiss_coverage_count(1, 3043);\n";
423 cp.code() += "{ // block\n";
424 cp.code() += "etiss_coverage_count(1, 2971);\n";
425 cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0LL) { // conditional\n";
426 cp.code() += "etiss_coverage_count(5, 2978, 2976, 2975, 2973, 2977);\n";
427 { // block
428 cp.code() += "etiss_coverage_count(1, 3034);\n";
429 cp.code() += "{ // block\n";
430 etiss_uint32 MMIN = 2147483648ULL;
431 cp.code() += "etiss_coverage_count(1, 2986);\n";
432 cp.code() += "etiss_coverage_count(1, 2987);\n";
433 cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] == " + std::to_string(MMIN) + "ULL && (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) == -1LL) { // conditional\n";
434 cp.code() += "etiss_coverage_count(11, 3005, 2994, 2992, 2991, 2989, 2993, 3004, 3001, 2999, 2998, 2996);\n";
435 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(MMIN) + "ULL;\n";
436 cp.code() += "etiss_coverage_count(5, 3012, 3010, 3009, 3007, 3011);\n";
437 cp.code() += "} // conditional\n";
438 cp.code() += "else { // conditional\n";
439 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) / (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
440 cp.code() += "etiss_coverage_count(13, 3033, 3017, 3016, 3014, 3032, 3024, 3022, 3021, 3019, 3031, 3029, 3028, 3026);\n";
441 cp.code() += "} // conditional\n";
442 cp.code() += "} // block\n";
443 } // block
444 cp.code() += "} // conditional\n";
445 cp.code() += "else { // conditional\n";
446 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -1LL;\n";
447 cp.code() += "etiss_coverage_count(4, 3042, 3039, 3038, 3036);\n";
448 cp.code() += "} // conditional\n";
449 cp.code() += "} // block\n";
450 } // block
451 } // conditional
452 cp.code() += "} // block\n";
453 } // block
454 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
455 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
456 // -----------------------------------------------------------------------------
457  cp.getAffectedRegisters().add("instructionPointer", 32);
458  }
459 
460  return true;
461  },
462  0,
463  [] (BitArray & ba, Instruction & instr)
464  {
465 // -----------------------------------------------------------------------------
466 etiss_uint8 rd = 0;
467 static BitArrayRange R_rd_0(11, 7);
468 rd += R_rd_0.read(ba) << 0;
469 etiss_uint8 rs1 = 0;
470 static BitArrayRange R_rs1_0(19, 15);
471 rs1 += R_rs1_0.read(ba) << 0;
472 etiss_uint8 rs2 = 0;
473 static BitArrayRange R_rs2_0(24, 20);
474 rs2 += R_rs2_0.read(ba) << 0;
475 
476 // -----------------------------------------------------------------------------
477 
478  std::stringstream ss;
479 // -----------------------------------------------------------------------------
480 ss << "div" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
481 // -----------------------------------------------------------------------------
482  return ss.str();
483  }
484 );
485 
486 // DIVU ------------------------------------------------------------------------
487 static InstructionDefinition divu_rd_rs1_rs2 (
488  ISA32_RV32IMACFD,
489  "divu",
490  (uint32_t) 0x2005033,
491  (uint32_t) 0xfe00707f,
492  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
493  {
494 
495 // -----------------------------------------------------------------------------
496 
497 // -----------------------------------------------------------------------------
498 
499 // -----------------------------------------------------------------------------
500 etiss_uint8 rd = 0;
501 static BitArrayRange R_rd_0(11, 7);
502 rd += R_rd_0.read(ba) << 0;
503 etiss_uint8 rs1 = 0;
504 static BitArrayRange R_rs1_0(19, 15);
505 rs1 += R_rs1_0.read(ba) << 0;
506 etiss_uint8 rs2 = 0;
507 static BitArrayRange R_rs2_0(24, 20);
508 rs2 += R_rs2_0.read(ba) << 0;
509 
510 // -----------------------------------------------------------------------------
511 
512  {
513  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
514 
515  cp.code() = std::string("//DIVU\n");
516 
517 // -----------------------------------------------------------------------------
518 cp.code() += "etiss_coverage_count(1, 77);\n";
519 { // block
520 cp.code() += "etiss_coverage_count(1, 1169);\n";
521 cp.code() += "{ // block\n";
522 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
523 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
524 cp.code() += "} // block\n";
525 } // block
526 { // block
527 cp.code() += "etiss_coverage_count(1, 3086);\n";
528 cp.code() += "{ // block\n";
529 cp.code() += "etiss_coverage_count(1, 3045);\n";
530 if ((rd % 32ULL) != 0LL) { // conditional
531 cp.code() += "etiss_coverage_count(5, 3051, 3048, 3046, 3049, 3050);\n";
532 { // block
533 cp.code() += "etiss_coverage_count(1, 3085);\n";
534 cp.code() += "{ // block\n";
535 cp.code() += "etiss_coverage_count(1, 3052);\n";
536 cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0LL) { // conditional\n";
537 cp.code() += "etiss_coverage_count(5, 3059, 3057, 3056, 3054, 3058);\n";
538 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] / *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
539 cp.code() += "etiss_coverage_count(11, 3076, 3064, 3063, 3061, 3075, 3069, 3068, 3066, 3074, 3073, 3071);\n";
540 cp.code() += "} // conditional\n";
541 cp.code() += "else { // conditional\n";
542 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -1LL;\n";
543 cp.code() += "etiss_coverage_count(4, 3084, 3081, 3080, 3078);\n";
544 cp.code() += "} // conditional\n";
545 cp.code() += "} // block\n";
546 } // block
547 } // conditional
548 cp.code() += "} // block\n";
549 } // block
550 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
551 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
552 // -----------------------------------------------------------------------------
553  cp.getAffectedRegisters().add("instructionPointer", 32);
554  }
555 
556  return true;
557  },
558  0,
559  [] (BitArray & ba, Instruction & instr)
560  {
561 // -----------------------------------------------------------------------------
562 etiss_uint8 rd = 0;
563 static BitArrayRange R_rd_0(11, 7);
564 rd += R_rd_0.read(ba) << 0;
565 etiss_uint8 rs1 = 0;
566 static BitArrayRange R_rs1_0(19, 15);
567 rs1 += R_rs1_0.read(ba) << 0;
568 etiss_uint8 rs2 = 0;
569 static BitArrayRange R_rs2_0(24, 20);
570 rs2 += R_rs2_0.read(ba) << 0;
571 
572 // -----------------------------------------------------------------------------
573 
574  std::stringstream ss;
575 // -----------------------------------------------------------------------------
576 ss << "divu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
577 // -----------------------------------------------------------------------------
578  return ss.str();
579  }
580 );
581 
582 // REM -------------------------------------------------------------------------
583 static InstructionDefinition rem_rd_rs1_rs2 (
584  ISA32_RV32IMACFD,
585  "rem",
586  (uint32_t) 0x2006033,
587  (uint32_t) 0xfe00707f,
588  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
589  {
590 
591 // -----------------------------------------------------------------------------
592 
593 // -----------------------------------------------------------------------------
594 
595 // -----------------------------------------------------------------------------
596 etiss_uint8 rd = 0;
597 static BitArrayRange R_rd_0(11, 7);
598 rd += R_rd_0.read(ba) << 0;
599 etiss_uint8 rs1 = 0;
600 static BitArrayRange R_rs1_0(19, 15);
601 rs1 += R_rs1_0.read(ba) << 0;
602 etiss_uint8 rs2 = 0;
603 static BitArrayRange R_rs2_0(24, 20);
604 rs2 += R_rs2_0.read(ba) << 0;
605 
606 // -----------------------------------------------------------------------------
607 
608  {
609  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
610 
611  cp.code() = std::string("//REM\n");
612 
613 // -----------------------------------------------------------------------------
614 cp.code() += "etiss_coverage_count(1, 78);\n";
615 { // block
616 cp.code() += "etiss_coverage_count(1, 1169);\n";
617 cp.code() += "{ // block\n";
618 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
619 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
620 cp.code() += "} // block\n";
621 } // block
622 { // block
623 cp.code() += "etiss_coverage_count(1, 3170);\n";
624 cp.code() += "{ // block\n";
625 cp.code() += "etiss_coverage_count(1, 3087);\n";
626 if ((rd % 32ULL) != 0LL) { // conditional
627 cp.code() += "etiss_coverage_count(5, 3093, 3090, 3088, 3091, 3092);\n";
628 { // block
629 cp.code() += "etiss_coverage_count(1, 3169);\n";
630 cp.code() += "{ // block\n";
631 cp.code() += "etiss_coverage_count(1, 3094);\n";
632 cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0LL) { // conditional\n";
633 cp.code() += "etiss_coverage_count(5, 3101, 3099, 3098, 3096, 3100);\n";
634 { // block
635 cp.code() += "etiss_coverage_count(1, 3157);\n";
636 cp.code() += "{ // block\n";
637 etiss_uint32 MMIN = 2147483648ULL;
638 cp.code() += "etiss_coverage_count(1, 3109);\n";
639 cp.code() += "etiss_coverage_count(1, 3110);\n";
640 cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] == " + std::to_string(MMIN) + "ULL && (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) == -1LL) { // conditional\n";
641 cp.code() += "etiss_coverage_count(11, 3128, 3117, 3115, 3114, 3112, 3116, 3127, 3124, 3122, 3121, 3119);\n";
642 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = 0LL;\n";
643 cp.code() += "etiss_coverage_count(5, 3135, 3133, 3132, 3130, 3134);\n";
644 cp.code() += "} // conditional\n";
645 cp.code() += "else { // conditional\n";
646 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) % (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
647 cp.code() += "etiss_coverage_count(13, 3156, 3140, 3139, 3137, 3155, 3147, 3145, 3144, 3142, 3154, 3152, 3151, 3149);\n";
648 cp.code() += "} // conditional\n";
649 cp.code() += "} // block\n";
650 } // block
651 cp.code() += "} // conditional\n";
652 cp.code() += "else { // conditional\n";
653 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
654 cp.code() += "etiss_coverage_count(7, 3168, 3162, 3161, 3159, 3167, 3166, 3164);\n";
655 cp.code() += "} // conditional\n";
656 cp.code() += "} // block\n";
657 } // block
658 } // conditional
659 cp.code() += "} // block\n";
660 } // block
661 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
662 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
663 // -----------------------------------------------------------------------------
664  cp.getAffectedRegisters().add("instructionPointer", 32);
665  }
666 
667  return true;
668  },
669  0,
670  [] (BitArray & ba, Instruction & instr)
671  {
672 // -----------------------------------------------------------------------------
673 etiss_uint8 rd = 0;
674 static BitArrayRange R_rd_0(11, 7);
675 rd += R_rd_0.read(ba) << 0;
676 etiss_uint8 rs1 = 0;
677 static BitArrayRange R_rs1_0(19, 15);
678 rs1 += R_rs1_0.read(ba) << 0;
679 etiss_uint8 rs2 = 0;
680 static BitArrayRange R_rs2_0(24, 20);
681 rs2 += R_rs2_0.read(ba) << 0;
682 
683 // -----------------------------------------------------------------------------
684 
685  std::stringstream ss;
686 // -----------------------------------------------------------------------------
687 ss << "rem" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
688 // -----------------------------------------------------------------------------
689  return ss.str();
690  }
691 );
692 
693 // REMU ------------------------------------------------------------------------
694 static InstructionDefinition remu_rd_rs1_rs2 (
695  ISA32_RV32IMACFD,
696  "remu",
697  (uint32_t) 0x2007033,
698  (uint32_t) 0xfe00707f,
699  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
700  {
701 
702 // -----------------------------------------------------------------------------
703 
704 // -----------------------------------------------------------------------------
705 
706 // -----------------------------------------------------------------------------
707 etiss_uint8 rd = 0;
708 static BitArrayRange R_rd_0(11, 7);
709 rd += R_rd_0.read(ba) << 0;
710 etiss_uint8 rs1 = 0;
711 static BitArrayRange R_rs1_0(19, 15);
712 rs1 += R_rs1_0.read(ba) << 0;
713 etiss_uint8 rs2 = 0;
714 static BitArrayRange R_rs2_0(24, 20);
715 rs2 += R_rs2_0.read(ba) << 0;
716 
717 // -----------------------------------------------------------------------------
718 
719  {
720  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
721 
722  cp.code() = std::string("//REMU\n");
723 
724 // -----------------------------------------------------------------------------
725 cp.code() += "etiss_coverage_count(1, 79);\n";
726 { // block
727 cp.code() += "etiss_coverage_count(1, 1169);\n";
728 cp.code() += "{ // block\n";
729 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
730 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
731 cp.code() += "} // block\n";
732 } // block
733 { // block
734 cp.code() += "etiss_coverage_count(1, 3215);\n";
735 cp.code() += "{ // block\n";
736 cp.code() += "etiss_coverage_count(1, 3171);\n";
737 if ((rd % 32ULL) != 0LL) { // conditional
738 cp.code() += "etiss_coverage_count(5, 3177, 3174, 3172, 3175, 3176);\n";
739 { // block
740 cp.code() += "etiss_coverage_count(1, 3214);\n";
741 cp.code() += "{ // block\n";
742 cp.code() += "etiss_coverage_count(1, 3178);\n";
743 cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0LL) { // conditional\n";
744 cp.code() += "etiss_coverage_count(5, 3185, 3183, 3182, 3180, 3184);\n";
745 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] % *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
746 cp.code() += "etiss_coverage_count(11, 3202, 3190, 3189, 3187, 3201, 3195, 3194, 3192, 3200, 3199, 3197);\n";
747 cp.code() += "} // conditional\n";
748 cp.code() += "else { // conditional\n";
749 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
750 cp.code() += "etiss_coverage_count(7, 3213, 3207, 3206, 3204, 3212, 3211, 3209);\n";
751 cp.code() += "} // conditional\n";
752 cp.code() += "} // block\n";
753 } // block
754 } // conditional
755 cp.code() += "} // block\n";
756 } // block
757 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
758 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
759 // -----------------------------------------------------------------------------
760  cp.getAffectedRegisters().add("instructionPointer", 32);
761  }
762 
763  return true;
764  },
765  0,
766  [] (BitArray & ba, Instruction & instr)
767  {
768 // -----------------------------------------------------------------------------
769 etiss_uint8 rd = 0;
770 static BitArrayRange R_rd_0(11, 7);
771 rd += R_rd_0.read(ba) << 0;
772 etiss_uint8 rs1 = 0;
773 static BitArrayRange R_rs1_0(19, 15);
774 rs1 += R_rs1_0.read(ba) << 0;
775 etiss_uint8 rs2 = 0;
776 static BitArrayRange R_rs2_0(24, 20);
777 rs2 += R_rs2_0.read(ba) << 0;
778 
779 // -----------------------------------------------------------------------------
780 
781  std::stringstream ss;
782 // -----------------------------------------------------------------------------
783 ss << "remu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
784 // -----------------------------------------------------------------------------
785  return ss.str();
786  }
787 );
ISA32_RV32IMACFD
etiss::instr::InstructionGroup ISA32_RV32IMACFD("ISA32_RV32IMACFD", 32)
divu_rd_rs1_rs2
static InstructionDefinition divu_rd_rs1_rs2(ISA32_RV32IMACFD, "divu",(uint32_t) 0x2005033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//DIVU\n");cp.code()+="etiss_coverage_count(1, 77);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3086);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3045);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3051, 3048, 3046, 3049, 3050);\n";{ cp.code()+="etiss_coverage_count(1, 3085);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3052);\n";cp.code()+="if (*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 3059, 3057, 3056, 3054, 3058);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] / *((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 3076, 3064, 3063, 3061, 3075, 3069, 3068, 3066, 3074, 3073, 3071);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = -1LL;\n";cp.code()+="etiss_coverage_count(4, 3084, 3081, 3080, 3078);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "divu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
mulh_rd_rs1_rs2
static InstructionDefinition mulh_rd_rs1_rs2(ISA32_RV32IMACFD, "mulh",(uint32_t) 0x2001033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MULH\n");cp.code()+="etiss_coverage_count(1, 73);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2886);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2847);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2853, 2850, 2848, 2851, 2852);\n";{ cp.code()+="etiss_coverage_count(1, 2885);\n";cp.code()+="{ // block\n";cp.code()+="etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL])) * (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]));\n";cp.code()+="etiss_coverage_count(12, 2872, 2871, 2862, 2860, 2859, 2858, 2856, 2870, 2868, 2867, 2866, 2864);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint32)((res >> 32ULL));\n";cp.code()+="etiss_coverage_count(8, 2884, 2877, 2876, 2874, 2883, 2880, 2878, 2881);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "mulh"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
rem_rd_rs1_rs2
static InstructionDefinition rem_rd_rs1_rs2(ISA32_RV32IMACFD, "rem",(uint32_t) 0x2006033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//REM\n");cp.code()+="etiss_coverage_count(1, 78);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3170);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3087);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3093, 3090, 3088, 3091, 3092);\n";{ cp.code()+="etiss_coverage_count(1, 3169);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3094);\n";cp.code()+="if (*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 3101, 3099, 3098, 3096, 3100);\n";{ cp.code()+="etiss_coverage_count(1, 3157);\n";cp.code()+="{ // block\n";etiss_uint32 MMIN=2147483648ULL;cp.code()+="etiss_coverage_count(1, 3109);\n";cp.code()+="etiss_coverage_count(1, 3110);\n";cp.code()+="if (*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] == "+std::to_string(MMIN)+"ULL && (etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) == -1LL) { // conditional\n";cp.code()+="etiss_coverage_count(11, 3128, 3117, 3115, 3114, 3112, 3116, 3127, 3124, 3122, 3121, 3119);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = 0LL;\n";cp.code()+="etiss_coverage_count(5, 3135, 3133, 3132, 3130, 3134);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) % (etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(13, 3156, 3140, 3139, 3137, 3155, 3147, 3145, 3144, 3142, 3154, 3152, 3151, 3149);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(7, 3168, 3162, 3161, 3159, 3167, 3166, 3164);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "rem"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
div_rd_rs1_rs2
static InstructionDefinition div_rd_rs1_rs2(ISA32_RV32IMACFD, "div",(uint32_t) 0x2004033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//DIV\n");cp.code()+="etiss_coverage_count(1, 76);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3044);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2964);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2970, 2967, 2965, 2968, 2969);\n";{ cp.code()+="etiss_coverage_count(1, 3043);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2971);\n";cp.code()+="if (*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 2978, 2976, 2975, 2973, 2977);\n";{ cp.code()+="etiss_coverage_count(1, 3034);\n";cp.code()+="{ // block\n";etiss_uint32 MMIN=2147483648ULL;cp.code()+="etiss_coverage_count(1, 2986);\n";cp.code()+="etiss_coverage_count(1, 2987);\n";cp.code()+="if (*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] == "+std::to_string(MMIN)+"ULL && (etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) == -1LL) { // conditional\n";cp.code()+="etiss_coverage_count(11, 3005, 2994, 2992, 2991, 2989, 2993, 3004, 3001, 2999, 2998, 2996);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string(MMIN)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 3012, 3010, 3009, 3007, 3011);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) / (etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(13, 3033, 3017, 3016, 3014, 3032, 3024, 3022, 3021, 3019, 3031, 3029, 3028, 3026);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = -1LL;\n";cp.code()+="etiss_coverage_count(4, 3042, 3039, 3038, 3036);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "div"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
mulhsu_rd_rs1_rs2
static InstructionDefinition mulhsu_rd_rs1_rs2(ISA32_RV32IMACFD, "mulhsu",(uint32_t) 0x2002033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MULHSU\n");cp.code()+="etiss_coverage_count(1, 74);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2925);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2887);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2893, 2890, 2888, 2891, 2892);\n";{ cp.code()+="etiss_coverage_count(1, 2924);\n";cp.code()+="{ // block\n";cp.code()+="etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL])) * (etiss_uint64)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(11, 2911, 2910, 2902, 2900, 2899, 2898, 2896, 2909, 2907, 2906, 2904);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint32)((res >> 32ULL));\n";cp.code()+="etiss_coverage_count(8, 2923, 2916, 2915, 2913, 2922, 2919, 2917, 2920);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "mulhsu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
mulhu_rd_rs1_rs2
static InstructionDefinition mulhu_rd_rs1_rs2(ISA32_RV32IMACFD, "mulhu",(uint32_t) 0x2003033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MULHU\n");cp.code()+="etiss_coverage_count(1, 75);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2963);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2926);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2932, 2929, 2927, 2930, 2931);\n";{ cp.code()+="etiss_coverage_count(1, 2962);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = (etiss_uint64)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) * (etiss_uint64)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(10, 2949, 2948, 2940, 2938, 2937, 2935, 2947, 2945, 2944, 2942);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint32)((res >> 32ULL));\n";cp.code()+="etiss_coverage_count(8, 2961, 2954, 2953, 2951, 2960, 2957, 2955, 2958);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "mulhu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
mul_rd_rs1_rs2
static InstructionDefinition mul_rd_rs1_rs2(ISA32_RV32IMACFD, "mul",(uint32_t) 0x2000033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MUL\n");cp.code()+="etiss_coverage_count(1, 72);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2846);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2810);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2816, 2813, 2811, 2814, 2815);\n";{ cp.code()+="etiss_coverage_count(1, 2845);\n";cp.code()+="{ // block\n";cp.code()+="etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL])) * (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]));\n";cp.code()+="etiss_coverage_count(12, 2835, 2834, 2825, 2823, 2822, 2821, 2819, 2833, 2831, 2830, 2829, 2827);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint32)(res);\n";cp.code()+="etiss_coverage_count(6, 2844, 2840, 2839, 2837, 2843, 2841);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "mul"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
remu_rd_rs1_rs2
static InstructionDefinition remu_rd_rs1_rs2(ISA32_RV32IMACFD, "remu",(uint32_t) 0x2007033,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//REMU\n");cp.code()+="etiss_coverage_count(1, 79);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3215);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3171);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3177, 3174, 3172, 3175, 3176);\n";{ cp.code()+="etiss_coverage_count(1, 3214);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3178);\n";cp.code()+="if (*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 3185, 3183, 3182, 3180, 3184);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] % *((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 3202, 3190, 3189, 3187, 3201, 3195, 3194, 3192, 3200, 3199, 3197);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(7, 3213, 3207, 3206, 3204, 3212, 3211, 3209);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "remu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
uint32_t
static __inline__ uint32_t
Definition: arm_cde.h:25
etiss_uint32
uint32_t etiss_uint32
Definition: types.h:93
etiss_uint8
uint8_t etiss_uint8
Definition: types.h:87
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:386
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition: Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition: Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
Generated on Thu Oct 24 2024 09:40:11 for ETISS 0.8.0 by doxygen 1.9.1