ETISS 0.11.2
ExtendableTranslatingInstructionSetSimulator(version0.11.2)
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RV32IMACFD_RV32MInstr.cpp
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1// clang-format off
9#include "RV32IMACFDArch.h"
10#include "RV32IMACFDFuncs.h"
11
12using namespace etiss;
13using namespace etiss::instr;
14
15// MUL -------------------------------------------------------------------------
16static InstructionDefinition mul_rd_rs1_rs2 (
17 ISA32_RV32IMACFD,
18 "mul",
19 (uint64_t) 0x2000033,
20 (uint64_t) 0xfe00707f,
21 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22 {
23
24// -----------------------------------------------------------------------------
25
26// -----------------------------------------------------------------------------
27
28// -----------------------------------------------------------------------------
29// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
30etiss_uint8 rd = 0;
31static BitArrayRange R_rd_0(11, 7);
32rd += R_rd_0.read(ba) << 0;
33etiss_uint8 rs1 = 0;
34static BitArrayRange R_rs1_0(19, 15);
35rs1 += R_rs1_0.read(ba) << 0;
36etiss_uint8 rs2 = 0;
37static BitArrayRange R_rs2_0(24, 20);
38rs2 += R_rs2_0.read(ba) << 0;
39
40// NOLINTEND(clang-diagnostic-unused-but-set-variable)
41// -----------------------------------------------------------------------------
42
43 {
44 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
45
46 cp.code() = std::string("//MUL\n");
47
48// -----------------------------------------------------------------------------
49cp.code() += "etiss_coverage_count(1, 72);\n";
50{ // block
51cp.code() += "etiss_coverage_count(1, 1189);\n";
52cp.code() += "{ // block\n";
53cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
54cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
55cp.code() += "} // block\n";
56} // block
57{ // block
58cp.code() += "etiss_coverage_count(1, 2786);\n";
59cp.code() += "{ // block\n";
60cp.code() += "etiss_coverage_count(1, 2750);\n";
61if ((rd % 32ULL) != 0LL) { // conditional
62cp.code() += "etiss_coverage_count(5, 2756, 2753, 2751, 2754, 2755);\n";
63{ // block
64cp.code() += "etiss_coverage_count(1, 2785);\n";
65cp.code() += "{ // block\n";
66cp.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) * (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]));\n";
67cp.code() += "etiss_coverage_count(12, 2775, 2774, 2765, 2763, 2762, 2761, 2759, 2773, 2771, 2770, 2769, 2767);\n";
68cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)(res);\n";
69cp.code() += "etiss_coverage_count(6, 2784, 2780, 2779, 2777, 2783, 2781);\n";
70cp.code() += "} // block\n";
71} // block
72} // conditional
73cp.code() += "} // block\n";
74} // block
75cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
76cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
77// -----------------------------------------------------------------------------
78 cp.getAffectedRegisters().add("instructionPointer", 32);
79 }
80
81 return true;
82 },
83 0,
84 [] (BitArray & ba, Instruction & instr)
85 {
86// -----------------------------------------------------------------------------
87etiss_uint8 rd = 0;
88static BitArrayRange R_rd_0(11, 7);
89rd += R_rd_0.read(ba) << 0;
90etiss_uint8 rs1 = 0;
91static BitArrayRange R_rs1_0(19, 15);
92rs1 += R_rs1_0.read(ba) << 0;
93etiss_uint8 rs2 = 0;
94static BitArrayRange R_rs2_0(24, 20);
95rs2 += R_rs2_0.read(ba) << 0;
96
97// -----------------------------------------------------------------------------
98
99 std::stringstream ss;
100// -----------------------------------------------------------------------------
101ss << "mul" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
102// -----------------------------------------------------------------------------
103 return ss.str();
104 }
105);
106
107// MULH ------------------------------------------------------------------------
108static InstructionDefinition mulh_rd_rs1_rs2 (
109 ISA32_RV32IMACFD,
110 "mulh",
111 (uint64_t) 0x2001033,
112 (uint64_t) 0xfe00707f,
113 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
114 {
115
116// -----------------------------------------------------------------------------
117
118// -----------------------------------------------------------------------------
119
120// -----------------------------------------------------------------------------
121// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
122etiss_uint8 rd = 0;
123static BitArrayRange R_rd_0(11, 7);
124rd += R_rd_0.read(ba) << 0;
125etiss_uint8 rs1 = 0;
126static BitArrayRange R_rs1_0(19, 15);
127rs1 += R_rs1_0.read(ba) << 0;
128etiss_uint8 rs2 = 0;
129static BitArrayRange R_rs2_0(24, 20);
130rs2 += R_rs2_0.read(ba) << 0;
131
132// NOLINTEND(clang-diagnostic-unused-but-set-variable)
133// -----------------------------------------------------------------------------
134
135 {
136 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
137
138 cp.code() = std::string("//MULH\n");
139
140// -----------------------------------------------------------------------------
141cp.code() += "etiss_coverage_count(1, 73);\n";
142{ // block
143cp.code() += "etiss_coverage_count(1, 1189);\n";
144cp.code() += "{ // block\n";
145cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
146cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
147cp.code() += "} // block\n";
148} // block
149{ // block
150cp.code() += "etiss_coverage_count(1, 2826);\n";
151cp.code() += "{ // block\n";
152cp.code() += "etiss_coverage_count(1, 2787);\n";
153if ((rd % 32ULL) != 0LL) { // conditional
154cp.code() += "etiss_coverage_count(5, 2793, 2790, 2788, 2791, 2792);\n";
155{ // block
156cp.code() += "etiss_coverage_count(1, 2825);\n";
157cp.code() += "{ // block\n";
158cp.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) * (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]));\n";
159cp.code() += "etiss_coverage_count(12, 2812, 2811, 2802, 2800, 2799, 2798, 2796, 2810, 2808, 2807, 2806, 2804);\n";
160cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)((res >> 32ULL));\n";
161cp.code() += "etiss_coverage_count(8, 2824, 2817, 2816, 2814, 2823, 2820, 2818, 2821);\n";
162cp.code() += "} // block\n";
163} // block
164} // conditional
165cp.code() += "} // block\n";
166} // block
167cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
168cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
169// -----------------------------------------------------------------------------
170 cp.getAffectedRegisters().add("instructionPointer", 32);
171 }
172
173 return true;
174 },
175 0,
176 [] (BitArray & ba, Instruction & instr)
177 {
178// -----------------------------------------------------------------------------
179etiss_uint8 rd = 0;
180static BitArrayRange R_rd_0(11, 7);
181rd += R_rd_0.read(ba) << 0;
182etiss_uint8 rs1 = 0;
183static BitArrayRange R_rs1_0(19, 15);
184rs1 += R_rs1_0.read(ba) << 0;
185etiss_uint8 rs2 = 0;
186static BitArrayRange R_rs2_0(24, 20);
187rs2 += R_rs2_0.read(ba) << 0;
188
189// -----------------------------------------------------------------------------
190
191 std::stringstream ss;
192// -----------------------------------------------------------------------------
193ss << "mulh" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
194// -----------------------------------------------------------------------------
195 return ss.str();
196 }
197);
198
199// MULHSU ----------------------------------------------------------------------
200static InstructionDefinition mulhsu_rd_rs1_rs2 (
201 ISA32_RV32IMACFD,
202 "mulhsu",
203 (uint64_t) 0x2002033,
204 (uint64_t) 0xfe00707f,
205 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
206 {
207
208// -----------------------------------------------------------------------------
209
210// -----------------------------------------------------------------------------
211
212// -----------------------------------------------------------------------------
213// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
214etiss_uint8 rd = 0;
215static BitArrayRange R_rd_0(11, 7);
216rd += R_rd_0.read(ba) << 0;
217etiss_uint8 rs1 = 0;
218static BitArrayRange R_rs1_0(19, 15);
219rs1 += R_rs1_0.read(ba) << 0;
220etiss_uint8 rs2 = 0;
221static BitArrayRange R_rs2_0(24, 20);
222rs2 += R_rs2_0.read(ba) << 0;
223
224// NOLINTEND(clang-diagnostic-unused-but-set-variable)
225// -----------------------------------------------------------------------------
226
227 {
228 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
229
230 cp.code() = std::string("//MULHSU\n");
231
232// -----------------------------------------------------------------------------
233cp.code() += "etiss_coverage_count(1, 74);\n";
234{ // block
235cp.code() += "etiss_coverage_count(1, 1189);\n";
236cp.code() += "{ // block\n";
237cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
238cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
239cp.code() += "} // block\n";
240} // block
241{ // block
242cp.code() += "etiss_coverage_count(1, 2865);\n";
243cp.code() += "{ // block\n";
244cp.code() += "etiss_coverage_count(1, 2827);\n";
245if ((rd % 32ULL) != 0LL) { // conditional
246cp.code() += "etiss_coverage_count(5, 2833, 2830, 2828, 2831, 2832);\n";
247{ // block
248cp.code() += "etiss_coverage_count(1, 2864);\n";
249cp.code() += "{ // block\n";
250cp.code() += "etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL])) * (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
251cp.code() += "etiss_coverage_count(11, 2851, 2850, 2842, 2840, 2839, 2838, 2836, 2849, 2847, 2846, 2844);\n";
252cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)((res >> 32ULL));\n";
253cp.code() += "etiss_coverage_count(8, 2863, 2856, 2855, 2853, 2862, 2859, 2857, 2860);\n";
254cp.code() += "} // block\n";
255} // block
256} // conditional
257cp.code() += "} // block\n";
258} // block
259cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
260cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
261// -----------------------------------------------------------------------------
262 cp.getAffectedRegisters().add("instructionPointer", 32);
263 }
264
265 return true;
266 },
267 0,
268 [] (BitArray & ba, Instruction & instr)
269 {
270// -----------------------------------------------------------------------------
271etiss_uint8 rd = 0;
272static BitArrayRange R_rd_0(11, 7);
273rd += R_rd_0.read(ba) << 0;
274etiss_uint8 rs1 = 0;
275static BitArrayRange R_rs1_0(19, 15);
276rs1 += R_rs1_0.read(ba) << 0;
277etiss_uint8 rs2 = 0;
278static BitArrayRange R_rs2_0(24, 20);
279rs2 += R_rs2_0.read(ba) << 0;
280
281// -----------------------------------------------------------------------------
282
283 std::stringstream ss;
284// -----------------------------------------------------------------------------
285ss << "mulhsu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
286// -----------------------------------------------------------------------------
287 return ss.str();
288 }
289);
290
291// MULHU -----------------------------------------------------------------------
292static InstructionDefinition mulhu_rd_rs1_rs2 (
293 ISA32_RV32IMACFD,
294 "mulhu",
295 (uint64_t) 0x2003033,
296 (uint64_t) 0xfe00707f,
297 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
298 {
299
300// -----------------------------------------------------------------------------
301
302// -----------------------------------------------------------------------------
303
304// -----------------------------------------------------------------------------
305// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
306etiss_uint8 rd = 0;
307static BitArrayRange R_rd_0(11, 7);
308rd += R_rd_0.read(ba) << 0;
309etiss_uint8 rs1 = 0;
310static BitArrayRange R_rs1_0(19, 15);
311rs1 += R_rs1_0.read(ba) << 0;
312etiss_uint8 rs2 = 0;
313static BitArrayRange R_rs2_0(24, 20);
314rs2 += R_rs2_0.read(ba) << 0;
315
316// NOLINTEND(clang-diagnostic-unused-but-set-variable)
317// -----------------------------------------------------------------------------
318
319 {
320 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
321
322 cp.code() = std::string("//MULHU\n");
323
324// -----------------------------------------------------------------------------
325cp.code() += "etiss_coverage_count(1, 75);\n";
326{ // block
327cp.code() += "etiss_coverage_count(1, 1189);\n";
328cp.code() += "{ // block\n";
329cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
330cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
331cp.code() += "} // block\n";
332} // block
333{ // block
334cp.code() += "etiss_coverage_count(1, 2903);\n";
335cp.code() += "{ // block\n";
336cp.code() += "etiss_coverage_count(1, 2866);\n";
337if ((rd % 32ULL) != 0LL) { // conditional
338cp.code() += "etiss_coverage_count(5, 2872, 2869, 2867, 2870, 2871);\n";
339{ // block
340cp.code() += "etiss_coverage_count(1, 2902);\n";
341cp.code() += "{ // block\n";
342cp.code() += "etiss_uint64 res = (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) * (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
343cp.code() += "etiss_coverage_count(10, 2889, 2888, 2880, 2878, 2877, 2875, 2887, 2885, 2884, 2882);\n";
344cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)((res >> 32ULL));\n";
345cp.code() += "etiss_coverage_count(8, 2901, 2894, 2893, 2891, 2900, 2897, 2895, 2898);\n";
346cp.code() += "} // block\n";
347} // block
348} // conditional
349cp.code() += "} // block\n";
350} // block
351cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
352cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
353// -----------------------------------------------------------------------------
354 cp.getAffectedRegisters().add("instructionPointer", 32);
355 }
356
357 return true;
358 },
359 0,
360 [] (BitArray & ba, Instruction & instr)
361 {
362// -----------------------------------------------------------------------------
363etiss_uint8 rd = 0;
364static BitArrayRange R_rd_0(11, 7);
365rd += R_rd_0.read(ba) << 0;
366etiss_uint8 rs1 = 0;
367static BitArrayRange R_rs1_0(19, 15);
368rs1 += R_rs1_0.read(ba) << 0;
369etiss_uint8 rs2 = 0;
370static BitArrayRange R_rs2_0(24, 20);
371rs2 += R_rs2_0.read(ba) << 0;
372
373// -----------------------------------------------------------------------------
374
375 std::stringstream ss;
376// -----------------------------------------------------------------------------
377ss << "mulhu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
378// -----------------------------------------------------------------------------
379 return ss.str();
380 }
381);
382
383// DIV -------------------------------------------------------------------------
384static InstructionDefinition div_rd_rs1_rs2 (
385 ISA32_RV32IMACFD,
386 "div",
387 (uint64_t) 0x2004033,
388 (uint64_t) 0xfe00707f,
389 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
390 {
391
392// -----------------------------------------------------------------------------
393
394// -----------------------------------------------------------------------------
395
396// -----------------------------------------------------------------------------
397// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
398etiss_uint8 rd = 0;
399static BitArrayRange R_rd_0(11, 7);
400rd += R_rd_0.read(ba) << 0;
401etiss_uint8 rs1 = 0;
402static BitArrayRange R_rs1_0(19, 15);
403rs1 += R_rs1_0.read(ba) << 0;
404etiss_uint8 rs2 = 0;
405static BitArrayRange R_rs2_0(24, 20);
406rs2 += R_rs2_0.read(ba) << 0;
407
408// NOLINTEND(clang-diagnostic-unused-but-set-variable)
409// -----------------------------------------------------------------------------
410
411 {
412 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
413
414 cp.code() = std::string("//DIV\n");
415
416// -----------------------------------------------------------------------------
417cp.code() += "etiss_coverage_count(1, 76);\n";
418{ // block
419cp.code() += "etiss_coverage_count(1, 1189);\n";
420cp.code() += "{ // block\n";
421cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
422cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
423cp.code() += "} // block\n";
424} // block
425{ // block
426cp.code() += "etiss_coverage_count(1, 2984);\n";
427cp.code() += "{ // block\n";
428cp.code() += "etiss_coverage_count(1, 2904);\n";
429if ((rd % 32ULL) != 0LL) { // conditional
430cp.code() += "etiss_coverage_count(5, 2910, 2907, 2905, 2908, 2909);\n";
431{ // block
432cp.code() += "etiss_coverage_count(1, 2983);\n";
433cp.code() += "{ // block\n";
434cp.code() += "etiss_coverage_count(1, 2911);\n";
435cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0LL) { // conditional\n";
436cp.code() += "etiss_coverage_count(5, 2918, 2916, 2915, 2913, 2917);\n";
437{ // block
438cp.code() += "etiss_coverage_count(1, 2974);\n";
439cp.code() += "{ // block\n";
440etiss_uint32 MMIN = 2147483648ULL;
441cp.code() += "etiss_coverage_count(1, 2926);\n";
442cp.code() += "etiss_coverage_count(1, 2927);\n";
443cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] == " + std::to_string(MMIN) + "ULL && (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) == -1LL) { // conditional\n";
444cp.code() += "etiss_coverage_count(11, 2945, 2934, 2932, 2931, 2929, 2933, 2944, 2941, 2939, 2938, 2936);\n";
445cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(MMIN) + "ULL;\n";
446cp.code() += "etiss_coverage_count(5, 2952, 2950, 2949, 2947, 2951);\n";
447cp.code() += "} // conditional\n";
448cp.code() += "else { // conditional\n";
449cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) / (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
450cp.code() += "etiss_coverage_count(13, 2973, 2957, 2956, 2954, 2972, 2964, 2962, 2961, 2959, 2971, 2969, 2968, 2966);\n";
451cp.code() += "} // conditional\n";
452cp.code() += "} // block\n";
453} // block
454cp.code() += "} // conditional\n";
455cp.code() += "else { // conditional\n";
456cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -1LL;\n";
457cp.code() += "etiss_coverage_count(4, 2982, 2979, 2978, 2976);\n";
458cp.code() += "} // conditional\n";
459cp.code() += "} // block\n";
460} // block
461} // conditional
462cp.code() += "} // block\n";
463} // block
464cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
465cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
466// -----------------------------------------------------------------------------
467 cp.getAffectedRegisters().add("instructionPointer", 32);
468 }
469
470 return true;
471 },
472 0,
473 [] (BitArray & ba, Instruction & instr)
474 {
475// -----------------------------------------------------------------------------
476etiss_uint8 rd = 0;
477static BitArrayRange R_rd_0(11, 7);
478rd += R_rd_0.read(ba) << 0;
479etiss_uint8 rs1 = 0;
480static BitArrayRange R_rs1_0(19, 15);
481rs1 += R_rs1_0.read(ba) << 0;
482etiss_uint8 rs2 = 0;
483static BitArrayRange R_rs2_0(24, 20);
484rs2 += R_rs2_0.read(ba) << 0;
485
486// -----------------------------------------------------------------------------
487
488 std::stringstream ss;
489// -----------------------------------------------------------------------------
490ss << "div" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
491// -----------------------------------------------------------------------------
492 return ss.str();
493 }
494);
495
496// DIVU ------------------------------------------------------------------------
497static InstructionDefinition divu_rd_rs1_rs2 (
498 ISA32_RV32IMACFD,
499 "divu",
500 (uint64_t) 0x2005033,
501 (uint64_t) 0xfe00707f,
502 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
503 {
504
505// -----------------------------------------------------------------------------
506
507// -----------------------------------------------------------------------------
508
509// -----------------------------------------------------------------------------
510// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
511etiss_uint8 rd = 0;
512static BitArrayRange R_rd_0(11, 7);
513rd += R_rd_0.read(ba) << 0;
514etiss_uint8 rs1 = 0;
515static BitArrayRange R_rs1_0(19, 15);
516rs1 += R_rs1_0.read(ba) << 0;
517etiss_uint8 rs2 = 0;
518static BitArrayRange R_rs2_0(24, 20);
519rs2 += R_rs2_0.read(ba) << 0;
520
521// NOLINTEND(clang-diagnostic-unused-but-set-variable)
522// -----------------------------------------------------------------------------
523
524 {
525 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
526
527 cp.code() = std::string("//DIVU\n");
528
529// -----------------------------------------------------------------------------
530cp.code() += "etiss_coverage_count(1, 77);\n";
531{ // block
532cp.code() += "etiss_coverage_count(1, 1189);\n";
533cp.code() += "{ // block\n";
534cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
535cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
536cp.code() += "} // block\n";
537} // block
538{ // block
539cp.code() += "etiss_coverage_count(1, 3026);\n";
540cp.code() += "{ // block\n";
541cp.code() += "etiss_coverage_count(1, 2985);\n";
542if ((rd % 32ULL) != 0LL) { // conditional
543cp.code() += "etiss_coverage_count(5, 2991, 2988, 2986, 2989, 2990);\n";
544{ // block
545cp.code() += "etiss_coverage_count(1, 3025);\n";
546cp.code() += "{ // block\n";
547cp.code() += "etiss_coverage_count(1, 2992);\n";
548cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0LL) { // conditional\n";
549cp.code() += "etiss_coverage_count(5, 2999, 2997, 2996, 2994, 2998);\n";
550cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] / *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
551cp.code() += "etiss_coverage_count(11, 3016, 3004, 3003, 3001, 3015, 3009, 3008, 3006, 3014, 3013, 3011);\n";
552cp.code() += "} // conditional\n";
553cp.code() += "else { // conditional\n";
554cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = -1LL;\n";
555cp.code() += "etiss_coverage_count(4, 3024, 3021, 3020, 3018);\n";
556cp.code() += "} // conditional\n";
557cp.code() += "} // block\n";
558} // block
559} // conditional
560cp.code() += "} // block\n";
561} // block
562cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
563cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
564// -----------------------------------------------------------------------------
565 cp.getAffectedRegisters().add("instructionPointer", 32);
566 }
567
568 return true;
569 },
570 0,
571 [] (BitArray & ba, Instruction & instr)
572 {
573// -----------------------------------------------------------------------------
574etiss_uint8 rd = 0;
575static BitArrayRange R_rd_0(11, 7);
576rd += R_rd_0.read(ba) << 0;
577etiss_uint8 rs1 = 0;
578static BitArrayRange R_rs1_0(19, 15);
579rs1 += R_rs1_0.read(ba) << 0;
580etiss_uint8 rs2 = 0;
581static BitArrayRange R_rs2_0(24, 20);
582rs2 += R_rs2_0.read(ba) << 0;
583
584// -----------------------------------------------------------------------------
585
586 std::stringstream ss;
587// -----------------------------------------------------------------------------
588ss << "divu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
589// -----------------------------------------------------------------------------
590 return ss.str();
591 }
592);
593
594// REM -------------------------------------------------------------------------
595static InstructionDefinition rem_rd_rs1_rs2 (
596 ISA32_RV32IMACFD,
597 "rem",
598 (uint64_t) 0x2006033,
599 (uint64_t) 0xfe00707f,
600 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
601 {
602
603// -----------------------------------------------------------------------------
604
605// -----------------------------------------------------------------------------
606
607// -----------------------------------------------------------------------------
608// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
609etiss_uint8 rd = 0;
610static BitArrayRange R_rd_0(11, 7);
611rd += R_rd_0.read(ba) << 0;
612etiss_uint8 rs1 = 0;
613static BitArrayRange R_rs1_0(19, 15);
614rs1 += R_rs1_0.read(ba) << 0;
615etiss_uint8 rs2 = 0;
616static BitArrayRange R_rs2_0(24, 20);
617rs2 += R_rs2_0.read(ba) << 0;
618
619// NOLINTEND(clang-diagnostic-unused-but-set-variable)
620// -----------------------------------------------------------------------------
621
622 {
623 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
624
625 cp.code() = std::string("//REM\n");
626
627// -----------------------------------------------------------------------------
628cp.code() += "etiss_coverage_count(1, 78);\n";
629{ // block
630cp.code() += "etiss_coverage_count(1, 1189);\n";
631cp.code() += "{ // block\n";
632cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
633cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
634cp.code() += "} // block\n";
635} // block
636{ // block
637cp.code() += "etiss_coverage_count(1, 3110);\n";
638cp.code() += "{ // block\n";
639cp.code() += "etiss_coverage_count(1, 3027);\n";
640if ((rd % 32ULL) != 0LL) { // conditional
641cp.code() += "etiss_coverage_count(5, 3033, 3030, 3028, 3031, 3032);\n";
642{ // block
643cp.code() += "etiss_coverage_count(1, 3109);\n";
644cp.code() += "{ // block\n";
645cp.code() += "etiss_coverage_count(1, 3034);\n";
646cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0LL) { // conditional\n";
647cp.code() += "etiss_coverage_count(5, 3041, 3039, 3038, 3036, 3040);\n";
648{ // block
649cp.code() += "etiss_coverage_count(1, 3097);\n";
650cp.code() += "{ // block\n";
651etiss_uint32 MMIN = 2147483648ULL;
652cp.code() += "etiss_coverage_count(1, 3049);\n";
653cp.code() += "etiss_coverage_count(1, 3050);\n";
654cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] == " + std::to_string(MMIN) + "ULL && (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]) == -1LL) { // conditional\n";
655cp.code() += "etiss_coverage_count(11, 3068, 3057, 3055, 3054, 3052, 3056, 3067, 3064, 3062, 3061, 3059);\n";
656cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = 0LL;\n";
657cp.code() += "etiss_coverage_count(5, 3075, 3073, 3072, 3070, 3074);\n";
658cp.code() += "} // conditional\n";
659cp.code() += "else { // conditional\n";
660cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]) % (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
661cp.code() += "etiss_coverage_count(13, 3096, 3080, 3079, 3077, 3095, 3087, 3085, 3084, 3082, 3094, 3092, 3091, 3089);\n";
662cp.code() += "} // conditional\n";
663cp.code() += "} // block\n";
664} // block
665cp.code() += "} // conditional\n";
666cp.code() += "else { // conditional\n";
667cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
668cp.code() += "etiss_coverage_count(7, 3108, 3102, 3101, 3099, 3107, 3106, 3104);\n";
669cp.code() += "} // conditional\n";
670cp.code() += "} // block\n";
671} // block
672} // conditional
673cp.code() += "} // block\n";
674} // block
675cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
676cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
677// -----------------------------------------------------------------------------
678 cp.getAffectedRegisters().add("instructionPointer", 32);
679 }
680
681 return true;
682 },
683 0,
684 [] (BitArray & ba, Instruction & instr)
685 {
686// -----------------------------------------------------------------------------
687etiss_uint8 rd = 0;
688static BitArrayRange R_rd_0(11, 7);
689rd += R_rd_0.read(ba) << 0;
690etiss_uint8 rs1 = 0;
691static BitArrayRange R_rs1_0(19, 15);
692rs1 += R_rs1_0.read(ba) << 0;
693etiss_uint8 rs2 = 0;
694static BitArrayRange R_rs2_0(24, 20);
695rs2 += R_rs2_0.read(ba) << 0;
696
697// -----------------------------------------------------------------------------
698
699 std::stringstream ss;
700// -----------------------------------------------------------------------------
701ss << "rem" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
702// -----------------------------------------------------------------------------
703 return ss.str();
704 }
705);
706
707// REMU ------------------------------------------------------------------------
708static InstructionDefinition remu_rd_rs1_rs2 (
709 ISA32_RV32IMACFD,
710 "remu",
711 (uint64_t) 0x2007033,
712 (uint64_t) 0xfe00707f,
713 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
714 {
715
716// -----------------------------------------------------------------------------
717
718// -----------------------------------------------------------------------------
719
720// -----------------------------------------------------------------------------
721// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
722etiss_uint8 rd = 0;
723static BitArrayRange R_rd_0(11, 7);
724rd += R_rd_0.read(ba) << 0;
725etiss_uint8 rs1 = 0;
726static BitArrayRange R_rs1_0(19, 15);
727rs1 += R_rs1_0.read(ba) << 0;
728etiss_uint8 rs2 = 0;
729static BitArrayRange R_rs2_0(24, 20);
730rs2 += R_rs2_0.read(ba) << 0;
731
732// NOLINTEND(clang-diagnostic-unused-but-set-variable)
733// -----------------------------------------------------------------------------
734
735 {
736 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
737
738 cp.code() = std::string("//REMU\n");
739
740// -----------------------------------------------------------------------------
741cp.code() += "etiss_coverage_count(1, 79);\n";
742{ // block
743cp.code() += "etiss_coverage_count(1, 1189);\n";
744cp.code() += "{ // block\n";
745cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
746cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
747cp.code() += "} // block\n";
748} // block
749{ // block
750cp.code() += "etiss_coverage_count(1, 3155);\n";
751cp.code() += "{ // block\n";
752cp.code() += "etiss_coverage_count(1, 3111);\n";
753if ((rd % 32ULL) != 0LL) { // conditional
754cp.code() += "etiss_coverage_count(5, 3117, 3114, 3112, 3115, 3116);\n";
755{ // block
756cp.code() += "etiss_coverage_count(1, 3154);\n";
757cp.code() += "{ // block\n";
758cp.code() += "etiss_coverage_count(1, 3118);\n";
759cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL] != 0LL) { // conditional\n";
760cp.code() += "etiss_coverage_count(5, 3125, 3123, 3122, 3120, 3124);\n";
761cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] % *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
762cp.code() += "etiss_coverage_count(11, 3142, 3130, 3129, 3127, 3141, 3135, 3134, 3132, 3140, 3139, 3137);\n";
763cp.code() += "} // conditional\n";
764cp.code() += "else { // conditional\n";
765cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
766cp.code() += "etiss_coverage_count(7, 3153, 3147, 3146, 3144, 3152, 3151, 3149);\n";
767cp.code() += "} // conditional\n";
768cp.code() += "} // block\n";
769} // block
770} // conditional
771cp.code() += "} // block\n";
772} // block
773cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
774cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
775// -----------------------------------------------------------------------------
776 cp.getAffectedRegisters().add("instructionPointer", 32);
777 }
778
779 return true;
780 },
781 0,
782 [] (BitArray & ba, Instruction & instr)
783 {
784// -----------------------------------------------------------------------------
785etiss_uint8 rd = 0;
786static BitArrayRange R_rd_0(11, 7);
787rd += R_rd_0.read(ba) << 0;
788etiss_uint8 rs1 = 0;
789static BitArrayRange R_rs1_0(19, 15);
790rs1 += R_rs1_0.read(ba) << 0;
791etiss_uint8 rs2 = 0;
792static BitArrayRange R_rs2_0(24, 20);
793rs2 += R_rs2_0.read(ba) << 0;
794
795// -----------------------------------------------------------------------------
796
797 std::stringstream ss;
798// -----------------------------------------------------------------------------
799ss << "remu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
800// -----------------------------------------------------------------------------
801 return ss.str();
802 }
803);
804// clang-format on
ISA32_RV32IMACFD
etiss::instr::InstructionGroup ISA32_RV32IMACFD("ISA32_RV32IMACFD", 32)
div_rd_rs1_rs2
static InstructionDefinition div_rd_rs1_rs2(ISA32_RV32IMACFD, "div",(uint64_t) 0x2004033,(uint64_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//DIV\n");cp.code()+="etiss_coverage_count(1, 76);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2984);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2904);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2910, 2907, 2905, 2908, 2909);\n";{ cp.code()+="etiss_coverage_count(1, 2983);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2911);\n";cp.code()+="if (*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 2918, 2916, 2915, 2913, 2917);\n";{ cp.code()+="etiss_coverage_count(1, 2974);\n";cp.code()+="{ // block\n";etiss_uint32 MMIN=2147483648ULL;cp.code()+="etiss_coverage_count(1, 2926);\n";cp.code()+="etiss_coverage_count(1, 2927);\n";cp.code()+="if (*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] == "+std::to_string(MMIN)+"ULL && (etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) == -1LL) { // conditional\n";cp.code()+="etiss_coverage_count(11, 2945, 2934, 2932, 2931, 2929, 2933, 2944, 2941, 2939, 2938, 2936);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string(MMIN)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 2952, 2950, 2949, 2947, 2951);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) / (etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(13, 2973, 2957, 2956, 2954, 2972, 2964, 2962, 2961, 2959, 2971, 2969, 2968, 2966);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = -1LL;\n";cp.code()+="etiss_coverage_count(4, 2982, 2979, 2978, 2976);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "div"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
mulhu_rd_rs1_rs2
static InstructionDefinition mulhu_rd_rs1_rs2(ISA32_RV32IMACFD, "mulhu",(uint64_t) 0x2003033,(uint64_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MULHU\n");cp.code()+="etiss_coverage_count(1, 75);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2903);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2866);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2872, 2869, 2867, 2870, 2871);\n";{ cp.code()+="etiss_coverage_count(1, 2902);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint64 res = (etiss_uint64)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) * (etiss_uint64)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(10, 2889, 2888, 2880, 2878, 2877, 2875, 2887, 2885, 2884, 2882);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint32)((res >> 32ULL));\n";cp.code()+="etiss_coverage_count(8, 2901, 2894, 2893, 2891, 2900, 2897, 2895, 2898);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "mulhu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
remu_rd_rs1_rs2
static InstructionDefinition remu_rd_rs1_rs2(ISA32_RV32IMACFD, "remu",(uint64_t) 0x2007033,(uint64_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//REMU\n");cp.code()+="etiss_coverage_count(1, 79);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3155);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3111);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3117, 3114, 3112, 3115, 3116);\n";{ cp.code()+="etiss_coverage_count(1, 3154);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3118);\n";cp.code()+="if (*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 3125, 3123, 3122, 3120, 3124);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] % *((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 3142, 3130, 3129, 3127, 3141, 3135, 3134, 3132, 3140, 3139, 3137);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(7, 3153, 3147, 3146, 3144, 3152, 3151, 3149);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "remu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
rem_rd_rs1_rs2
static InstructionDefinition rem_rd_rs1_rs2(ISA32_RV32IMACFD, "rem",(uint64_t) 0x2006033,(uint64_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//REM\n");cp.code()+="etiss_coverage_count(1, 78);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3110);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3027);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 3033, 3030, 3028, 3031, 3032);\n";{ cp.code()+="etiss_coverage_count(1, 3109);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 3034);\n";cp.code()+="if (*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 3041, 3039, 3038, 3036, 3040);\n";{ cp.code()+="etiss_coverage_count(1, 3097);\n";cp.code()+="{ // block\n";etiss_uint32 MMIN=2147483648ULL;cp.code()+="etiss_coverage_count(1, 3049);\n";cp.code()+="etiss_coverage_count(1, 3050);\n";cp.code()+="if (*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] == "+std::to_string(MMIN)+"ULL && (etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]) == -1LL) { // conditional\n";cp.code()+="etiss_coverage_count(11, 3068, 3057, 3055, 3054, 3052, 3056, 3067, 3064, 3062, 3061, 3059);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = 0LL;\n";cp.code()+="etiss_coverage_count(5, 3075, 3073, 3072, 3070, 3074);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]) % (etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(13, 3096, 3080, 3079, 3077, 3095, 3087, 3085, 3084, 3082, 3094, 3092, 3091, 3089);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(7, 3108, 3102, 3101, 3099, 3107, 3106, 3104);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "rem"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
mulhsu_rd_rs1_rs2
static InstructionDefinition mulhsu_rd_rs1_rs2(ISA32_RV32IMACFD, "mulhsu",(uint64_t) 0x2002033,(uint64_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MULHSU\n");cp.code()+="etiss_coverage_count(1, 74);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2865);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2827);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2833, 2830, 2828, 2831, 2832);\n";{ cp.code()+="etiss_coverage_count(1, 2864);\n";cp.code()+="{ // block\n";cp.code()+="etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL])) * (etiss_uint64)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(11, 2851, 2850, 2842, 2840, 2839, 2838, 2836, 2849, 2847, 2846, 2844);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint32)((res >> 32ULL));\n";cp.code()+="etiss_coverage_count(8, 2863, 2856, 2855, 2853, 2862, 2859, 2857, 2860);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "mulhsu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
divu_rd_rs1_rs2
static InstructionDefinition divu_rd_rs1_rs2(ISA32_RV32IMACFD, "divu",(uint64_t) 0x2005033,(uint64_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//DIVU\n");cp.code()+="etiss_coverage_count(1, 77);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3026);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2985);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2991, 2988, 2986, 2989, 2990);\n";{ cp.code()+="etiss_coverage_count(1, 3025);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2992);\n";cp.code()+="if (*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(5, 2999, 2997, 2996, 2994, 2998);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] / *((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 3016, 3004, 3003, 3001, 3015, 3009, 3008, 3006, 3014, 3013, 3011);\n";cp.code()+="} // conditional\n";cp.code()+="else { // conditional\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = -1LL;\n";cp.code()+="etiss_coverage_count(4, 3024, 3021, 3020, 3018);\n";cp.code()+="} // conditional\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "divu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
mul_rd_rs1_rs2
static InstructionDefinition mul_rd_rs1_rs2(ISA32_RV32IMACFD, "mul",(uint64_t) 0x2000033,(uint64_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MUL\n");cp.code()+="etiss_coverage_count(1, 72);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2786);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2750);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2756, 2753, 2751, 2754, 2755);\n";{ cp.code()+="etiss_coverage_count(1, 2785);\n";cp.code()+="{ // block\n";cp.code()+="etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL])) * (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]));\n";cp.code()+="etiss_coverage_count(12, 2775, 2774, 2765, 2763, 2762, 2761, 2759, 2773, 2771, 2770, 2769, 2767);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint32)(res);\n";cp.code()+="etiss_coverage_count(6, 2784, 2780, 2779, 2777, 2783, 2781);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "mul"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
mulh_rd_rs1_rs2
static InstructionDefinition mulh_rd_rs1_rs2(ISA32_RV32IMACFD, "mulh",(uint64_t) 0x2001033,(uint64_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//MULH\n");cp.code()+="etiss_coverage_count(1, 73);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2826);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2787);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2793, 2790, 2788, 2791, 2792);\n";{ cp.code()+="etiss_coverage_count(1, 2825);\n";cp.code()+="{ // block\n";cp.code()+="etiss_int64 res = (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL])) * (etiss_int64)((etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]));\n";cp.code()+="etiss_coverage_count(12, 2812, 2811, 2802, 2800, 2799, 2798, 2796, 2810, 2808, 2807, 2806, 2804);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint32)((res >> 32ULL));\n";cp.code()+="etiss_coverage_count(8, 2824, 2817, 2816, 2814, 2823, 2820, 2818, 2821);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "mulh"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
etiss_uint32
uint32_t etiss_uint32
Definition types.h:55
etiss_uint8
uint8_t etiss_uint8
Definition types.h:49
etiss::CodePart
Contains a small code snipped.
Definition CodePart.h:348
etiss::CodePart::code
std::string & code()
Definition CodePart.h:378
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition CodePart.h:376
etiss::CodeSet
A set of CodeParts.
Definition CodePart.h:399
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition CodePart.h:412
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition CodePart.h:184
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition Instruction.h:162
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition Instruction.cpp:171
etiss::instr::BitArray
stores a bit vector
Definition Instruction.h:114
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition Instruction.h:290
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition Instruction.h:319
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition Instruction.h:346
etiss
forwards: include/jit/*
Definition Benchmark.h:17
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