ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV32IMACFD_RV32ICInstr.cpp
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1 
8 #include "RV32IMACFDArch.h"
9 #include "RV32IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // CADDI4SPN -------------------------------------------------------------------
16 static InstructionDefinition caddi4spn_rd_imm (
17  ISA16_RV32IMACFD,
18  "caddi4spn",
19  (uint16_t) 0x00,
20  (uint16_t) 0xe003,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 etiss_uint8 rd = 0;
30 static BitArrayRange R_rd_0(4, 2);
31 rd += R_rd_0.read(ba) << 0;
32 etiss_uint16 imm = 0;
33 static BitArrayRange R_imm_3(5, 5);
34 imm += R_imm_3.read(ba) << 3;
35 static BitArrayRange R_imm_2(6, 6);
36 imm += R_imm_2.read(ba) << 2;
37 static BitArrayRange R_imm_6(10, 7);
38 imm += R_imm_6.read(ba) << 6;
39 static BitArrayRange R_imm_4(12, 11);
40 imm += R_imm_4.read(ba) << 4;
41 
42 // -----------------------------------------------------------------------------
43 
44  {
45  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
46 
47  cp.code() = std::string("//CADDI4SPN\n");
48 
49 // -----------------------------------------------------------------------------
50 { // block
51 cp.code() += "{ // block\n";
52 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
53 cp.code() += "} // block\n";
54 } // block
55 if (imm) { // conditional
56 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(imm) + "ULL;\n";
57 } // conditional
58 else { // conditional
59 { // procedure
60 cp.code() += "{ // procedure\n";
61 cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";
62 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
63 cp.code() += "} // procedure\n";
64 } // procedure
65 } // conditional
66 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
67 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
68 // -----------------------------------------------------------------------------
69  cp.getAffectedRegisters().add("instructionPointer", 32);
70  }
71  {
72  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
73 
74  cp.code() = std::string("//CADDI4SPN\n");
75 
76 // -----------------------------------------------------------------------------
77 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
78 // -----------------------------------------------------------------------------
79  }
80 
81  return true;
82  },
83  0,
84  [] (BitArray & ba, Instruction & instr)
85  {
86 // -----------------------------------------------------------------------------
87 etiss_uint8 rd = 0;
88 static BitArrayRange R_rd_0(4, 2);
89 rd += R_rd_0.read(ba) << 0;
90 etiss_uint16 imm = 0;
91 static BitArrayRange R_imm_3(5, 5);
92 imm += R_imm_3.read(ba) << 3;
93 static BitArrayRange R_imm_2(6, 6);
94 imm += R_imm_2.read(ba) << 2;
95 static BitArrayRange R_imm_6(10, 7);
96 imm += R_imm_6.read(ba) << 6;
97 static BitArrayRange R_imm_4(12, 11);
98 imm += R_imm_4.read(ba) << 4;
99 
100 // -----------------------------------------------------------------------------
101 
102  std::stringstream ss;
103 // -----------------------------------------------------------------------------
104 ss << "caddi4spn" << " # " << ba << (" [rd=" + std::to_string(rd) + " | imm=" + std::to_string(imm) + "]");
105 // -----------------------------------------------------------------------------
106  return ss.str();
107  }
108 );
109 
110 // CLW -------------------------------------------------------------------------
111 static InstructionDefinition clw_rd_uimm_rs1 (
112  ISA16_RV32IMACFD,
113  "clw",
114  (uint16_t) 0x4000,
115  (uint16_t) 0xe003,
116  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
117  {
118 
119 // -----------------------------------------------------------------------------
120 
121 // -----------------------------------------------------------------------------
122 
123 // -----------------------------------------------------------------------------
124 etiss_uint8 rd = 0;
125 static BitArrayRange R_rd_0(4, 2);
126 rd += R_rd_0.read(ba) << 0;
127 etiss_uint8 uimm = 0;
128 static BitArrayRange R_uimm_6(5, 5);
129 uimm += R_uimm_6.read(ba) << 6;
130 static BitArrayRange R_uimm_2(6, 6);
131 uimm += R_uimm_2.read(ba) << 2;
132 etiss_uint8 rs1 = 0;
133 static BitArrayRange R_rs1_0(9, 7);
134 rs1 += R_rs1_0.read(ba) << 0;
135 static BitArrayRange R_uimm_3(12, 10);
136 uimm += R_uimm_3.read(ba) << 3;
137 
138 // -----------------------------------------------------------------------------
139 
140  {
141  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
142 
143  cp.code() = std::string("//CLW\n");
144 
145 // -----------------------------------------------------------------------------
146 { // block
147 cp.code() += "{ // block\n";
148 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
149 cp.code() += "} // block\n";
150 } // block
151 { // block
152 cp.code() += "{ // block\n";
153 cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
154 cp.code() += "etiss_uint32 mem_val_0;\n";
155 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
156 cp.code() += "if (cpu->exception) { // conditional\n";
157 { // procedure
158 cp.code() += "{ // procedure\n";
159 cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
160 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
161 cp.code() += "} // procedure\n";
162 } // procedure
163 cp.code() += "} // conditional\n";
164 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = (etiss_int32)(mem_val_0);\n";
165 cp.code() += "} // block\n";
166 } // block
167 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
168 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
169 // -----------------------------------------------------------------------------
170  cp.getAffectedRegisters().add("instructionPointer", 32);
171  }
172  {
173  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
174 
175  cp.code() = std::string("//CLW\n");
176 
177 // -----------------------------------------------------------------------------
178 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
179 // -----------------------------------------------------------------------------
180  }
181 
182  return true;
183  },
184  0,
185  [] (BitArray & ba, Instruction & instr)
186  {
187 // -----------------------------------------------------------------------------
188 etiss_uint8 rd = 0;
189 static BitArrayRange R_rd_0(4, 2);
190 rd += R_rd_0.read(ba) << 0;
191 etiss_uint8 uimm = 0;
192 static BitArrayRange R_uimm_6(5, 5);
193 uimm += R_uimm_6.read(ba) << 6;
194 static BitArrayRange R_uimm_2(6, 6);
195 uimm += R_uimm_2.read(ba) << 2;
196 etiss_uint8 rs1 = 0;
197 static BitArrayRange R_rs1_0(9, 7);
198 rs1 += R_rs1_0.read(ba) << 0;
199 static BitArrayRange R_uimm_3(12, 10);
200 uimm += R_uimm_3.read(ba) << 3;
201 
202 // -----------------------------------------------------------------------------
203 
204  std::stringstream ss;
205 // -----------------------------------------------------------------------------
206 ss << "clw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | uimm=" + std::to_string(uimm) + " | rs1=" + std::to_string(rs1) + "]");
207 // -----------------------------------------------------------------------------
208  return ss.str();
209  }
210 );
211 
212 // CSW -------------------------------------------------------------------------
213 static InstructionDefinition csw_rs2_uimm_rs1 (
214  ISA16_RV32IMACFD,
215  "csw",
216  (uint16_t) 0xc000,
217  (uint16_t) 0xe003,
218  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
219  {
220 
221 // -----------------------------------------------------------------------------
222 
223 // -----------------------------------------------------------------------------
224 
225 // -----------------------------------------------------------------------------
226 etiss_uint8 rs2 = 0;
227 static BitArrayRange R_rs2_0(4, 2);
228 rs2 += R_rs2_0.read(ba) << 0;
229 etiss_uint8 uimm = 0;
230 static BitArrayRange R_uimm_6(5, 5);
231 uimm += R_uimm_6.read(ba) << 6;
232 static BitArrayRange R_uimm_2(6, 6);
233 uimm += R_uimm_2.read(ba) << 2;
234 etiss_uint8 rs1 = 0;
235 static BitArrayRange R_rs1_0(9, 7);
236 rs1 += R_rs1_0.read(ba) << 0;
237 static BitArrayRange R_uimm_3(12, 10);
238 uimm += R_uimm_3.read(ba) << 3;
239 
240 // -----------------------------------------------------------------------------
241 
242  {
243  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
244 
245  cp.code() = std::string("//CSW\n");
246 
247 // -----------------------------------------------------------------------------
248 { // block
249 cp.code() += "{ // block\n";
250 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
251 cp.code() += "} // block\n";
252 } // block
253 { // block
254 cp.code() += "{ // block\n";
255 cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
256 cp.code() += "etiss_uint32 mem_val_0;\n";
257 cp.code() += "mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL]);\n";
258 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
259 cp.code() += "if (cpu->exception) { // conditional\n";
260 { // procedure
261 cp.code() += "{ // procedure\n";
262 cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
263 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
264 cp.code() += "} // procedure\n";
265 } // procedure
266 cp.code() += "} // conditional\n";
267 cp.code() += "} // block\n";
268 } // block
269 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
270 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
271 // -----------------------------------------------------------------------------
272  cp.getAffectedRegisters().add("instructionPointer", 32);
273  }
274  {
275  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
276 
277  cp.code() = std::string("//CSW\n");
278 
279 // -----------------------------------------------------------------------------
280 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
281 // -----------------------------------------------------------------------------
282  }
283 
284  return true;
285  },
286  0,
287  [] (BitArray & ba, Instruction & instr)
288  {
289 // -----------------------------------------------------------------------------
290 etiss_uint8 rs2 = 0;
291 static BitArrayRange R_rs2_0(4, 2);
292 rs2 += R_rs2_0.read(ba) << 0;
293 etiss_uint8 uimm = 0;
294 static BitArrayRange R_uimm_6(5, 5);
295 uimm += R_uimm_6.read(ba) << 6;
296 static BitArrayRange R_uimm_2(6, 6);
297 uimm += R_uimm_2.read(ba) << 2;
298 etiss_uint8 rs1 = 0;
299 static BitArrayRange R_rs1_0(9, 7);
300 rs1 += R_rs1_0.read(ba) << 0;
301 static BitArrayRange R_uimm_3(12, 10);
302 uimm += R_uimm_3.read(ba) << 3;
303 
304 // -----------------------------------------------------------------------------
305 
306  std::stringstream ss;
307 // -----------------------------------------------------------------------------
308 ss << "csw" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | uimm=" + std::to_string(uimm) + " | rs1=" + std::to_string(rs1) + "]");
309 // -----------------------------------------------------------------------------
310  return ss.str();
311  }
312 );
313 
314 // CADDI -----------------------------------------------------------------------
315 static InstructionDefinition caddi_imm_rs1 (
316  ISA16_RV32IMACFD,
317  "caddi",
318  (uint16_t) 0x01,
319  (uint16_t) 0xe003,
320  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
321  {
322 
323 // -----------------------------------------------------------------------------
324 
325 // -----------------------------------------------------------------------------
326 
327 // -----------------------------------------------------------------------------
328 etiss_uint8 imm = 0;
329 static BitArrayRange R_imm_0(6, 2);
330 imm += R_imm_0.read(ba) << 0;
331 etiss_uint8 rs1 = 0;
332 static BitArrayRange R_rs1_0(11, 7);
333 rs1 += R_rs1_0.read(ba) << 0;
334 static BitArrayRange R_imm_5(12, 12);
335 imm += R_imm_5.read(ba) << 5;
336 
337 // -----------------------------------------------------------------------------
338 
339  {
340  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
341 
342  cp.code() = std::string("//CADDI\n");
343 
344 // -----------------------------------------------------------------------------
345 { // block
346 cp.code() += "{ // block\n";
347 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
348 cp.code() += "} // block\n";
349 } // block
350 if ((rs1 % 32ULL) != 0LL) { // conditional
351 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int8)(((etiss_int8)imm) << (2)) >> (2))) + "LL;\n";
352 } // conditional
353 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
354 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
355 // -----------------------------------------------------------------------------
356  cp.getAffectedRegisters().add("instructionPointer", 32);
357  }
358 
359  return true;
360  },
361  0,
362  [] (BitArray & ba, Instruction & instr)
363  {
364 // -----------------------------------------------------------------------------
365 etiss_uint8 imm = 0;
366 static BitArrayRange R_imm_0(6, 2);
367 imm += R_imm_0.read(ba) << 0;
368 etiss_uint8 rs1 = 0;
369 static BitArrayRange R_rs1_0(11, 7);
370 rs1 += R_rs1_0.read(ba) << 0;
371 static BitArrayRange R_imm_5(12, 12);
372 imm += R_imm_5.read(ba) << 5;
373 
374 // -----------------------------------------------------------------------------
375 
376  std::stringstream ss;
377 // -----------------------------------------------------------------------------
378 ss << "caddi" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + "]");
379 // -----------------------------------------------------------------------------
380  return ss.str();
381  }
382 );
383 
384 // CNOP ------------------------------------------------------------------------
385 static InstructionDefinition cnop_nzimm (
386  ISA16_RV32IMACFD,
387  "cnop",
388  (uint16_t) 0x01,
389  (uint16_t) 0xef83,
390  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
391  {
392 
393 // -----------------------------------------------------------------------------
394 
395 // -----------------------------------------------------------------------------
396 
397 // -----------------------------------------------------------------------------
398 etiss_uint8 nzimm = 0;
399 static BitArrayRange R_nzimm_0(6, 2);
400 nzimm += R_nzimm_0.read(ba) << 0;
401 static BitArrayRange R_nzimm_5(12, 12);
402 nzimm += R_nzimm_5.read(ba) << 5;
403 
404 // -----------------------------------------------------------------------------
405 
406  {
407  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
408 
409  cp.code() = std::string("//CNOP\n");
410 
411 // -----------------------------------------------------------------------------
412 { // block
413 cp.code() += "{ // block\n";
414 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
415 cp.code() += "} // block\n";
416 } // block
417 { // block
418 cp.code() += "{ // block\n";
419 cp.code() += "} // block\n";
420 } // block
421 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
422 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
423 // -----------------------------------------------------------------------------
424  cp.getAffectedRegisters().add("instructionPointer", 32);
425  }
426 
427  return true;
428  },
429  0,
430  [] (BitArray & ba, Instruction & instr)
431  {
432 // -----------------------------------------------------------------------------
433 etiss_uint8 nzimm = 0;
434 static BitArrayRange R_nzimm_0(6, 2);
435 nzimm += R_nzimm_0.read(ba) << 0;
436 static BitArrayRange R_nzimm_5(12, 12);
437 nzimm += R_nzimm_5.read(ba) << 5;
438 
439 // -----------------------------------------------------------------------------
440 
441  std::stringstream ss;
442 // -----------------------------------------------------------------------------
443 ss << "cnop" << " # " << ba << (" [nzimm=" + std::to_string(nzimm) + "]");
444 // -----------------------------------------------------------------------------
445  return ss.str();
446  }
447 );
448 
449 // CJAL ------------------------------------------------------------------------
450 static InstructionDefinition cjal_imm (
451  ISA16_RV32IMACFD,
452  "cjal",
453  (uint16_t) 0x2001,
454  (uint16_t) 0xe003,
455  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
456  {
457 
458 // -----------------------------------------------------------------------------
459 
460 // -----------------------------------------------------------------------------
461 
462 // -----------------------------------------------------------------------------
463 etiss_uint16 imm = 0;
464 static BitArrayRange R_imm_5(2, 2);
465 imm += R_imm_5.read(ba) << 5;
466 static BitArrayRange R_imm_1(5, 3);
467 imm += R_imm_1.read(ba) << 1;
468 static BitArrayRange R_imm_7(6, 6);
469 imm += R_imm_7.read(ba) << 7;
470 static BitArrayRange R_imm_6(7, 7);
471 imm += R_imm_6.read(ba) << 6;
472 static BitArrayRange R_imm_10(8, 8);
473 imm += R_imm_10.read(ba) << 10;
474 static BitArrayRange R_imm_8(10, 9);
475 imm += R_imm_8.read(ba) << 8;
476 static BitArrayRange R_imm_4(11, 11);
477 imm += R_imm_4.read(ba) << 4;
478 static BitArrayRange R_imm_11(12, 12);
479 imm += R_imm_11.read(ba) << 11;
480 
481 // -----------------------------------------------------------------------------
482 
483  {
484  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
485 
486  cp.code() = std::string("//CJAL\n");
487 
488 // -----------------------------------------------------------------------------
489 { // block
490 cp.code() += "{ // block\n";
491 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
492 cp.code() += "} // block\n";
493 } // block
494 { // block
495 cp.code() += "{ // block\n";
496 cp.code() += "*((RV32IMACFD*)cpu)->X[1ULL] = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
497 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
498 cp.code() += "} // block\n";
499 } // block
500 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
501 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
502 // -----------------------------------------------------------------------------
503  cp.getAffectedRegisters().add("instructionPointer", 32);
504  }
505  {
506  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
507 
508  cp.code() = std::string("//CJAL\n");
509 
510 // -----------------------------------------------------------------------------
511 cp.code() += "return cpu->exception;\n";
512 // -----------------------------------------------------------------------------
513  }
514 
515  return true;
516  },
517  0,
518  [] (BitArray & ba, Instruction & instr)
519  {
520 // -----------------------------------------------------------------------------
521 etiss_uint16 imm = 0;
522 static BitArrayRange R_imm_5(2, 2);
523 imm += R_imm_5.read(ba) << 5;
524 static BitArrayRange R_imm_1(5, 3);
525 imm += R_imm_1.read(ba) << 1;
526 static BitArrayRange R_imm_7(6, 6);
527 imm += R_imm_7.read(ba) << 7;
528 static BitArrayRange R_imm_6(7, 7);
529 imm += R_imm_6.read(ba) << 6;
530 static BitArrayRange R_imm_10(8, 8);
531 imm += R_imm_10.read(ba) << 10;
532 static BitArrayRange R_imm_8(10, 9);
533 imm += R_imm_8.read(ba) << 8;
534 static BitArrayRange R_imm_4(11, 11);
535 imm += R_imm_4.read(ba) << 4;
536 static BitArrayRange R_imm_11(12, 12);
537 imm += R_imm_11.read(ba) << 11;
538 
539 // -----------------------------------------------------------------------------
540 
541  std::stringstream ss;
542 // -----------------------------------------------------------------------------
543 ss << "cjal" << " # " << ba << (" [imm=" + std::to_string(imm) + "]");
544 // -----------------------------------------------------------------------------
545  return ss.str();
546  }
547 );
548 
549 // CLI -------------------------------------------------------------------------
550 static InstructionDefinition cli_imm_rd (
551  ISA16_RV32IMACFD,
552  "cli",
553  (uint16_t) 0x4001,
554  (uint16_t) 0xe003,
555  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
556  {
557 
558 // -----------------------------------------------------------------------------
559 
560 // -----------------------------------------------------------------------------
561 
562 // -----------------------------------------------------------------------------
563 etiss_uint8 imm = 0;
564 static BitArrayRange R_imm_0(6, 2);
565 imm += R_imm_0.read(ba) << 0;
566 etiss_uint8 rd = 0;
567 static BitArrayRange R_rd_0(11, 7);
568 rd += R_rd_0.read(ba) << 0;
569 static BitArrayRange R_imm_5(12, 12);
570 imm += R_imm_5.read(ba) << 5;
571 
572 // -----------------------------------------------------------------------------
573 
574  {
575  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
576 
577  cp.code() = std::string("//CLI\n");
578 
579 // -----------------------------------------------------------------------------
580 { // block
581 cp.code() += "{ // block\n";
582 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
583 cp.code() += "} // block\n";
584 } // block
585 { // block
586 cp.code() += "{ // block\n";
587 if ((rd % 32ULL) != 0LL) { // conditional
588 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(((etiss_int8)(((etiss_int8)imm) << (2)) >> (2))) + "LL;\n";
589 } // conditional
590 cp.code() += "} // block\n";
591 } // block
592 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
593 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
594 // -----------------------------------------------------------------------------
595  cp.getAffectedRegisters().add("instructionPointer", 32);
596  }
597 
598  return true;
599  },
600  0,
601  [] (BitArray & ba, Instruction & instr)
602  {
603 // -----------------------------------------------------------------------------
604 etiss_uint8 imm = 0;
605 static BitArrayRange R_imm_0(6, 2);
606 imm += R_imm_0.read(ba) << 0;
607 etiss_uint8 rd = 0;
608 static BitArrayRange R_rd_0(11, 7);
609 rd += R_rd_0.read(ba) << 0;
610 static BitArrayRange R_imm_5(12, 12);
611 imm += R_imm_5.read(ba) << 5;
612 
613 // -----------------------------------------------------------------------------
614 
615  std::stringstream ss;
616 // -----------------------------------------------------------------------------
617 ss << "cli" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rd=" + std::to_string(rd) + "]");
618 // -----------------------------------------------------------------------------
619  return ss.str();
620  }
621 );
622 
623 // CLUI ------------------------------------------------------------------------
624 static InstructionDefinition clui_imm_rd (
625  ISA16_RV32IMACFD,
626  "clui",
627  (uint16_t) 0x6001,
628  (uint16_t) 0xe003,
629  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
630  {
631 
632 // -----------------------------------------------------------------------------
633 
634 // -----------------------------------------------------------------------------
635 
636 // -----------------------------------------------------------------------------
637 etiss_uint32 imm = 0;
638 static BitArrayRange R_imm_12(6, 2);
639 imm += R_imm_12.read(ba) << 12;
640 etiss_uint8 rd = 0;
641 static BitArrayRange R_rd_0(11, 7);
642 rd += R_rd_0.read(ba) << 0;
643 static BitArrayRange R_imm_17(12, 12);
644 imm += R_imm_17.read(ba) << 17;
645 
646 // -----------------------------------------------------------------------------
647 
648  {
649  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
650 
651  cp.code() = std::string("//CLUI\n");
652 
653 // -----------------------------------------------------------------------------
654 { // block
655 cp.code() += "{ // block\n";
656 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
657 cp.code() += "} // block\n";
658 } // block
659 { // block
660 cp.code() += "{ // block\n";
661 if (imm == 0LL) { // conditional
662 { // procedure
663 cp.code() += "{ // procedure\n";
664 cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";
665 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
666 cp.code() += "} // procedure\n";
667 } // procedure
668 } // conditional
669 if ((rd % 32ULL) != 0LL) { // conditional
670 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(((etiss_int32)(((etiss_int32)imm) << (14)) >> (14))) + "LL;\n";
671 } // conditional
672 cp.code() += "} // block\n";
673 } // block
674 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
675 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
676 // -----------------------------------------------------------------------------
677  cp.getAffectedRegisters().add("instructionPointer", 32);
678  }
679  {
680  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
681 
682  cp.code() = std::string("//CLUI\n");
683 
684 // -----------------------------------------------------------------------------
685 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
686 // -----------------------------------------------------------------------------
687  }
688 
689  return true;
690  },
691  0,
692  [] (BitArray & ba, Instruction & instr)
693  {
694 // -----------------------------------------------------------------------------
695 etiss_uint32 imm = 0;
696 static BitArrayRange R_imm_12(6, 2);
697 imm += R_imm_12.read(ba) << 12;
698 etiss_uint8 rd = 0;
699 static BitArrayRange R_rd_0(11, 7);
700 rd += R_rd_0.read(ba) << 0;
701 static BitArrayRange R_imm_17(12, 12);
702 imm += R_imm_17.read(ba) << 17;
703 
704 // -----------------------------------------------------------------------------
705 
706  std::stringstream ss;
707 // -----------------------------------------------------------------------------
708 ss << "clui" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rd=" + std::to_string(rd) + "]");
709 // -----------------------------------------------------------------------------
710  return ss.str();
711  }
712 );
713 
714 // CADDI16SP -------------------------------------------------------------------
715 static InstructionDefinition caddi16sp_nzimm (
716  ISA16_RV32IMACFD,
717  "caddi16sp",
718  (uint16_t) 0x6101,
719  (uint16_t) 0xef83,
720  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
721  {
722 
723 // -----------------------------------------------------------------------------
724 
725 // -----------------------------------------------------------------------------
726 
727 // -----------------------------------------------------------------------------
728 etiss_uint16 nzimm = 0;
729 static BitArrayRange R_nzimm_5(2, 2);
730 nzimm += R_nzimm_5.read(ba) << 5;
731 static BitArrayRange R_nzimm_7(4, 3);
732 nzimm += R_nzimm_7.read(ba) << 7;
733 static BitArrayRange R_nzimm_6(5, 5);
734 nzimm += R_nzimm_6.read(ba) << 6;
735 static BitArrayRange R_nzimm_4(6, 6);
736 nzimm += R_nzimm_4.read(ba) << 4;
737 static BitArrayRange R_nzimm_9(12, 12);
738 nzimm += R_nzimm_9.read(ba) << 9;
739 
740 // -----------------------------------------------------------------------------
741 
742  {
743  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
744 
745  cp.code() = std::string("//CADDI16SP\n");
746 
747 // -----------------------------------------------------------------------------
748 { // block
749 cp.code() += "{ // block\n";
750 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
751 cp.code() += "} // block\n";
752 } // block
753 if (nzimm) { // conditional
754 cp.code() += "*((RV32IMACFD*)cpu)->X[2ULL] = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)nzimm) << (6)) >> (6))) + "LL;\n";
755 } // conditional
756 else { // conditional
757 { // procedure
758 cp.code() += "{ // procedure\n";
759 cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";
760 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
761 cp.code() += "} // procedure\n";
762 } // procedure
763 } // conditional
764 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
765 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
766 // -----------------------------------------------------------------------------
767  cp.getAffectedRegisters().add("instructionPointer", 32);
768  }
769  {
770  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
771 
772  cp.code() = std::string("//CADDI16SP\n");
773 
774 // -----------------------------------------------------------------------------
775 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
776 // -----------------------------------------------------------------------------
777  }
778 
779  return true;
780  },
781  0,
782  [] (BitArray & ba, Instruction & instr)
783  {
784 // -----------------------------------------------------------------------------
785 etiss_uint16 nzimm = 0;
786 static BitArrayRange R_nzimm_5(2, 2);
787 nzimm += R_nzimm_5.read(ba) << 5;
788 static BitArrayRange R_nzimm_7(4, 3);
789 nzimm += R_nzimm_7.read(ba) << 7;
790 static BitArrayRange R_nzimm_6(5, 5);
791 nzimm += R_nzimm_6.read(ba) << 6;
792 static BitArrayRange R_nzimm_4(6, 6);
793 nzimm += R_nzimm_4.read(ba) << 4;
794 static BitArrayRange R_nzimm_9(12, 12);
795 nzimm += R_nzimm_9.read(ba) << 9;
796 
797 // -----------------------------------------------------------------------------
798 
799  std::stringstream ss;
800 // -----------------------------------------------------------------------------
801 ss << "caddi16sp" << " # " << ba << (" [nzimm=" + std::to_string(nzimm) + "]");
802 // -----------------------------------------------------------------------------
803  return ss.str();
804  }
805 );
806 
807 // __reserved_clui -------------------------------------------------------------
808 static InstructionDefinition __reserved_clui_rd (
809  ISA16_RV32IMACFD,
810  "__reserved_clui",
811  (uint16_t) 0x6001,
812  (uint16_t) 0xf07f,
813  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
814  {
815 
816 // -----------------------------------------------------------------------------
817 
818 // -----------------------------------------------------------------------------
819 
820 // -----------------------------------------------------------------------------
821 etiss_uint8 rd = 0;
822 static BitArrayRange R_rd_0(11, 7);
823 rd += R_rd_0.read(ba) << 0;
824 
825 // -----------------------------------------------------------------------------
826 
827  {
828  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
829 
830  cp.code() = std::string("//__reserved_clui\n");
831 
832 // -----------------------------------------------------------------------------
833 { // block
834 cp.code() += "{ // block\n";
835 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
836 cp.code() += "} // block\n";
837 } // block
838 { // procedure
839 cp.code() += "{ // procedure\n";
840 cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";
841 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
842 cp.code() += "} // procedure\n";
843 } // procedure
844 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
845 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
846 // -----------------------------------------------------------------------------
847  cp.getAffectedRegisters().add("instructionPointer", 32);
848  }
849  {
850  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
851 
852  cp.code() = std::string("//__reserved_clui\n");
853 
854 // -----------------------------------------------------------------------------
855 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
856 // -----------------------------------------------------------------------------
857  }
858 
859  return true;
860  },
861  0,
862  [] (BitArray & ba, Instruction & instr)
863  {
864 // -----------------------------------------------------------------------------
865 etiss_uint8 rd = 0;
866 static BitArrayRange R_rd_0(11, 7);
867 rd += R_rd_0.read(ba) << 0;
868 
869 // -----------------------------------------------------------------------------
870 
871  std::stringstream ss;
872 // -----------------------------------------------------------------------------
873 ss << "__reserved_clui" << " # " << ba << (" [rd=" + std::to_string(rd) + "]");
874 // -----------------------------------------------------------------------------
875  return ss.str();
876  }
877 );
878 
879 // CSRLI -----------------------------------------------------------------------
880 static InstructionDefinition csrli_shamt_rs1 (
881  ISA16_RV32IMACFD,
882  "csrli",
883  (uint16_t) 0x8001,
884  (uint16_t) 0xfc03,
885  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
886  {
887 
888 // -----------------------------------------------------------------------------
889 
890 // -----------------------------------------------------------------------------
891 
892 // -----------------------------------------------------------------------------
893 etiss_uint8 shamt = 0;
894 static BitArrayRange R_shamt_0(6, 2);
895 shamt += R_shamt_0.read(ba) << 0;
896 etiss_uint8 rs1 = 0;
897 static BitArrayRange R_rs1_0(9, 7);
898 rs1 += R_rs1_0.read(ba) << 0;
899 
900 // -----------------------------------------------------------------------------
901 
902  {
903  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
904 
905  cp.code() = std::string("//CSRLI\n");
906 
907 // -----------------------------------------------------------------------------
908 { // block
909 cp.code() += "{ // block\n";
910 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
911 cp.code() += "} // block\n";
912 } // block
913 { // block
914 cp.code() += "{ // block\n";
915 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] >> " + std::to_string(shamt) + "ULL;\n";
916 cp.code() += "} // block\n";
917 } // block
918 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
919 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
920 // -----------------------------------------------------------------------------
921  cp.getAffectedRegisters().add("instructionPointer", 32);
922  }
923 
924  return true;
925  },
926  0,
927  [] (BitArray & ba, Instruction & instr)
928  {
929 // -----------------------------------------------------------------------------
930 etiss_uint8 shamt = 0;
931 static BitArrayRange R_shamt_0(6, 2);
932 shamt += R_shamt_0.read(ba) << 0;
933 etiss_uint8 rs1 = 0;
934 static BitArrayRange R_rs1_0(9, 7);
935 rs1 += R_rs1_0.read(ba) << 0;
936 
937 // -----------------------------------------------------------------------------
938 
939  std::stringstream ss;
940 // -----------------------------------------------------------------------------
941 ss << "csrli" << " # " << ba << (" [shamt=" + std::to_string(shamt) + " | rs1=" + std::to_string(rs1) + "]");
942 // -----------------------------------------------------------------------------
943  return ss.str();
944  }
945 );
946 
947 // CSRAI -----------------------------------------------------------------------
948 static InstructionDefinition csrai_shamt_rs1 (
949  ISA16_RV32IMACFD,
950  "csrai",
951  (uint16_t) 0x8401,
952  (uint16_t) 0xfc03,
953  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
954  {
955 
956 // -----------------------------------------------------------------------------
957 
958 // -----------------------------------------------------------------------------
959 
960 // -----------------------------------------------------------------------------
961 etiss_uint8 shamt = 0;
962 static BitArrayRange R_shamt_0(6, 2);
963 shamt += R_shamt_0.read(ba) << 0;
964 etiss_uint8 rs1 = 0;
965 static BitArrayRange R_rs1_0(9, 7);
966 rs1 += R_rs1_0.read(ba) << 0;
967 
968 // -----------------------------------------------------------------------------
969 
970  {
971  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
972 
973  cp.code() = std::string("//CSRAI\n");
974 
975 // -----------------------------------------------------------------------------
976 { // block
977 cp.code() += "{ // block\n";
978 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
979 cp.code() += "} // block\n";
980 } // block
981 { // block
982 cp.code() += "{ // block\n";
983 if (shamt) { // conditional
984 { // block
985 cp.code() += "{ // block\n";
986 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL])) >> " + std::to_string(shamt) + "ULL;\n";
987 cp.code() += "} // block\n";
988 } // block
989 } // conditional
990 cp.code() += "} // block\n";
991 } // block
992 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
993 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
994 // -----------------------------------------------------------------------------
995  cp.getAffectedRegisters().add("instructionPointer", 32);
996  }
997 
998  return true;
999  },
1000  0,
1001  [] (BitArray & ba, Instruction & instr)
1002  {
1003 // -----------------------------------------------------------------------------
1004 etiss_uint8 shamt = 0;
1005 static BitArrayRange R_shamt_0(6, 2);
1006 shamt += R_shamt_0.read(ba) << 0;
1007 etiss_uint8 rs1 = 0;
1008 static BitArrayRange R_rs1_0(9, 7);
1009 rs1 += R_rs1_0.read(ba) << 0;
1010 
1011 // -----------------------------------------------------------------------------
1012 
1013  std::stringstream ss;
1014 // -----------------------------------------------------------------------------
1015 ss << "csrai" << " # " << ba << (" [shamt=" + std::to_string(shamt) + " | rs1=" + std::to_string(rs1) + "]");
1016 // -----------------------------------------------------------------------------
1017  return ss.str();
1018  }
1019 );
1020 
1021 // CANDI -----------------------------------------------------------------------
1022 static InstructionDefinition candi_imm_rs1 (
1023  ISA16_RV32IMACFD,
1024  "candi",
1025  (uint16_t) 0x8801,
1026  (uint16_t) 0xec03,
1027  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1028  {
1029 
1030 // -----------------------------------------------------------------------------
1031 
1032 // -----------------------------------------------------------------------------
1033 
1034 // -----------------------------------------------------------------------------
1035 etiss_uint8 imm = 0;
1036 static BitArrayRange R_imm_0(6, 2);
1037 imm += R_imm_0.read(ba) << 0;
1038 etiss_uint8 rs1 = 0;
1039 static BitArrayRange R_rs1_0(9, 7);
1040 rs1 += R_rs1_0.read(ba) << 0;
1041 static BitArrayRange R_imm_5(12, 12);
1042 imm += R_imm_5.read(ba) << 5;
1043 
1044 // -----------------------------------------------------------------------------
1045 
1046  {
1047  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1048 
1049  cp.code() = std::string("//CANDI\n");
1050 
1051 // -----------------------------------------------------------------------------
1052 { // block
1053 cp.code() += "{ // block\n";
1054 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1055 cp.code() += "} // block\n";
1056 } // block
1057 { // block
1058 cp.code() += "{ // block\n";
1059 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] & " + std::to_string(((etiss_int8)(((etiss_int8)imm) << (2)) >> (2))) + "LL;\n";
1060 cp.code() += "} // block\n";
1061 } // block
1062 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1063 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1064 // -----------------------------------------------------------------------------
1065  cp.getAffectedRegisters().add("instructionPointer", 32);
1066  }
1067 
1068  return true;
1069  },
1070  0,
1071  [] (BitArray & ba, Instruction & instr)
1072  {
1073 // -----------------------------------------------------------------------------
1074 etiss_uint8 imm = 0;
1075 static BitArrayRange R_imm_0(6, 2);
1076 imm += R_imm_0.read(ba) << 0;
1077 etiss_uint8 rs1 = 0;
1078 static BitArrayRange R_rs1_0(9, 7);
1079 rs1 += R_rs1_0.read(ba) << 0;
1080 static BitArrayRange R_imm_5(12, 12);
1081 imm += R_imm_5.read(ba) << 5;
1082 
1083 // -----------------------------------------------------------------------------
1084 
1085  std::stringstream ss;
1086 // -----------------------------------------------------------------------------
1087 ss << "candi" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + "]");
1088 // -----------------------------------------------------------------------------
1089  return ss.str();
1090  }
1091 );
1092 
1093 // CSUB ------------------------------------------------------------------------
1094 static InstructionDefinition csub_rs2_rd (
1095  ISA16_RV32IMACFD,
1096  "csub",
1097  (uint16_t) 0x8c01,
1098  (uint16_t) 0xfc63,
1099  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1100  {
1101 
1102 // -----------------------------------------------------------------------------
1103 
1104 // -----------------------------------------------------------------------------
1105 
1106 // -----------------------------------------------------------------------------
1107 etiss_uint8 rs2 = 0;
1108 static BitArrayRange R_rs2_0(4, 2);
1109 rs2 += R_rs2_0.read(ba) << 0;
1110 etiss_uint8 rd = 0;
1111 static BitArrayRange R_rd_0(9, 7);
1112 rd += R_rd_0.read(ba) << 0;
1113 
1114 // -----------------------------------------------------------------------------
1115 
1116  {
1117  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1118 
1119  cp.code() = std::string("//CSUB\n");
1120 
1121 // -----------------------------------------------------------------------------
1122 { // block
1123 cp.code() += "{ // block\n";
1124 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1125 cp.code() += "} // block\n";
1126 } // block
1127 { // block
1128 cp.code() += "{ // block\n";
1129 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] - *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n";
1130 cp.code() += "} // block\n";
1131 } // block
1132 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1133 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1134 // -----------------------------------------------------------------------------
1135  cp.getAffectedRegisters().add("instructionPointer", 32);
1136  }
1137 
1138  return true;
1139  },
1140  0,
1141  [] (BitArray & ba, Instruction & instr)
1142  {
1143 // -----------------------------------------------------------------------------
1144 etiss_uint8 rs2 = 0;
1145 static BitArrayRange R_rs2_0(4, 2);
1146 rs2 += R_rs2_0.read(ba) << 0;
1147 etiss_uint8 rd = 0;
1148 static BitArrayRange R_rd_0(9, 7);
1149 rd += R_rd_0.read(ba) << 0;
1150 
1151 // -----------------------------------------------------------------------------
1152 
1153  std::stringstream ss;
1154 // -----------------------------------------------------------------------------
1155 ss << "csub" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]");
1156 // -----------------------------------------------------------------------------
1157  return ss.str();
1158  }
1159 );
1160 
1161 // CXOR ------------------------------------------------------------------------
1162 static InstructionDefinition cxor_rs2_rd (
1163  ISA16_RV32IMACFD,
1164  "cxor",
1165  (uint16_t) 0x8c21,
1166  (uint16_t) 0xfc63,
1167  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1168  {
1169 
1170 // -----------------------------------------------------------------------------
1171 
1172 // -----------------------------------------------------------------------------
1173 
1174 // -----------------------------------------------------------------------------
1175 etiss_uint8 rs2 = 0;
1176 static BitArrayRange R_rs2_0(4, 2);
1177 rs2 += R_rs2_0.read(ba) << 0;
1178 etiss_uint8 rd = 0;
1179 static BitArrayRange R_rd_0(9, 7);
1180 rd += R_rd_0.read(ba) << 0;
1181 
1182 // -----------------------------------------------------------------------------
1183 
1184  {
1185  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1186 
1187  cp.code() = std::string("//CXOR\n");
1188 
1189 // -----------------------------------------------------------------------------
1190 { // block
1191 cp.code() += "{ // block\n";
1192 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1193 cp.code() += "} // block\n";
1194 } // block
1195 { // block
1196 cp.code() += "{ // block\n";
1197 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n";
1198 cp.code() += "} // block\n";
1199 } // block
1200 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1201 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1202 // -----------------------------------------------------------------------------
1203  cp.getAffectedRegisters().add("instructionPointer", 32);
1204  }
1205 
1206  return true;
1207  },
1208  0,
1209  [] (BitArray & ba, Instruction & instr)
1210  {
1211 // -----------------------------------------------------------------------------
1212 etiss_uint8 rs2 = 0;
1213 static BitArrayRange R_rs2_0(4, 2);
1214 rs2 += R_rs2_0.read(ba) << 0;
1215 etiss_uint8 rd = 0;
1216 static BitArrayRange R_rd_0(9, 7);
1217 rd += R_rd_0.read(ba) << 0;
1218 
1219 // -----------------------------------------------------------------------------
1220 
1221  std::stringstream ss;
1222 // -----------------------------------------------------------------------------
1223 ss << "cxor" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]");
1224 // -----------------------------------------------------------------------------
1225  return ss.str();
1226  }
1227 );
1228 
1229 // COR -------------------------------------------------------------------------
1230 static InstructionDefinition cor_rs2_rd (
1231  ISA16_RV32IMACFD,
1232  "cor",
1233  (uint16_t) 0x8c41,
1234  (uint16_t) 0xfc63,
1235  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1236  {
1237 
1238 // -----------------------------------------------------------------------------
1239 
1240 // -----------------------------------------------------------------------------
1241 
1242 // -----------------------------------------------------------------------------
1243 etiss_uint8 rs2 = 0;
1244 static BitArrayRange R_rs2_0(4, 2);
1245 rs2 += R_rs2_0.read(ba) << 0;
1246 etiss_uint8 rd = 0;
1247 static BitArrayRange R_rd_0(9, 7);
1248 rd += R_rd_0.read(ba) << 0;
1249 
1250 // -----------------------------------------------------------------------------
1251 
1252  {
1253  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1254 
1255  cp.code() = std::string("//COR\n");
1256 
1257 // -----------------------------------------------------------------------------
1258 { // block
1259 cp.code() += "{ // block\n";
1260 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1261 cp.code() += "} // block\n";
1262 } // block
1263 { // block
1264 cp.code() += "{ // block\n";
1265 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n";
1266 cp.code() += "} // block\n";
1267 } // block
1268 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1269 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1270 // -----------------------------------------------------------------------------
1271  cp.getAffectedRegisters().add("instructionPointer", 32);
1272  }
1273 
1274  return true;
1275  },
1276  0,
1277  [] (BitArray & ba, Instruction & instr)
1278  {
1279 // -----------------------------------------------------------------------------
1280 etiss_uint8 rs2 = 0;
1281 static BitArrayRange R_rs2_0(4, 2);
1282 rs2 += R_rs2_0.read(ba) << 0;
1283 etiss_uint8 rd = 0;
1284 static BitArrayRange R_rd_0(9, 7);
1285 rd += R_rd_0.read(ba) << 0;
1286 
1287 // -----------------------------------------------------------------------------
1288 
1289  std::stringstream ss;
1290 // -----------------------------------------------------------------------------
1291 ss << "cor" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]");
1292 // -----------------------------------------------------------------------------
1293  return ss.str();
1294  }
1295 );
1296 
1297 // CAND ------------------------------------------------------------------------
1298 static InstructionDefinition cand_rs2_rd (
1299  ISA16_RV32IMACFD,
1300  "cand",
1301  (uint16_t) 0x8c61,
1302  (uint16_t) 0xfc63,
1303  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1304  {
1305 
1306 // -----------------------------------------------------------------------------
1307 
1308 // -----------------------------------------------------------------------------
1309 
1310 // -----------------------------------------------------------------------------
1311 etiss_uint8 rs2 = 0;
1312 static BitArrayRange R_rs2_0(4, 2);
1313 rs2 += R_rs2_0.read(ba) << 0;
1314 etiss_uint8 rd = 0;
1315 static BitArrayRange R_rd_0(9, 7);
1316 rd += R_rd_0.read(ba) << 0;
1317 
1318 // -----------------------------------------------------------------------------
1319 
1320  {
1321  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1322 
1323  cp.code() = std::string("//CAND\n");
1324 
1325 // -----------------------------------------------------------------------------
1326 { // block
1327 cp.code() += "{ // block\n";
1328 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1329 cp.code() += "} // block\n";
1330 } // block
1331 { // block
1332 cp.code() += "{ // block\n";
1333 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n";
1334 cp.code() += "} // block\n";
1335 } // block
1336 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1337 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1338 // -----------------------------------------------------------------------------
1339  cp.getAffectedRegisters().add("instructionPointer", 32);
1340  }
1341 
1342  return true;
1343  },
1344  0,
1345  [] (BitArray & ba, Instruction & instr)
1346  {
1347 // -----------------------------------------------------------------------------
1348 etiss_uint8 rs2 = 0;
1349 static BitArrayRange R_rs2_0(4, 2);
1350 rs2 += R_rs2_0.read(ba) << 0;
1351 etiss_uint8 rd = 0;
1352 static BitArrayRange R_rd_0(9, 7);
1353 rd += R_rd_0.read(ba) << 0;
1354 
1355 // -----------------------------------------------------------------------------
1356 
1357  std::stringstream ss;
1358 // -----------------------------------------------------------------------------
1359 ss << "cand" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]");
1360 // -----------------------------------------------------------------------------
1361  return ss.str();
1362  }
1363 );
1364 
1365 // CJ --------------------------------------------------------------------------
1366 static InstructionDefinition cj_imm (
1367  ISA16_RV32IMACFD,
1368  "cj",
1369  (uint16_t) 0xa001,
1370  (uint16_t) 0xe003,
1371  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1372  {
1373 
1374 // -----------------------------------------------------------------------------
1375 
1376 // -----------------------------------------------------------------------------
1377 
1378 // -----------------------------------------------------------------------------
1379 etiss_uint16 imm = 0;
1380 static BitArrayRange R_imm_5(2, 2);
1381 imm += R_imm_5.read(ba) << 5;
1382 static BitArrayRange R_imm_1(5, 3);
1383 imm += R_imm_1.read(ba) << 1;
1384 static BitArrayRange R_imm_7(6, 6);
1385 imm += R_imm_7.read(ba) << 7;
1386 static BitArrayRange R_imm_6(7, 7);
1387 imm += R_imm_6.read(ba) << 6;
1388 static BitArrayRange R_imm_10(8, 8);
1389 imm += R_imm_10.read(ba) << 10;
1390 static BitArrayRange R_imm_8(10, 9);
1391 imm += R_imm_8.read(ba) << 8;
1392 static BitArrayRange R_imm_4(11, 11);
1393 imm += R_imm_4.read(ba) << 4;
1394 static BitArrayRange R_imm_11(12, 12);
1395 imm += R_imm_11.read(ba) << 11;
1396 
1397 // -----------------------------------------------------------------------------
1398 
1399  {
1400  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1401 
1402  cp.code() = std::string("//CJ\n");
1403 
1404 // -----------------------------------------------------------------------------
1405 { // block
1406 cp.code() += "{ // block\n";
1407 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1408 cp.code() += "} // block\n";
1409 } // block
1410 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1411 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1412 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1413 // -----------------------------------------------------------------------------
1414  cp.getAffectedRegisters().add("instructionPointer", 32);
1415  }
1416  {
1417  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1418 
1419  cp.code() = std::string("//CJ\n");
1420 
1421 // -----------------------------------------------------------------------------
1422 cp.code() += "return cpu->exception;\n";
1423 // -----------------------------------------------------------------------------
1424  }
1425 
1426  return true;
1427  },
1428  0,
1429  [] (BitArray & ba, Instruction & instr)
1430  {
1431 // -----------------------------------------------------------------------------
1432 etiss_uint16 imm = 0;
1433 static BitArrayRange R_imm_5(2, 2);
1434 imm += R_imm_5.read(ba) << 5;
1435 static BitArrayRange R_imm_1(5, 3);
1436 imm += R_imm_1.read(ba) << 1;
1437 static BitArrayRange R_imm_7(6, 6);
1438 imm += R_imm_7.read(ba) << 7;
1439 static BitArrayRange R_imm_6(7, 7);
1440 imm += R_imm_6.read(ba) << 6;
1441 static BitArrayRange R_imm_10(8, 8);
1442 imm += R_imm_10.read(ba) << 10;
1443 static BitArrayRange R_imm_8(10, 9);
1444 imm += R_imm_8.read(ba) << 8;
1445 static BitArrayRange R_imm_4(11, 11);
1446 imm += R_imm_4.read(ba) << 4;
1447 static BitArrayRange R_imm_11(12, 12);
1448 imm += R_imm_11.read(ba) << 11;
1449 
1450 // -----------------------------------------------------------------------------
1451 
1452  std::stringstream ss;
1453 // -----------------------------------------------------------------------------
1454 ss << "cj" << " # " << ba << (" [imm=" + std::to_string(imm) + "]");
1455 // -----------------------------------------------------------------------------
1456  return ss.str();
1457  }
1458 );
1459 
1460 // CBEQZ -----------------------------------------------------------------------
1461 static InstructionDefinition cbeqz_imm_rs1 (
1462  ISA16_RV32IMACFD,
1463  "cbeqz",
1464  (uint16_t) 0xc001,
1465  (uint16_t) 0xe003,
1466  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1467  {
1468 
1469 // -----------------------------------------------------------------------------
1470 
1471 // -----------------------------------------------------------------------------
1472 
1473 // -----------------------------------------------------------------------------
1474 etiss_uint16 imm = 0;
1475 static BitArrayRange R_imm_5(2, 2);
1476 imm += R_imm_5.read(ba) << 5;
1477 static BitArrayRange R_imm_1(4, 3);
1478 imm += R_imm_1.read(ba) << 1;
1479 static BitArrayRange R_imm_6(6, 5);
1480 imm += R_imm_6.read(ba) << 6;
1481 etiss_uint8 rs1 = 0;
1482 static BitArrayRange R_rs1_0(9, 7);
1483 rs1 += R_rs1_0.read(ba) << 0;
1484 static BitArrayRange R_imm_3(11, 10);
1485 imm += R_imm_3.read(ba) << 3;
1486 static BitArrayRange R_imm_8(12, 12);
1487 imm += R_imm_8.read(ba) << 8;
1488 
1489 // -----------------------------------------------------------------------------
1490 
1491  {
1492  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1493 
1494  cp.code() = std::string("//CBEQZ\n");
1495 
1496 // -----------------------------------------------------------------------------
1497 { // block
1498 cp.code() += "{ // block\n";
1499 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1500 cp.code() += "} // block\n";
1501 } // block
1502 cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] == 0LL) { // conditional\n";
1503 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (7)) >> (7))) + "LL;\n";
1504 cp.code() += "} // conditional\n";
1505 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1506 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1507 // -----------------------------------------------------------------------------
1508  cp.getAffectedRegisters().add("instructionPointer", 32);
1509  }
1510  {
1511  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1512 
1513  cp.code() = std::string("//CBEQZ\n");
1514 
1515 // -----------------------------------------------------------------------------
1516 cp.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + "ULL) return cpu->exception;\n";
1517 // -----------------------------------------------------------------------------
1518  }
1519 
1520  return true;
1521  },
1522  0,
1523  [] (BitArray & ba, Instruction & instr)
1524  {
1525 // -----------------------------------------------------------------------------
1526 etiss_uint16 imm = 0;
1527 static BitArrayRange R_imm_5(2, 2);
1528 imm += R_imm_5.read(ba) << 5;
1529 static BitArrayRange R_imm_1(4, 3);
1530 imm += R_imm_1.read(ba) << 1;
1531 static BitArrayRange R_imm_6(6, 5);
1532 imm += R_imm_6.read(ba) << 6;
1533 etiss_uint8 rs1 = 0;
1534 static BitArrayRange R_rs1_0(9, 7);
1535 rs1 += R_rs1_0.read(ba) << 0;
1536 static BitArrayRange R_imm_3(11, 10);
1537 imm += R_imm_3.read(ba) << 3;
1538 static BitArrayRange R_imm_8(12, 12);
1539 imm += R_imm_8.read(ba) << 8;
1540 
1541 // -----------------------------------------------------------------------------
1542 
1543  std::stringstream ss;
1544 // -----------------------------------------------------------------------------
1545 ss << "cbeqz" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + "]");
1546 // -----------------------------------------------------------------------------
1547  return ss.str();
1548  }
1549 );
1550 
1551 // CBNEZ -----------------------------------------------------------------------
1552 static InstructionDefinition cbnez_imm_rs1 (
1553  ISA16_RV32IMACFD,
1554  "cbnez",
1555  (uint16_t) 0xe001,
1556  (uint16_t) 0xe003,
1557  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1558  {
1559 
1560 // -----------------------------------------------------------------------------
1561 
1562 // -----------------------------------------------------------------------------
1563 
1564 // -----------------------------------------------------------------------------
1565 etiss_uint16 imm = 0;
1566 static BitArrayRange R_imm_5(2, 2);
1567 imm += R_imm_5.read(ba) << 5;
1568 static BitArrayRange R_imm_1(4, 3);
1569 imm += R_imm_1.read(ba) << 1;
1570 static BitArrayRange R_imm_6(6, 5);
1571 imm += R_imm_6.read(ba) << 6;
1572 etiss_uint8 rs1 = 0;
1573 static BitArrayRange R_rs1_0(9, 7);
1574 rs1 += R_rs1_0.read(ba) << 0;
1575 static BitArrayRange R_imm_3(11, 10);
1576 imm += R_imm_3.read(ba) << 3;
1577 static BitArrayRange R_imm_8(12, 12);
1578 imm += R_imm_8.read(ba) << 8;
1579 
1580 // -----------------------------------------------------------------------------
1581 
1582  {
1583  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1584 
1585  cp.code() = std::string("//CBNEZ\n");
1586 
1587 // -----------------------------------------------------------------------------
1588 { // block
1589 cp.code() += "{ // block\n";
1590 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1591 cp.code() += "} // block\n";
1592 } // block
1593 cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] != 0LL) { // conditional\n";
1594 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (7)) >> (7))) + "LL;\n";
1595 cp.code() += "} // conditional\n";
1596 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1597 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1598 // -----------------------------------------------------------------------------
1599  cp.getAffectedRegisters().add("instructionPointer", 32);
1600  }
1601  {
1602  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1603 
1604  cp.code() = std::string("//CBNEZ\n");
1605 
1606 // -----------------------------------------------------------------------------
1607 cp.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + "ULL) return cpu->exception;\n";
1608 // -----------------------------------------------------------------------------
1609  }
1610 
1611  return true;
1612  },
1613  0,
1614  [] (BitArray & ba, Instruction & instr)
1615  {
1616 // -----------------------------------------------------------------------------
1617 etiss_uint16 imm = 0;
1618 static BitArrayRange R_imm_5(2, 2);
1619 imm += R_imm_5.read(ba) << 5;
1620 static BitArrayRange R_imm_1(4, 3);
1621 imm += R_imm_1.read(ba) << 1;
1622 static BitArrayRange R_imm_6(6, 5);
1623 imm += R_imm_6.read(ba) << 6;
1624 etiss_uint8 rs1 = 0;
1625 static BitArrayRange R_rs1_0(9, 7);
1626 rs1 += R_rs1_0.read(ba) << 0;
1627 static BitArrayRange R_imm_3(11, 10);
1628 imm += R_imm_3.read(ba) << 3;
1629 static BitArrayRange R_imm_8(12, 12);
1630 imm += R_imm_8.read(ba) << 8;
1631 
1632 // -----------------------------------------------------------------------------
1633 
1634  std::stringstream ss;
1635 // -----------------------------------------------------------------------------
1636 ss << "cbnez" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + "]");
1637 // -----------------------------------------------------------------------------
1638  return ss.str();
1639  }
1640 );
1641 
1642 // CSLLI -----------------------------------------------------------------------
1643 static InstructionDefinition cslli_nzuimm_rs1 (
1644  ISA16_RV32IMACFD,
1645  "cslli",
1646  (uint16_t) 0x02,
1647  (uint16_t) 0xf003,
1648  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1649  {
1650 
1651 // -----------------------------------------------------------------------------
1652 
1653 // -----------------------------------------------------------------------------
1654 
1655 // -----------------------------------------------------------------------------
1656 etiss_uint8 nzuimm = 0;
1657 static BitArrayRange R_nzuimm_0(6, 2);
1658 nzuimm += R_nzuimm_0.read(ba) << 0;
1659 etiss_uint8 rs1 = 0;
1660 static BitArrayRange R_rs1_0(11, 7);
1661 rs1 += R_rs1_0.read(ba) << 0;
1662 
1663 // -----------------------------------------------------------------------------
1664 
1665  {
1666  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1667 
1668  cp.code() = std::string("//CSLLI\n");
1669 
1670 // -----------------------------------------------------------------------------
1671 { // block
1672 cp.code() += "{ // block\n";
1673 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1674 cp.code() += "} // block\n";
1675 } // block
1676 if (nzuimm) { // conditional
1677 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << " + std::to_string(nzuimm) + "ULL;\n";
1678 } // conditional
1679 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1680 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1681 // -----------------------------------------------------------------------------
1682  cp.getAffectedRegisters().add("instructionPointer", 32);
1683  }
1684 
1685  return true;
1686  },
1687  0,
1688  [] (BitArray & ba, Instruction & instr)
1689  {
1690 // -----------------------------------------------------------------------------
1691 etiss_uint8 nzuimm = 0;
1692 static BitArrayRange R_nzuimm_0(6, 2);
1693 nzuimm += R_nzuimm_0.read(ba) << 0;
1694 etiss_uint8 rs1 = 0;
1695 static BitArrayRange R_rs1_0(11, 7);
1696 rs1 += R_rs1_0.read(ba) << 0;
1697 
1698 // -----------------------------------------------------------------------------
1699 
1700  std::stringstream ss;
1701 // -----------------------------------------------------------------------------
1702 ss << "cslli" << " # " << ba << (" [nzuimm=" + std::to_string(nzuimm) + " | rs1=" + std::to_string(rs1) + "]");
1703 // -----------------------------------------------------------------------------
1704  return ss.str();
1705  }
1706 );
1707 
1708 // CLWSP -----------------------------------------------------------------------
1709 static InstructionDefinition clwsp_uimm_rd (
1710  ISA16_RV32IMACFD,
1711  "clwsp",
1712  (uint16_t) 0x4002,
1713  (uint16_t) 0xe003,
1714  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1715  {
1716 
1717 // -----------------------------------------------------------------------------
1718 
1719 // -----------------------------------------------------------------------------
1720 
1721 // -----------------------------------------------------------------------------
1722 etiss_uint8 uimm = 0;
1723 static BitArrayRange R_uimm_6(3, 2);
1724 uimm += R_uimm_6.read(ba) << 6;
1725 static BitArrayRange R_uimm_2(6, 4);
1726 uimm += R_uimm_2.read(ba) << 2;
1727 etiss_uint8 rd = 0;
1728 static BitArrayRange R_rd_0(11, 7);
1729 rd += R_rd_0.read(ba) << 0;
1730 static BitArrayRange R_uimm_5(12, 12);
1731 uimm += R_uimm_5.read(ba) << 5;
1732 
1733 // -----------------------------------------------------------------------------
1734 
1735  {
1736  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1737 
1738  cp.code() = std::string("//CLWSP\n");
1739 
1740 // -----------------------------------------------------------------------------
1741 { // block
1742 cp.code() += "{ // block\n";
1743 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1744 cp.code() += "} // block\n";
1745 } // block
1746 { // block
1747 cp.code() += "{ // block\n";
1748 if (rd % 32ULL) { // conditional
1749 { // block
1750 cp.code() += "{ // block\n";
1751 cp.code() += "etiss_uint32 mem_val_0;\n";
1752 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL, (etiss_uint8*)&mem_val_0, 4);\n";
1753 cp.code() += "if (cpu->exception) { // conditional\n";
1754 { // procedure
1755 cp.code() += "{ // procedure\n";
1756 cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1757 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1758 cp.code() += "} // procedure\n";
1759 } // procedure
1760 cp.code() += "} // conditional\n";
1761 cp.code() += "etiss_int32 res = mem_val_0;\n";
1762 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(res);\n";
1763 cp.code() += "} // block\n";
1764 } // block
1765 } // conditional
1766 else { // conditional
1767 { // procedure
1768 cp.code() += "{ // procedure\n";
1769 cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2ULL);\n";
1770 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1771 cp.code() += "} // procedure\n";
1772 } // procedure
1773 } // conditional
1774 cp.code() += "} // block\n";
1775 } // block
1776 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1777 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1778 // -----------------------------------------------------------------------------
1779  cp.getAffectedRegisters().add("instructionPointer", 32);
1780  }
1781  {
1782  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1783 
1784  cp.code() = std::string("//CLWSP\n");
1785 
1786 // -----------------------------------------------------------------------------
1787 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1788 // -----------------------------------------------------------------------------
1789  }
1790 
1791  return true;
1792  },
1793  0,
1794  [] (BitArray & ba, Instruction & instr)
1795  {
1796 // -----------------------------------------------------------------------------
1797 etiss_uint8 uimm = 0;
1798 static BitArrayRange R_uimm_6(3, 2);
1799 uimm += R_uimm_6.read(ba) << 6;
1800 static BitArrayRange R_uimm_2(6, 4);
1801 uimm += R_uimm_2.read(ba) << 2;
1802 etiss_uint8 rd = 0;
1803 static BitArrayRange R_rd_0(11, 7);
1804 rd += R_rd_0.read(ba) << 0;
1805 static BitArrayRange R_uimm_5(12, 12);
1806 uimm += R_uimm_5.read(ba) << 5;
1807 
1808 // -----------------------------------------------------------------------------
1809 
1810  std::stringstream ss;
1811 // -----------------------------------------------------------------------------
1812 ss << "clwsp" << " # " << ba << (" [uimm=" + std::to_string(uimm) + " | rd=" + std::to_string(rd) + "]");
1813 // -----------------------------------------------------------------------------
1814  return ss.str();
1815  }
1816 );
1817 
1818 // CMV -------------------------------------------------------------------------
1819 static InstructionDefinition cmv_rs2_rd (
1820  ISA16_RV32IMACFD,
1821  "cmv",
1822  (uint16_t) 0x8002,
1823  (uint16_t) 0xf003,
1824  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1825  {
1826 
1827 // -----------------------------------------------------------------------------
1828 
1829 // -----------------------------------------------------------------------------
1830 
1831 // -----------------------------------------------------------------------------
1832 etiss_uint8 rs2 = 0;
1833 static BitArrayRange R_rs2_0(6, 2);
1834 rs2 += R_rs2_0.read(ba) << 0;
1835 etiss_uint8 rd = 0;
1836 static BitArrayRange R_rd_0(11, 7);
1837 rd += R_rd_0.read(ba) << 0;
1838 
1839 // -----------------------------------------------------------------------------
1840 
1841  {
1842  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1843 
1844  cp.code() = std::string("//CMV\n");
1845 
1846 // -----------------------------------------------------------------------------
1847 { // block
1848 cp.code() += "{ // block\n";
1849 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1850 cp.code() += "} // block\n";
1851 } // block
1852 if ((rd % 32ULL) != 0LL) { // conditional
1853 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
1854 } // conditional
1855 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1856 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1857 // -----------------------------------------------------------------------------
1858  cp.getAffectedRegisters().add("instructionPointer", 32);
1859  }
1860 
1861  return true;
1862  },
1863  0,
1864  [] (BitArray & ba, Instruction & instr)
1865  {
1866 // -----------------------------------------------------------------------------
1867 etiss_uint8 rs2 = 0;
1868 static BitArrayRange R_rs2_0(6, 2);
1869 rs2 += R_rs2_0.read(ba) << 0;
1870 etiss_uint8 rd = 0;
1871 static BitArrayRange R_rd_0(11, 7);
1872 rd += R_rd_0.read(ba) << 0;
1873 
1874 // -----------------------------------------------------------------------------
1875 
1876  std::stringstream ss;
1877 // -----------------------------------------------------------------------------
1878 ss << "cmv" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]");
1879 // -----------------------------------------------------------------------------
1880  return ss.str();
1881  }
1882 );
1883 
1884 // CJR -------------------------------------------------------------------------
1885 static InstructionDefinition cjr_rs1 (
1886  ISA16_RV32IMACFD,
1887  "cjr",
1888  (uint16_t) 0x8002,
1889  (uint16_t) 0xf07f,
1890  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1891  {
1892 
1893 // -----------------------------------------------------------------------------
1894 
1895 // -----------------------------------------------------------------------------
1896 
1897 // -----------------------------------------------------------------------------
1898 etiss_uint8 rs1 = 0;
1899 static BitArrayRange R_rs1_0(11, 7);
1900 rs1 += R_rs1_0.read(ba) << 0;
1901 
1902 // -----------------------------------------------------------------------------
1903 
1904  {
1905  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1906 
1907  cp.code() = std::string("//CJR\n");
1908 
1909 // -----------------------------------------------------------------------------
1910 { // block
1911 cp.code() += "{ // block\n";
1912 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1913 cp.code() += "} // block\n";
1914 } // block
1915 if (rs1) { // conditional
1916 cp.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] & -2LL;\n";
1917 } // conditional
1918 else { // conditional
1919 { // procedure
1920 cp.code() += "{ // procedure\n";
1921 cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2ULL);\n";
1922 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1923 cp.code() += "} // procedure\n";
1924 } // procedure
1925 } // conditional
1926 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1927 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1928 // -----------------------------------------------------------------------------
1929  cp.getAffectedRegisters().add("instructionPointer", 32);
1930  }
1931  {
1932  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1933 
1934  cp.code() = std::string("//CJR\n");
1935 
1936 // -----------------------------------------------------------------------------
1937 cp.code() += "return cpu->exception;\n";
1938 // -----------------------------------------------------------------------------
1939  }
1940 
1941  return true;
1942  },
1943  0,
1944  [] (BitArray & ba, Instruction & instr)
1945  {
1946 // -----------------------------------------------------------------------------
1947 etiss_uint8 rs1 = 0;
1948 static BitArrayRange R_rs1_0(11, 7);
1949 rs1 += R_rs1_0.read(ba) << 0;
1950 
1951 // -----------------------------------------------------------------------------
1952 
1953  std::stringstream ss;
1954 // -----------------------------------------------------------------------------
1955 ss << "cjr" << " # " << ba << (" [rs1=" + std::to_string(rs1) + "]");
1956 // -----------------------------------------------------------------------------
1957  return ss.str();
1958  }
1959 );
1960 
1961 // __reserved_cmv --------------------------------------------------------------
1962 static InstructionDefinition __reserved_cmv_ (
1963  ISA16_RV32IMACFD,
1964  "__reserved_cmv",
1965  (uint16_t) 0x8002,
1966  (uint16_t) 0xffff,
1967  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1968  {
1969 
1970 // -----------------------------------------------------------------------------
1971 
1972 // -----------------------------------------------------------------------------
1973 
1974 // -----------------------------------------------------------------------------
1975 
1976 // -----------------------------------------------------------------------------
1977 
1978  {
1979  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1980 
1981  cp.code() = std::string("//__reserved_cmv\n");
1982 
1983 // -----------------------------------------------------------------------------
1984 { // block
1985 cp.code() += "{ // block\n";
1986 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1987 cp.code() += "} // block\n";
1988 } // block
1989 { // procedure
1990 cp.code() += "{ // procedure\n";
1991 cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2ULL);\n";
1992 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1993 cp.code() += "} // procedure\n";
1994 } // procedure
1995 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1996 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1997 // -----------------------------------------------------------------------------
1998  cp.getAffectedRegisters().add("instructionPointer", 32);
1999  }
2000  {
2001  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
2002 
2003  cp.code() = std::string("//__reserved_cmv\n");
2004 
2005 // -----------------------------------------------------------------------------
2006 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
2007 // -----------------------------------------------------------------------------
2008  }
2009 
2010  return true;
2011  },
2012  0,
2013  [] (BitArray & ba, Instruction & instr)
2014  {
2015 // -----------------------------------------------------------------------------
2016 
2017 // -----------------------------------------------------------------------------
2018 
2019  std::stringstream ss;
2020 // -----------------------------------------------------------------------------
2021 ss << "__reserved_cmv" << " # " << ba << (" []");
2022 // -----------------------------------------------------------------------------
2023  return ss.str();
2024  }
2025 );
2026 
2027 // CADD ------------------------------------------------------------------------
2028 static InstructionDefinition cadd_rs2_rd (
2029  ISA16_RV32IMACFD,
2030  "cadd",
2031  (uint16_t) 0x9002,
2032  (uint16_t) 0xf003,
2033  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2034  {
2035 
2036 // -----------------------------------------------------------------------------
2037 
2038 // -----------------------------------------------------------------------------
2039 
2040 // -----------------------------------------------------------------------------
2041 etiss_uint8 rs2 = 0;
2042 static BitArrayRange R_rs2_0(6, 2);
2043 rs2 += R_rs2_0.read(ba) << 0;
2044 etiss_uint8 rd = 0;
2045 static BitArrayRange R_rd_0(11, 7);
2046 rd += R_rd_0.read(ba) << 0;
2047 
2048 // -----------------------------------------------------------------------------
2049 
2050  {
2051  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2052 
2053  cp.code() = std::string("//CADD\n");
2054 
2055 // -----------------------------------------------------------------------------
2056 { // block
2057 cp.code() += "{ // block\n";
2058 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
2059 cp.code() += "} // block\n";
2060 } // block
2061 if ((rd % 32ULL) != 0LL) { // conditional
2062 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
2063 } // conditional
2064 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2065 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2066 // -----------------------------------------------------------------------------
2067  cp.getAffectedRegisters().add("instructionPointer", 32);
2068  }
2069 
2070  return true;
2071  },
2072  0,
2073  [] (BitArray & ba, Instruction & instr)
2074  {
2075 // -----------------------------------------------------------------------------
2076 etiss_uint8 rs2 = 0;
2077 static BitArrayRange R_rs2_0(6, 2);
2078 rs2 += R_rs2_0.read(ba) << 0;
2079 etiss_uint8 rd = 0;
2080 static BitArrayRange R_rd_0(11, 7);
2081 rd += R_rd_0.read(ba) << 0;
2082 
2083 // -----------------------------------------------------------------------------
2084 
2085  std::stringstream ss;
2086 // -----------------------------------------------------------------------------
2087 ss << "cadd" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]");
2088 // -----------------------------------------------------------------------------
2089  return ss.str();
2090  }
2091 );
2092 
2093 // CJALR -----------------------------------------------------------------------
2094 static InstructionDefinition cjalr_rs1 (
2095  ISA16_RV32IMACFD,
2096  "cjalr",
2097  (uint16_t) 0x9002,
2098  (uint16_t) 0xf07f,
2099  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2100  {
2101 
2102 // -----------------------------------------------------------------------------
2103 
2104 // -----------------------------------------------------------------------------
2105 
2106 // -----------------------------------------------------------------------------
2107 etiss_uint8 rs1 = 0;
2108 static BitArrayRange R_rs1_0(11, 7);
2109 rs1 += R_rs1_0.read(ba) << 0;
2110 
2111 // -----------------------------------------------------------------------------
2112 
2113  {
2114  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2115 
2116  cp.code() = std::string("//CJALR\n");
2117 
2118 // -----------------------------------------------------------------------------
2119 { // block
2120 cp.code() += "{ // block\n";
2121 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
2122 cp.code() += "} // block\n";
2123 } // block
2124 { // block
2125 cp.code() += "{ // block\n";
2126 cp.code() += "etiss_uint32 new_pc = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
2127 cp.code() += "*((RV32IMACFD*)cpu)->X[1ULL] = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
2128 cp.code() += "cpu->nextPc = new_pc & -2LL;\n";
2129 cp.code() += "} // block\n";
2130 } // block
2131 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2132 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2133 // -----------------------------------------------------------------------------
2134  cp.getAffectedRegisters().add("instructionPointer", 32);
2135  }
2136  {
2137  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
2138 
2139  cp.code() = std::string("//CJALR\n");
2140 
2141 // -----------------------------------------------------------------------------
2142 cp.code() += "return cpu->exception;\n";
2143 // -----------------------------------------------------------------------------
2144  }
2145 
2146  return true;
2147  },
2148  0,
2149  [] (BitArray & ba, Instruction & instr)
2150  {
2151 // -----------------------------------------------------------------------------
2152 etiss_uint8 rs1 = 0;
2153 static BitArrayRange R_rs1_0(11, 7);
2154 rs1 += R_rs1_0.read(ba) << 0;
2155 
2156 // -----------------------------------------------------------------------------
2157 
2158  std::stringstream ss;
2159 // -----------------------------------------------------------------------------
2160 ss << "cjalr" << " # " << ba << (" [rs1=" + std::to_string(rs1) + "]");
2161 // -----------------------------------------------------------------------------
2162  return ss.str();
2163  }
2164 );
2165 
2166 // CEBREAK ---------------------------------------------------------------------
2167 static InstructionDefinition cebreak_ (
2168  ISA16_RV32IMACFD,
2169  "cebreak",
2170  (uint16_t) 0x9002,
2171  (uint16_t) 0xffff,
2172  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2173  {
2174 
2175 // -----------------------------------------------------------------------------
2176 
2177 // -----------------------------------------------------------------------------
2178 
2179 // -----------------------------------------------------------------------------
2180 
2181 // -----------------------------------------------------------------------------
2182 
2183  {
2184  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2185 
2186  cp.code() = std::string("//CEBREAK\n");
2187 
2188 // -----------------------------------------------------------------------------
2189 { // block
2190 cp.code() += "{ // block\n";
2191 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
2192 cp.code() += "} // block\n";
2193 } // block
2194 { // procedure
2195 cp.code() += "{ // procedure\n";
2196 cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 3LL);\n";
2197 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
2198 cp.code() += "} // procedure\n";
2199 } // procedure
2200 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2201 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2202 // -----------------------------------------------------------------------------
2203  cp.getAffectedRegisters().add("instructionPointer", 32);
2204  }
2205  {
2206  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
2207 
2208  cp.code() = std::string("//CEBREAK\n");
2209 
2210 // -----------------------------------------------------------------------------
2211 cp.code() += "return cpu->exception;\n";
2212 // -----------------------------------------------------------------------------
2213  }
2214 
2215  return true;
2216  },
2217  0,
2218  [] (BitArray & ba, Instruction & instr)
2219  {
2220 // -----------------------------------------------------------------------------
2221 
2222 // -----------------------------------------------------------------------------
2223 
2224  std::stringstream ss;
2225 // -----------------------------------------------------------------------------
2226 ss << "cebreak" << " # " << ba << (" []");
2227 // -----------------------------------------------------------------------------
2228  return ss.str();
2229  }
2230 );
2231 
2232 // CSWSP -----------------------------------------------------------------------
2233 static InstructionDefinition cswsp_rs2_uimm (
2234  ISA16_RV32IMACFD,
2235  "cswsp",
2236  (uint16_t) 0xc002,
2237  (uint16_t) 0xe003,
2238  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2239  {
2240 
2241 // -----------------------------------------------------------------------------
2242 
2243 // -----------------------------------------------------------------------------
2244 
2245 // -----------------------------------------------------------------------------
2246 etiss_uint8 rs2 = 0;
2247 static BitArrayRange R_rs2_0(6, 2);
2248 rs2 += R_rs2_0.read(ba) << 0;
2249 etiss_uint8 uimm = 0;
2250 static BitArrayRange R_uimm_6(8, 7);
2251 uimm += R_uimm_6.read(ba) << 6;
2252 static BitArrayRange R_uimm_2(12, 9);
2253 uimm += R_uimm_2.read(ba) << 2;
2254 
2255 // -----------------------------------------------------------------------------
2256 
2257  {
2258  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2259 
2260  cp.code() = std::string("//CSWSP\n");
2261 
2262 // -----------------------------------------------------------------------------
2263 { // block
2264 cp.code() += "{ // block\n";
2265 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
2266 cp.code() += "} // block\n";
2267 } // block
2268 { // block
2269 cp.code() += "{ // block\n";
2270 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
2271 cp.code() += "etiss_uint32 mem_val_0;\n";
2272 cp.code() += "mem_val_0 = (etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
2273 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
2274 cp.code() += "if (cpu->exception) { // conditional\n";
2275 { // procedure
2276 cp.code() += "{ // procedure\n";
2277 cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
2278 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
2279 cp.code() += "} // procedure\n";
2280 } // procedure
2281 cp.code() += "} // conditional\n";
2282 cp.code() += "} // block\n";
2283 } // block
2284 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2285 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2286 // -----------------------------------------------------------------------------
2287  cp.getAffectedRegisters().add("instructionPointer", 32);
2288  }
2289  {
2290  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
2291 
2292  cp.code() = std::string("//CSWSP\n");
2293 
2294 // -----------------------------------------------------------------------------
2295 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
2296 // -----------------------------------------------------------------------------
2297  }
2298 
2299  return true;
2300  },
2301  0,
2302  [] (BitArray & ba, Instruction & instr)
2303  {
2304 // -----------------------------------------------------------------------------
2305 etiss_uint8 rs2 = 0;
2306 static BitArrayRange R_rs2_0(6, 2);
2307 rs2 += R_rs2_0.read(ba) << 0;
2308 etiss_uint8 uimm = 0;
2309 static BitArrayRange R_uimm_6(8, 7);
2310 uimm += R_uimm_6.read(ba) << 6;
2311 static BitArrayRange R_uimm_2(12, 9);
2312 uimm += R_uimm_2.read(ba) << 2;
2313 
2314 // -----------------------------------------------------------------------------
2315 
2316  std::stringstream ss;
2317 // -----------------------------------------------------------------------------
2318 ss << "cswsp" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | uimm=" + std::to_string(uimm) + "]");
2319 // -----------------------------------------------------------------------------
2320  return ss.str();
2321  }
2322 );
2323 
2324 // DII -------------------------------------------------------------------------
2325 static InstructionDefinition dii_ (
2326  ISA16_RV32IMACFD,
2327  "dii",
2328  (uint16_t) 0x00,
2329  (uint16_t) 0xffff,
2330  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2331  {
2332 
2333 // -----------------------------------------------------------------------------
2334 
2335 // -----------------------------------------------------------------------------
2336 
2337 // -----------------------------------------------------------------------------
2338 
2339 // -----------------------------------------------------------------------------
2340 
2341  {
2342  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2343 
2344  cp.code() = std::string("//DII\n");
2345 
2346 // -----------------------------------------------------------------------------
2347 { // block
2348 cp.code() += "{ // block\n";
2349 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
2350 cp.code() += "} // block\n";
2351 } // block
2352 { // procedure
2353 cp.code() += "{ // procedure\n";
2354 cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";
2355 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
2356 cp.code() += "} // procedure\n";
2357 } // procedure
2358 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2359 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2360 // -----------------------------------------------------------------------------
2361  cp.getAffectedRegisters().add("instructionPointer", 32);
2362  }
2363  {
2364  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
2365 
2366  cp.code() = std::string("//DII\n");
2367 
2368 // -----------------------------------------------------------------------------
2369 cp.code() += "return cpu->exception;\n";
2370 // -----------------------------------------------------------------------------
2371  }
2372 
2373  return true;
2374  },
2375  0,
2376  [] (BitArray & ba, Instruction & instr)
2377  {
2378 // -----------------------------------------------------------------------------
2379 
2380 // -----------------------------------------------------------------------------
2381 
2382  std::stringstream ss;
2383 // -----------------------------------------------------------------------------
2384 ss << "dii" << " # " << ba << (" []");
2385 // -----------------------------------------------------------------------------
2386  return ss.str();
2387  }
2388 );
ISA16_RV32IMACFD
etiss::instr::InstructionGroup ISA16_RV32IMACFD("ISA16_RV32IMACFD", 16)
cj_imm
static InstructionDefinition cj_imm(ISA16_RV32IMACFD, "cj",(uint16_t) 0xa001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_5(2, 2);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_1(5, 3);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_7(6, 6);imm+=R_imm_7.read(ba)<< 7;static BitArrayRange R_imm_6(7, 7);imm+=R_imm_6.read(ba)<< 6;static BitArrayRange R_imm_10(8, 8);imm+=R_imm_10.read(ba)<< 10;static BitArrayRange R_imm_8(10, 9);imm+=R_imm_8.read(ba)<< 8;static BitArrayRange R_imm_4(11, 11);imm+=R_imm_4.read(ba)<< 4;static BitArrayRange R_imm_11(12, 12);imm+=R_imm_11.read(ba)<< 11;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CJ\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CJ\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_5(2, 2);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_1(5, 3);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_7(6, 6);imm+=R_imm_7.read(ba)<< 7;static BitArrayRange R_imm_6(7, 7);imm+=R_imm_6.read(ba)<< 6;static BitArrayRange R_imm_10(8, 8);imm+=R_imm_10.read(ba)<< 10;static BitArrayRange R_imm_8(10, 9);imm+=R_imm_8.read(ba)<< 8;static BitArrayRange R_imm_4(11, 11);imm+=R_imm_4.read(ba)<< 4;static BitArrayRange R_imm_11(12, 12);imm+=R_imm_11.read(ba)<< 11;std::stringstream ss;ss<< "cj"<< " # "<< ba<<(" [imm="+std::to_string(imm)+"]");return ss.str();})
dii_
static InstructionDefinition dii_(ISA16_RV32IMACFD, "dii",(uint16_t) 0x00,(uint16_t) 0xffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//DII\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//DII\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "dii"<< " # "<< ba<<(" []");return ss.str();})
cjr_rs1
static InstructionDefinition cjr_rs1(ISA16_RV32IMACFD, "cjr",(uint16_t) 0x8002,(uint16_t) 0xf07f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CJR\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} if(rs1) { cp.code()+="cpu->nextPc = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] & -2LL;\n";} else { { cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2ULL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} } cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CJR\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "cjr"<< " # "<< ba<<(" [rs1="+std::to_string(rs1)+"]");return ss.str();})
csrli_shamt_rs1
static InstructionDefinition csrli_shamt_rs1(ISA16_RV32IMACFD, "csrli",(uint16_t) 0x8001,(uint16_t) 0xfc03, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(6, 2);shamt+=R_shamt_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRLI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] >> "+std::to_string(shamt)+"ULL;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(6, 2);shamt+=R_shamt_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "csrli"<< " # "<< ba<<(" [shamt="+std::to_string(shamt)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
candi_imm_rs1
static InstructionDefinition candi_imm_rs1(ISA16_RV32IMACFD, "candi",(uint16_t) 0x8801,(uint16_t) 0xec03, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 imm=0;static BitArrayRange R_imm_0(6, 2);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_5(12, 12);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CANDI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] & "+std::to_string(((etiss_int8)(((etiss_int8) imm)<<(2)) >>(2)))+"LL;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 imm=0;static BitArrayRange R_imm_0(6, 2);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_5(12, 12);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "candi"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
caddi4spn_rd_imm
static InstructionDefinition caddi4spn_rd_imm(ISA16_RV32IMACFD, "caddi4spn",(uint16_t) 0x00,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_3(5, 5);imm+=R_imm_3.read(ba)<< 3;static BitArrayRange R_imm_2(6, 6);imm+=R_imm_2.read(ba)<< 2;static BitArrayRange R_imm_6(10, 7);imm+=R_imm_6.read(ba)<< 6;static BitArrayRange R_imm_4(12, 11);imm+=R_imm_4.read(ba)<< 4;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CADDI4SPN\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} if(imm) { cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = *((RV32IMACFD*)cpu)->X[2ULL] + "+std::to_string(imm)+"ULL;\n";} else { { cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} } cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CADDI4SPN\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_3(5, 5);imm+=R_imm_3.read(ba)<< 3;static BitArrayRange R_imm_2(6, 6);imm+=R_imm_2.read(ba)<< 2;static BitArrayRange R_imm_6(10, 7);imm+=R_imm_6.read(ba)<< 6;static BitArrayRange R_imm_4(12, 11);imm+=R_imm_4.read(ba)<< 4;std::stringstream ss;ss<< "caddi4spn"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | imm="+std::to_string(imm)+"]");return ss.str();})
cor_rs2_rd
static InstructionDefinition cor_rs2_rd(ISA16_RV32IMACFD, "cor",(uint16_t) 0x8c41,(uint16_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//COR\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] | *((RV32IMACFD*)cpu)->X["+std::to_string(rs2+8ULL)+"ULL];\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "cor"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | rd="+std::to_string(rd)+"]");return ss.str();})
__reserved_clui_rd
static InstructionDefinition __reserved_clui_rd(ISA16_RV32IMACFD, "__reserved_clui",(uint16_t) 0x6001,(uint16_t) 0xf07f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//__reserved_clui\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//__reserved_clui\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "__reserved_clui"<< " # "<< ba<<(" [rd="+std::to_string(rd)+"]");return ss.str();})
cjal_imm
static InstructionDefinition cjal_imm(ISA16_RV32IMACFD, "cjal",(uint16_t) 0x2001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_5(2, 2);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_1(5, 3);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_7(6, 6);imm+=R_imm_7.read(ba)<< 7;static BitArrayRange R_imm_6(7, 7);imm+=R_imm_6.read(ba)<< 6;static BitArrayRange R_imm_10(8, 8);imm+=R_imm_10.read(ba)<< 10;static BitArrayRange R_imm_8(10, 9);imm+=R_imm_8.read(ba)<< 8;static BitArrayRange R_imm_4(11, 11);imm+=R_imm_4.read(ba)<< 4;static BitArrayRange R_imm_11(12, 12);imm+=R_imm_11.read(ba)<< 11;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CJAL\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="*((RV32IMACFD*)cpu)->X[1ULL] = "+std::to_string(ic.current_address_+2ULL)+"ULL;\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CJAL\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_5(2, 2);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_1(5, 3);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_7(6, 6);imm+=R_imm_7.read(ba)<< 7;static BitArrayRange R_imm_6(7, 7);imm+=R_imm_6.read(ba)<< 6;static BitArrayRange R_imm_10(8, 8);imm+=R_imm_10.read(ba)<< 10;static BitArrayRange R_imm_8(10, 9);imm+=R_imm_8.read(ba)<< 8;static BitArrayRange R_imm_4(11, 11);imm+=R_imm_4.read(ba)<< 4;static BitArrayRange R_imm_11(12, 12);imm+=R_imm_11.read(ba)<< 11;std::stringstream ss;ss<< "cjal"<< " # "<< ba<<(" [imm="+std::to_string(imm)+"]");return ss.str();})
clwsp_uimm_rd
static InstructionDefinition clwsp_uimm_rd(ISA16_RV32IMACFD, "clwsp",(uint16_t) 0x4002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(3, 2);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 4);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_uimm_5(12, 12);uimm+=R_uimm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CLWSP\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if(rd % 32ULL) { { cp.code()+="{ // block\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, *((RV32IMACFD*)cpu)->X[2ULL] + "+std::to_string(uimm)+"ULL, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int32 res = mem_val_0;\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int32)(res);\n";cp.code()+="} // block\n";} } else { { cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2ULL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CLWSP\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(3, 2);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 4);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_uimm_5(12, 12);uimm+=R_uimm_5.read(ba)<< 5;std::stringstream ss;ss<< "clwsp"<< " # "<< ba<<(" [uimm="+std::to_string(uimm)+" | rd="+std::to_string(rd)+"]");return ss.str();})
cmv_rs2_rd
static InstructionDefinition cmv_rs2_rd(ISA16_RV32IMACFD, "cmv",(uint16_t) 0x8002,(uint16_t) 0xf003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CMV\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "cmv"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | rd="+std::to_string(rd)+"]");return ss.str();})
caddi_imm_rs1
static InstructionDefinition caddi_imm_rs1(ISA16_RV32IMACFD, "caddi",(uint16_t) 0x01,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 imm=0;static BitArrayRange R_imm_0(6, 2);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_5(12, 12);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CADDI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} if((rs1 % 32ULL) !=0LL) { cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int8)(((etiss_int8) imm)<<(2)) >>(2)))+"LL;\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 imm=0;static BitArrayRange R_imm_0(6, 2);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_5(12, 12);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "caddi"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
cebreak_
static InstructionDefinition cebreak_(ISA16_RV32IMACFD, "cebreak",(uint16_t) 0x9002,(uint16_t) 0xffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CEBREAK\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 3LL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CEBREAK\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "cebreak"<< " # "<< ba<<(" []");return ss.str();})
cli_imm_rd
static InstructionDefinition cli_imm_rd(ISA16_RV32IMACFD, "cli",(uint16_t) 0x4001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 imm=0;static BitArrayRange R_imm_0(6, 2);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_imm_5(12, 12);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CLI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string(((etiss_int8)(((etiss_int8) imm)<<(2)) >>(2)))+"LL;\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 imm=0;static BitArrayRange R_imm_0(6, 2);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_imm_5(12, 12);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "cli"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rd="+std::to_string(rd)+"]");return ss.str();})
cxor_rs2_rd
static InstructionDefinition cxor_rs2_rd(ISA16_RV32IMACFD, "cxor",(uint16_t) 0x8c21,(uint16_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CXOR\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] ^ *((RV32IMACFD*)cpu)->X["+std::to_string(rs2+8ULL)+"ULL];\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "cxor"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | rd="+std::to_string(rd)+"]");return ss.str();})
csrai_shamt_rs1
static InstructionDefinition csrai_shamt_rs1(ISA16_RV32IMACFD, "csrai",(uint16_t) 0x8401,(uint16_t) 0xfc03, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(6, 2);shamt+=R_shamt_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRAI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if(shamt) { { cp.code()+="{ // block\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] = ((etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL])) >> "+std::to_string(shamt)+"ULL;\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(6, 2);shamt+=R_shamt_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "csrai"<< " # "<< ba<<(" [shamt="+std::to_string(shamt)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
csub_rs2_rd
static InstructionDefinition csub_rs2_rd(ISA16_RV32IMACFD, "csub",(uint16_t) 0x8c01,(uint16_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSUB\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] - *((RV32IMACFD*)cpu)->X["+std::to_string(rs2+8ULL)+"ULL];\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "csub"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | rd="+std::to_string(rd)+"]");return ss.str();})
cbnez_imm_rs1
static InstructionDefinition cbnez_imm_rs1(ISA16_RV32IMACFD, "cbnez",(uint16_t) 0xe001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_5(2, 2);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_1(4, 3);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_6(6, 5);imm+=R_imm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_3(11, 10);imm+=R_imm_3.read(ba)<< 3;static BitArrayRange R_imm_8(12, 12);imm+=R_imm_8.read(ba)<< 8;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CBNEZ\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} cp.code()+="if (*((RV32IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(7)) >>(7)))+"LL;\n";cp.code()+="} // conditional\n";cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CBNEZ\n");cp.code()+="if (cpu->nextPc != "+std::to_string(ic.current_address_+2)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_5(2, 2);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_1(4, 3);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_6(6, 5);imm+=R_imm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_3(11, 10);imm+=R_imm_3.read(ba)<< 3;static BitArrayRange R_imm_8(12, 12);imm+=R_imm_8.read(ba)<< 8;std::stringstream ss;ss<< "cbnez"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
cnop_nzimm
static InstructionDefinition cnop_nzimm(ISA16_RV32IMACFD, "cnop",(uint16_t) 0x01,(uint16_t) 0xef83, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 nzimm=0;static BitArrayRange R_nzimm_0(6, 2);nzimm+=R_nzimm_0.read(ba)<< 0;static BitArrayRange R_nzimm_5(12, 12);nzimm+=R_nzimm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CNOP\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 nzimm=0;static BitArrayRange R_nzimm_0(6, 2);nzimm+=R_nzimm_0.read(ba)<< 0;static BitArrayRange R_nzimm_5(12, 12);nzimm+=R_nzimm_5.read(ba)<< 5;std::stringstream ss;ss<< "cnop"<< " # "<< ba<<(" [nzimm="+std::to_string(nzimm)+"]");return ss.str();})
cadd_rs2_rd
static InstructionDefinition cadd_rs2_rd(ISA16_RV32IMACFD, "cadd",(uint16_t) 0x9002,(uint16_t) 0xf003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CADD\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] + *((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "cadd"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | rd="+std::to_string(rd)+"]");return ss.str();})
caddi16sp_nzimm
static InstructionDefinition caddi16sp_nzimm(ISA16_RV32IMACFD, "caddi16sp",(uint16_t) 0x6101,(uint16_t) 0xef83, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 nzimm=0;static BitArrayRange R_nzimm_5(2, 2);nzimm+=R_nzimm_5.read(ba)<< 5;static BitArrayRange R_nzimm_7(4, 3);nzimm+=R_nzimm_7.read(ba)<< 7;static BitArrayRange R_nzimm_6(5, 5);nzimm+=R_nzimm_6.read(ba)<< 6;static BitArrayRange R_nzimm_4(6, 6);nzimm+=R_nzimm_4.read(ba)<< 4;static BitArrayRange R_nzimm_9(12, 12);nzimm+=R_nzimm_9.read(ba)<< 9;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CADDI16SP\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} if(nzimm) { cp.code()+="*((RV32IMACFD*)cpu)->X[2ULL] = *((RV32IMACFD*)cpu)->X[2ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) nzimm)<<(6)) >>(6)))+"LL;\n";} else { { cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} } cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CADDI16SP\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 nzimm=0;static BitArrayRange R_nzimm_5(2, 2);nzimm+=R_nzimm_5.read(ba)<< 5;static BitArrayRange R_nzimm_7(4, 3);nzimm+=R_nzimm_7.read(ba)<< 7;static BitArrayRange R_nzimm_6(5, 5);nzimm+=R_nzimm_6.read(ba)<< 6;static BitArrayRange R_nzimm_4(6, 6);nzimm+=R_nzimm_4.read(ba)<< 4;static BitArrayRange R_nzimm_9(12, 12);nzimm+=R_nzimm_9.read(ba)<< 9;std::stringstream ss;ss<< "caddi16sp"<< " # "<< ba<<(" [nzimm="+std::to_string(nzimm)+"]");return ss.str();})
cswsp_rs2_uimm
static InstructionDefinition cswsp_rs2_uimm(ISA16_RV32IMACFD, "cswsp",(uint16_t) 0xc002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(8, 7);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(12, 9);uimm+=R_uimm_2.read(ba)<< 2;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSWSP\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_uint32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CSWSP\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(8, 7);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(12, 9);uimm+=R_uimm_2.read(ba)<< 2;std::stringstream ss;ss<< "cswsp"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | uimm="+std::to_string(uimm)+"]");return ss.str();})
clw_rd_uimm_rs1
static InstructionDefinition clw_rd_uimm_rs1(ISA16_RV32IMACFD, "clw",(uint16_t) 0x4000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(5, 5);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 6);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CLW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = (etiss_int32)(mem_val_0);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CLW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(5, 5);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 6);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;std::stringstream ss;ss<< "clw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | uimm="+std::to_string(uimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
cjalr_rs1
static InstructionDefinition cjalr_rs1(ISA16_RV32IMACFD, "cjalr",(uint16_t) 0x9002,(uint16_t) 0xf07f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CJALR\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint32 new_pc = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="*((RV32IMACFD*)cpu)->X[1ULL] = "+std::to_string(ic.current_address_+2ULL)+"ULL;\n";cp.code()+="cpu->nextPc = new_pc & -2LL;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CJALR\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "cjalr"<< " # "<< ba<<(" [rs1="+std::to_string(rs1)+"]");return ss.str();})
__reserved_cmv_
static InstructionDefinition __reserved_cmv_(ISA16_RV32IMACFD, "__reserved_cmv",(uint16_t) 0x8002,(uint16_t) 0xffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//__reserved_cmv\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2ULL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//__reserved_cmv\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "__reserved_cmv"<< " # "<< ba<<(" []");return ss.str();})
cbeqz_imm_rs1
static InstructionDefinition cbeqz_imm_rs1(ISA16_RV32IMACFD, "cbeqz",(uint16_t) 0xc001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_5(2, 2);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_1(4, 3);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_6(6, 5);imm+=R_imm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_3(11, 10);imm+=R_imm_3.read(ba)<< 3;static BitArrayRange R_imm_8(12, 12);imm+=R_imm_8.read(ba)<< 8;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CBEQZ\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} cp.code()+="if (*((RV32IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] == 0LL) { // conditional\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(7)) >>(7)))+"LL;\n";cp.code()+="} // conditional\n";cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CBEQZ\n");cp.code()+="if (cpu->nextPc != "+std::to_string(ic.current_address_+2)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_5(2, 2);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_1(4, 3);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_6(6, 5);imm+=R_imm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_3(11, 10);imm+=R_imm_3.read(ba)<< 3;static BitArrayRange R_imm_8(12, 12);imm+=R_imm_8.read(ba)<< 8;std::stringstream ss;ss<< "cbeqz"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
clui_imm_rd
static InstructionDefinition clui_imm_rd(ISA16_RV32IMACFD, "clui",(uint16_t) 0x6001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint32 imm=0;static BitArrayRange R_imm_12(6, 2);imm+=R_imm_12.read(ba)<< 12;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_imm_17(12, 12);imm+=R_imm_17.read(ba)<< 17;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CLUI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if(imm==0LL) { { cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} } if((rd % 32ULL) !=0LL) { cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string(((etiss_int32)(((etiss_int32) imm)<<(14)) >>(14)))+"LL;\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CLUI\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint32 imm=0;static BitArrayRange R_imm_12(6, 2);imm+=R_imm_12.read(ba)<< 12;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_imm_17(12, 12);imm+=R_imm_17.read(ba)<< 17;std::stringstream ss;ss<< "clui"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rd="+std::to_string(rd)+"]");return ss.str();})
cand_rs2_rd
static InstructionDefinition cand_rs2_rd(ISA16_RV32IMACFD, "cand",(uint16_t) 0x8c61,(uint16_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CAND\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] & *((RV32IMACFD*)cpu)->X["+std::to_string(rs2+8ULL)+"ULL];\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "cand"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | rd="+std::to_string(rd)+"]");return ss.str();})
cslli_nzuimm_rs1
static InstructionDefinition cslli_nzuimm_rs1(ISA16_RV32IMACFD, "cslli",(uint16_t) 0x02,(uint16_t) 0xf003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 nzuimm=0;static BitArrayRange R_nzuimm_0(6, 2);nzuimm+=R_nzuimm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSLLI\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} if(nzuimm) { cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] << "+std::to_string(nzuimm)+"ULL;\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 nzuimm=0;static BitArrayRange R_nzuimm_0(6, 2);nzuimm+=R_nzuimm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "cslli"<< " # "<< ba<<(" [nzuimm="+std::to_string(nzuimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
csw_rs2_uimm_rs1
static InstructionDefinition csw_rs2_uimm_rs1(ISA16_RV32IMACFD, "csw",(uint16_t) 0xc000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(5, 5);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 6);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2+8ULL)+"ULL]);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CSW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(5, 5);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 6);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;std::stringstream ss;ss<< "csw"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | uimm="+std::to_string(uimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
uint16_t
static __inline__ uint16_t
Definition: arm_mve.h:315
etiss_int16
int16_t etiss_int16
Definition: types.h:89
etiss_uint32
uint32_t etiss_uint32
Definition: types.h:93
etiss_int8
int8_t etiss_int8
Definition: types.h:86
etiss_uint8
uint8_t etiss_uint8
Definition: types.h:87
etiss_int32
int32_t etiss_int32
Definition: types.h:92
etiss_uint16
uint16_t etiss_uint16
Definition: types.h:90
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:386
etiss::CodePart::APPENDEDRETURNINGREQUIRED
@ APPENDEDRETURNINGREQUIRED
Definition: CodePart.h:402
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition: Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition: Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
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