ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
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RV32IMACFD_RV32ICInstr.cpp
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1
8#include "RV32IMACFDArch.h"
9#include "RV32IMACFDFuncs.h"
10
11using namespace etiss;
12using namespace etiss::instr;
13
14
15// CADDI4SPN -------------------------------------------------------------------
16static InstructionDefinition caddi4spn_rd_imm (
17 ISA16_RV32IMACFD,
18 "caddi4spn",
19 (uint16_t) 0x00,
20 (uint16_t) 0xe003,
21 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22 {
23
24// -----------------------------------------------------------------------------
25
26// -----------------------------------------------------------------------------
27
28// -----------------------------------------------------------------------------
29etiss_uint8 rd = 0;
30static BitArrayRange R_rd_0(4, 2);
31rd += R_rd_0.read(ba) << 0;
32etiss_uint16 imm = 0;
33static BitArrayRange R_imm_3(5, 5);
34imm += R_imm_3.read(ba) << 3;
35static BitArrayRange R_imm_2(6, 6);
36imm += R_imm_2.read(ba) << 2;
37static BitArrayRange R_imm_6(10, 7);
38imm += R_imm_6.read(ba) << 6;
39static BitArrayRange R_imm_4(12, 11);
40imm += R_imm_4.read(ba) << 4;
41
42// -----------------------------------------------------------------------------
43
44 {
45 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
46
47 cp.code() = std::string("//CADDI4SPN\n");
48
49// -----------------------------------------------------------------------------
50cp.code() += "etiss_coverage_count(1, 42);\n";
51{ // block
52cp.code() += "etiss_coverage_count(1, 1169);\n";
53cp.code() += "{ // block\n";
54cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
55cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
56cp.code() += "} // block\n";
57} // block
58cp.code() += "etiss_coverage_count(1, 2327);\n";
59if (imm) { // conditional
60cp.code() += "etiss_coverage_count(1, 2328);\n";
61cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(imm) + "ULL;\n";
62cp.code() += "etiss_coverage_count(9, 2339, 2333, 2332, 2330, 2331, 2338, 2336, 2335, 2337);\n";
63} // conditional
64else { // conditional
65{ // procedure
66cp.code() += "{ // procedure\n";
67cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";
68cp.code() += "etiss_coverage_count(2, 2342, 2340);\n";
69cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
70cp.code() += "} // procedure\n";
71} // procedure
72} // conditional
73cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
74cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
75// -----------------------------------------------------------------------------
76 cp.getAffectedRegisters().add("instructionPointer", 32);
77 }
78 {
79 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
80
81 cp.code() = std::string("//CADDI4SPN\n");
82
83// -----------------------------------------------------------------------------
84cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
85// -----------------------------------------------------------------------------
86 }
87
88 return true;
89 },
90 0,
91 [] (BitArray & ba, Instruction & instr)
92 {
93// -----------------------------------------------------------------------------
94etiss_uint8 rd = 0;
95static BitArrayRange R_rd_0(4, 2);
96rd += R_rd_0.read(ba) << 0;
97etiss_uint16 imm = 0;
98static BitArrayRange R_imm_3(5, 5);
99imm += R_imm_3.read(ba) << 3;
100static BitArrayRange R_imm_2(6, 6);
101imm += R_imm_2.read(ba) << 2;
102static BitArrayRange R_imm_6(10, 7);
103imm += R_imm_6.read(ba) << 6;
104static BitArrayRange R_imm_4(12, 11);
105imm += R_imm_4.read(ba) << 4;
106
107// -----------------------------------------------------------------------------
108
109 std::stringstream ss;
110// -----------------------------------------------------------------------------
111ss << "caddi4spn" << " # " << ba << (" [rd=" + std::to_string(rd) + " | imm=" + std::to_string(imm) + "]");
112// -----------------------------------------------------------------------------
113 return ss.str();
114 }
115);
116
117// CLW -------------------------------------------------------------------------
118static InstructionDefinition clw_rd_uimm_rs1 (
119 ISA16_RV32IMACFD,
120 "clw",
121 (uint16_t) 0x4000,
122 (uint16_t) 0xe003,
123 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
124 {
125
126// -----------------------------------------------------------------------------
127
128// -----------------------------------------------------------------------------
129
130// -----------------------------------------------------------------------------
131etiss_uint8 rd = 0;
132static BitArrayRange R_rd_0(4, 2);
133rd += R_rd_0.read(ba) << 0;
134etiss_uint8 uimm = 0;
135static BitArrayRange R_uimm_6(5, 5);
136uimm += R_uimm_6.read(ba) << 6;
137static BitArrayRange R_uimm_2(6, 6);
138uimm += R_uimm_2.read(ba) << 2;
139etiss_uint8 rs1 = 0;
140static BitArrayRange R_rs1_0(9, 7);
141rs1 += R_rs1_0.read(ba) << 0;
142static BitArrayRange R_uimm_3(12, 10);
143uimm += R_uimm_3.read(ba) << 3;
144
145// -----------------------------------------------------------------------------
146
147 {
148 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
149
150 cp.code() = std::string("//CLW\n");
151
152// -----------------------------------------------------------------------------
153cp.code() += "etiss_coverage_count(1, 43);\n";
154{ // block
155cp.code() += "etiss_coverage_count(1, 1169);\n";
156cp.code() += "{ // block\n";
157cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
158cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
159cp.code() += "} // block\n";
160} // block
161{ // block
162cp.code() += "etiss_coverage_count(1, 2363);\n";
163cp.code() += "{ // block\n";
164cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
165cp.code() += "etiss_coverage_count(7, 2351, 2350, 2348, 2347, 2345, 2346, 2349);\n";
166cp.code() += "etiss_uint32 mem_val_0;\n";
167cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
168cp.code() += "if (cpu->exception) { // conditional\n";
169{ // procedure
170cp.code() += "{ // procedure\n";
171cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
172cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
173cp.code() += "} // procedure\n";
174} // procedure
175cp.code() += "} // conditional\n";
176cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = (etiss_int32)(mem_val_0);\n";
177cp.code() += "etiss_coverage_count(8, 2362, 2356, 2355, 2353, 2354, 2361, 2359, 2358);\n";
178cp.code() += "} // block\n";
179} // block
180cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
181cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
182// -----------------------------------------------------------------------------
183 cp.getAffectedRegisters().add("instructionPointer", 32);
184 }
185 {
186 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
187
188 cp.code() = std::string("//CLW\n");
189
190// -----------------------------------------------------------------------------
191cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
192// -----------------------------------------------------------------------------
193 }
194
195 return true;
196 },
197 0,
198 [] (BitArray & ba, Instruction & instr)
199 {
200// -----------------------------------------------------------------------------
201etiss_uint8 rd = 0;
202static BitArrayRange R_rd_0(4, 2);
203rd += R_rd_0.read(ba) << 0;
204etiss_uint8 uimm = 0;
205static BitArrayRange R_uimm_6(5, 5);
206uimm += R_uimm_6.read(ba) << 6;
207static BitArrayRange R_uimm_2(6, 6);
208uimm += R_uimm_2.read(ba) << 2;
209etiss_uint8 rs1 = 0;
210static BitArrayRange R_rs1_0(9, 7);
211rs1 += R_rs1_0.read(ba) << 0;
212static BitArrayRange R_uimm_3(12, 10);
213uimm += R_uimm_3.read(ba) << 3;
214
215// -----------------------------------------------------------------------------
216
217 std::stringstream ss;
218// -----------------------------------------------------------------------------
219ss << "clw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | uimm=" + std::to_string(uimm) + " | rs1=" + std::to_string(rs1) + "]");
220// -----------------------------------------------------------------------------
221 return ss.str();
222 }
223);
224
225// CSW -------------------------------------------------------------------------
226static InstructionDefinition csw_rs2_uimm_rs1 (
227 ISA16_RV32IMACFD,
228 "csw",
229 (uint16_t) 0xc000,
230 (uint16_t) 0xe003,
231 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
232 {
233
234// -----------------------------------------------------------------------------
235
236// -----------------------------------------------------------------------------
237
238// -----------------------------------------------------------------------------
239etiss_uint8 rs2 = 0;
240static BitArrayRange R_rs2_0(4, 2);
241rs2 += R_rs2_0.read(ba) << 0;
242etiss_uint8 uimm = 0;
243static BitArrayRange R_uimm_6(5, 5);
244uimm += R_uimm_6.read(ba) << 6;
245static BitArrayRange R_uimm_2(6, 6);
246uimm += R_uimm_2.read(ba) << 2;
247etiss_uint8 rs1 = 0;
248static BitArrayRange R_rs1_0(9, 7);
249rs1 += R_rs1_0.read(ba) << 0;
250static BitArrayRange R_uimm_3(12, 10);
251uimm += R_uimm_3.read(ba) << 3;
252
253// -----------------------------------------------------------------------------
254
255 {
256 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
257
258 cp.code() = std::string("//CSW\n");
259
260// -----------------------------------------------------------------------------
261cp.code() += "etiss_coverage_count(1, 44);\n";
262{ // block
263cp.code() += "etiss_coverage_count(1, 1169);\n";
264cp.code() += "{ // block\n";
265cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
266cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
267cp.code() += "} // block\n";
268} // block
269{ // block
270cp.code() += "etiss_coverage_count(1, 2384);\n";
271cp.code() += "{ // block\n";
272cp.code() += "etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
273cp.code() += "etiss_coverage_count(7, 2372, 2371, 2369, 2368, 2366, 2367, 2370);\n";
274cp.code() += "etiss_uint32 mem_val_0;\n";
275cp.code() += "mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL]);\n";
276cp.code() += "etiss_coverage_count(8, 2383, 2375, 2374, 2382, 2380, 2379, 2377, 2378);\n";
277cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";
278cp.code() += "if (cpu->exception) { // conditional\n";
279{ // procedure
280cp.code() += "{ // procedure\n";
281cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
282cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
283cp.code() += "} // procedure\n";
284} // procedure
285cp.code() += "} // conditional\n";
286cp.code() += "} // block\n";
287} // block
288cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
289cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
290// -----------------------------------------------------------------------------
291 cp.getAffectedRegisters().add("instructionPointer", 32);
292 }
293 {
294 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
295
296 cp.code() = std::string("//CSW\n");
297
298// -----------------------------------------------------------------------------
299cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
300// -----------------------------------------------------------------------------
301 }
302
303 return true;
304 },
305 0,
306 [] (BitArray & ba, Instruction & instr)
307 {
308// -----------------------------------------------------------------------------
309etiss_uint8 rs2 = 0;
310static BitArrayRange R_rs2_0(4, 2);
311rs2 += R_rs2_0.read(ba) << 0;
312etiss_uint8 uimm = 0;
313static BitArrayRange R_uimm_6(5, 5);
314uimm += R_uimm_6.read(ba) << 6;
315static BitArrayRange R_uimm_2(6, 6);
316uimm += R_uimm_2.read(ba) << 2;
317etiss_uint8 rs1 = 0;
318static BitArrayRange R_rs1_0(9, 7);
319rs1 += R_rs1_0.read(ba) << 0;
320static BitArrayRange R_uimm_3(12, 10);
321uimm += R_uimm_3.read(ba) << 3;
322
323// -----------------------------------------------------------------------------
324
325 std::stringstream ss;
326// -----------------------------------------------------------------------------
327ss << "csw" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | uimm=" + std::to_string(uimm) + " | rs1=" + std::to_string(rs1) + "]");
328// -----------------------------------------------------------------------------
329 return ss.str();
330 }
331);
332
333// CADDI -----------------------------------------------------------------------
334static InstructionDefinition caddi_imm_rs1 (
335 ISA16_RV32IMACFD,
336 "caddi",
337 (uint16_t) 0x01,
338 (uint16_t) 0xe003,
339 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
340 {
341
342// -----------------------------------------------------------------------------
343
344// -----------------------------------------------------------------------------
345
346// -----------------------------------------------------------------------------
347etiss_uint8 imm = 0;
348static BitArrayRange R_imm_0(6, 2);
349imm += R_imm_0.read(ba) << 0;
350etiss_uint8 rs1 = 0;
351static BitArrayRange R_rs1_0(11, 7);
352rs1 += R_rs1_0.read(ba) << 0;
353static BitArrayRange R_imm_5(12, 12);
354imm += R_imm_5.read(ba) << 5;
355
356// -----------------------------------------------------------------------------
357
358 {
359 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
360
361 cp.code() = std::string("//CADDI\n");
362
363// -----------------------------------------------------------------------------
364cp.code() += "etiss_coverage_count(1, 45);\n";
365{ // block
366cp.code() += "etiss_coverage_count(1, 1169);\n";
367cp.code() += "{ // block\n";
368cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
369cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
370cp.code() += "} // block\n";
371} // block
372cp.code() += "etiss_coverage_count(1, 2385);\n";
373if ((rs1 % 32ULL) != 0LL) { // conditional
374cp.code() += "etiss_coverage_count(5, 2391, 2388, 2386, 2389, 2390);\n";
375cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int8)(((etiss_int8)imm) << (2)) >> (2))) + "LL;\n";
376cp.code() += "etiss_coverage_count(10, 2406, 2396, 2395, 2393, 2405, 2401, 2400, 2398, 2404, 2402);\n";
377} // conditional
378cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
379cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
380// -----------------------------------------------------------------------------
381 cp.getAffectedRegisters().add("instructionPointer", 32);
382 }
383
384 return true;
385 },
386 0,
387 [] (BitArray & ba, Instruction & instr)
388 {
389// -----------------------------------------------------------------------------
390etiss_uint8 imm = 0;
391static BitArrayRange R_imm_0(6, 2);
392imm += R_imm_0.read(ba) << 0;
393etiss_uint8 rs1 = 0;
394static BitArrayRange R_rs1_0(11, 7);
395rs1 += R_rs1_0.read(ba) << 0;
396static BitArrayRange R_imm_5(12, 12);
397imm += R_imm_5.read(ba) << 5;
398
399// -----------------------------------------------------------------------------
400
401 std::stringstream ss;
402// -----------------------------------------------------------------------------
403ss << "caddi" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + "]");
404// -----------------------------------------------------------------------------
405 return ss.str();
406 }
407);
408
409// CNOP ------------------------------------------------------------------------
410static InstructionDefinition cnop_nzimm (
411 ISA16_RV32IMACFD,
412 "cnop",
413 (uint16_t) 0x01,
414 (uint16_t) 0xef83,
415 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
416 {
417
418// -----------------------------------------------------------------------------
419
420// -----------------------------------------------------------------------------
421
422// -----------------------------------------------------------------------------
423etiss_uint8 nzimm = 0;
424static BitArrayRange R_nzimm_0(6, 2);
425nzimm += R_nzimm_0.read(ba) << 0;
426static BitArrayRange R_nzimm_5(12, 12);
427nzimm += R_nzimm_5.read(ba) << 5;
428
429// -----------------------------------------------------------------------------
430
431 {
432 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
433
434 cp.code() = std::string("//CNOP\n");
435
436// -----------------------------------------------------------------------------
437cp.code() += "etiss_coverage_count(1, 46);\n";
438{ // block
439cp.code() += "etiss_coverage_count(1, 1169);\n";
440cp.code() += "{ // block\n";
441cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
442cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
443cp.code() += "} // block\n";
444} // block
445{ // block
446cp.code() += "etiss_coverage_count(1, 2407);\n";
447cp.code() += "{ // block\n";
448cp.code() += "} // block\n";
449} // block
450cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
451cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
452// -----------------------------------------------------------------------------
453 cp.getAffectedRegisters().add("instructionPointer", 32);
454 }
455
456 return true;
457 },
458 0,
459 [] (BitArray & ba, Instruction & instr)
460 {
461// -----------------------------------------------------------------------------
462etiss_uint8 nzimm = 0;
463static BitArrayRange R_nzimm_0(6, 2);
464nzimm += R_nzimm_0.read(ba) << 0;
465static BitArrayRange R_nzimm_5(12, 12);
466nzimm += R_nzimm_5.read(ba) << 5;
467
468// -----------------------------------------------------------------------------
469
470 std::stringstream ss;
471// -----------------------------------------------------------------------------
472ss << "cnop" << " # " << ba << (" [nzimm=" + std::to_string(nzimm) + "]");
473// -----------------------------------------------------------------------------
474 return ss.str();
475 }
476);
477
478// CJAL ------------------------------------------------------------------------
479static InstructionDefinition cjal_imm (
480 ISA16_RV32IMACFD,
481 "cjal",
482 (uint16_t) 0x2001,
483 (uint16_t) 0xe003,
484 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
485 {
486
487// -----------------------------------------------------------------------------
488
489// -----------------------------------------------------------------------------
490
491// -----------------------------------------------------------------------------
492etiss_uint16 imm = 0;
493static BitArrayRange R_imm_5(2, 2);
494imm += R_imm_5.read(ba) << 5;
495static BitArrayRange R_imm_1(5, 3);
496imm += R_imm_1.read(ba) << 1;
497static BitArrayRange R_imm_7(6, 6);
498imm += R_imm_7.read(ba) << 7;
499static BitArrayRange R_imm_6(7, 7);
500imm += R_imm_6.read(ba) << 6;
501static BitArrayRange R_imm_10(8, 8);
502imm += R_imm_10.read(ba) << 10;
503static BitArrayRange R_imm_8(10, 9);
504imm += R_imm_8.read(ba) << 8;
505static BitArrayRange R_imm_4(11, 11);
506imm += R_imm_4.read(ba) << 4;
507static BitArrayRange R_imm_11(12, 12);
508imm += R_imm_11.read(ba) << 11;
509
510// -----------------------------------------------------------------------------
511
512 {
513 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
514
515 cp.code() = std::string("//CJAL\n");
516
517// -----------------------------------------------------------------------------
518cp.code() += "etiss_coverage_count(1, 47);\n";
519{ // block
520cp.code() += "etiss_coverage_count(1, 1169);\n";
521cp.code() += "{ // block\n";
522cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
523cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
524cp.code() += "} // block\n";
525} // block
526{ // block
527cp.code() += "etiss_coverage_count(1, 2422);\n";
528cp.code() += "{ // block\n";
529cp.code() += "*((RV32IMACFD*)cpu)->X[1ULL] = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
530cp.code() += "etiss_coverage_count(6, 2414, 2410, 2409, 2413, 2411, 2412);\n";
531cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
532cp.code() += "etiss_coverage_count(6, 2421, 2415, 2420, 2416, 2419, 2417);\n";
533cp.code() += "} // block\n";
534} // block
535cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
536cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
537// -----------------------------------------------------------------------------
538 cp.getAffectedRegisters().add("instructionPointer", 32);
539 }
540 {
541 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
542
543 cp.code() = std::string("//CJAL\n");
544
545// -----------------------------------------------------------------------------
546cp.code() += "return cpu->exception;\n";
547// -----------------------------------------------------------------------------
548 }
549
550 return true;
551 },
552 0,
553 [] (BitArray & ba, Instruction & instr)
554 {
555// -----------------------------------------------------------------------------
556etiss_uint16 imm = 0;
557static BitArrayRange R_imm_5(2, 2);
558imm += R_imm_5.read(ba) << 5;
559static BitArrayRange R_imm_1(5, 3);
560imm += R_imm_1.read(ba) << 1;
561static BitArrayRange R_imm_7(6, 6);
562imm += R_imm_7.read(ba) << 7;
563static BitArrayRange R_imm_6(7, 7);
564imm += R_imm_6.read(ba) << 6;
565static BitArrayRange R_imm_10(8, 8);
566imm += R_imm_10.read(ba) << 10;
567static BitArrayRange R_imm_8(10, 9);
568imm += R_imm_8.read(ba) << 8;
569static BitArrayRange R_imm_4(11, 11);
570imm += R_imm_4.read(ba) << 4;
571static BitArrayRange R_imm_11(12, 12);
572imm += R_imm_11.read(ba) << 11;
573
574// -----------------------------------------------------------------------------
575
576 std::stringstream ss;
577// -----------------------------------------------------------------------------
578ss << "cjal" << " # " << ba << (" [imm=" + std::to_string(imm) + "]");
579// -----------------------------------------------------------------------------
580 return ss.str();
581 }
582);
583
584// CLI -------------------------------------------------------------------------
585static InstructionDefinition cli_imm_rd (
586 ISA16_RV32IMACFD,
587 "cli",
588 (uint16_t) 0x4001,
589 (uint16_t) 0xe003,
590 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
591 {
592
593// -----------------------------------------------------------------------------
594
595// -----------------------------------------------------------------------------
596
597// -----------------------------------------------------------------------------
598etiss_uint8 imm = 0;
599static BitArrayRange R_imm_0(6, 2);
600imm += R_imm_0.read(ba) << 0;
601etiss_uint8 rd = 0;
602static BitArrayRange R_rd_0(11, 7);
603rd += R_rd_0.read(ba) << 0;
604static BitArrayRange R_imm_5(12, 12);
605imm += R_imm_5.read(ba) << 5;
606
607// -----------------------------------------------------------------------------
608
609 {
610 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
611
612 cp.code() = std::string("//CLI\n");
613
614// -----------------------------------------------------------------------------
615cp.code() += "etiss_coverage_count(1, 48);\n";
616{ // block
617cp.code() += "etiss_coverage_count(1, 1169);\n";
618cp.code() += "{ // block\n";
619cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
620cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
621cp.code() += "} // block\n";
622} // block
623{ // block
624cp.code() += "etiss_coverage_count(1, 2439);\n";
625cp.code() += "{ // block\n";
626cp.code() += "etiss_coverage_count(1, 2423);\n";
627if ((rd % 32ULL) != 0LL) { // conditional
628cp.code() += "etiss_coverage_count(5, 2429, 2426, 2424, 2427, 2428);\n";
629cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(((etiss_int8)(((etiss_int8)imm) << (2)) >> (2))) + "LL;\n";
630cp.code() += "etiss_coverage_count(6, 2438, 2434, 2433, 2431, 2437, 2435);\n";
631} // conditional
632cp.code() += "} // block\n";
633} // block
634cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
635cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
636// -----------------------------------------------------------------------------
637 cp.getAffectedRegisters().add("instructionPointer", 32);
638 }
639
640 return true;
641 },
642 0,
643 [] (BitArray & ba, Instruction & instr)
644 {
645// -----------------------------------------------------------------------------
646etiss_uint8 imm = 0;
647static BitArrayRange R_imm_0(6, 2);
648imm += R_imm_0.read(ba) << 0;
649etiss_uint8 rd = 0;
650static BitArrayRange R_rd_0(11, 7);
651rd += R_rd_0.read(ba) << 0;
652static BitArrayRange R_imm_5(12, 12);
653imm += R_imm_5.read(ba) << 5;
654
655// -----------------------------------------------------------------------------
656
657 std::stringstream ss;
658// -----------------------------------------------------------------------------
659ss << "cli" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rd=" + std::to_string(rd) + "]");
660// -----------------------------------------------------------------------------
661 return ss.str();
662 }
663);
664
665// CLUI ------------------------------------------------------------------------
666static InstructionDefinition clui_imm_rd (
667 ISA16_RV32IMACFD,
668 "clui",
669 (uint16_t) 0x6001,
670 (uint16_t) 0xe003,
671 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
672 {
673
674// -----------------------------------------------------------------------------
675
676// -----------------------------------------------------------------------------
677
678// -----------------------------------------------------------------------------
679etiss_uint32 imm = 0;
680static BitArrayRange R_imm_12(6, 2);
681imm += R_imm_12.read(ba) << 12;
682etiss_uint8 rd = 0;
683static BitArrayRange R_rd_0(11, 7);
684rd += R_rd_0.read(ba) << 0;
685static BitArrayRange R_imm_17(12, 12);
686imm += R_imm_17.read(ba) << 17;
687
688// -----------------------------------------------------------------------------
689
690 {
691 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
692
693 cp.code() = std::string("//CLUI\n");
694
695// -----------------------------------------------------------------------------
696cp.code() += "etiss_coverage_count(1, 49);\n";
697{ // block
698cp.code() += "etiss_coverage_count(1, 1169);\n";
699cp.code() += "{ // block\n";
700cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
701cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
702cp.code() += "} // block\n";
703} // block
704{ // block
705cp.code() += "etiss_coverage_count(1, 2463);\n";
706cp.code() += "{ // block\n";
707cp.code() += "etiss_coverage_count(1, 2440);\n";
708if (imm == 0LL) { // conditional
709cp.code() += "etiss_coverage_count(3, 2443, 2441, 2442);\n";
710{ // procedure
711cp.code() += "{ // procedure\n";
712cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";
713cp.code() += "etiss_coverage_count(2, 2446, 2444);\n";
714cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
715cp.code() += "} // procedure\n";
716} // procedure
717} // conditional
718cp.code() += "etiss_coverage_count(1, 2447);\n";
719if ((rd % 32ULL) != 0LL) { // conditional
720cp.code() += "etiss_coverage_count(5, 2453, 2450, 2448, 2451, 2452);\n";
721cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = " + std::to_string(((etiss_int32)(((etiss_int32)imm) << (14)) >> (14))) + "LL;\n";
722cp.code() += "etiss_coverage_count(6, 2462, 2458, 2457, 2455, 2461, 2459);\n";
723} // conditional
724cp.code() += "} // block\n";
725} // block
726cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
727cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
728// -----------------------------------------------------------------------------
729 cp.getAffectedRegisters().add("instructionPointer", 32);
730 }
731 {
732 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
733
734 cp.code() = std::string("//CLUI\n");
735
736// -----------------------------------------------------------------------------
737cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
738// -----------------------------------------------------------------------------
739 }
740
741 return true;
742 },
743 0,
744 [] (BitArray & ba, Instruction & instr)
745 {
746// -----------------------------------------------------------------------------
747etiss_uint32 imm = 0;
748static BitArrayRange R_imm_12(6, 2);
749imm += R_imm_12.read(ba) << 12;
750etiss_uint8 rd = 0;
751static BitArrayRange R_rd_0(11, 7);
752rd += R_rd_0.read(ba) << 0;
753static BitArrayRange R_imm_17(12, 12);
754imm += R_imm_17.read(ba) << 17;
755
756// -----------------------------------------------------------------------------
757
758 std::stringstream ss;
759// -----------------------------------------------------------------------------
760ss << "clui" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rd=" + std::to_string(rd) + "]");
761// -----------------------------------------------------------------------------
762 return ss.str();
763 }
764);
765
766// CADDI16SP -------------------------------------------------------------------
767static InstructionDefinition caddi16sp_nzimm (
768 ISA16_RV32IMACFD,
769 "caddi16sp",
770 (uint16_t) 0x6101,
771 (uint16_t) 0xef83,
772 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
773 {
774
775// -----------------------------------------------------------------------------
776
777// -----------------------------------------------------------------------------
778
779// -----------------------------------------------------------------------------
780etiss_uint16 nzimm = 0;
781static BitArrayRange R_nzimm_5(2, 2);
782nzimm += R_nzimm_5.read(ba) << 5;
783static BitArrayRange R_nzimm_7(4, 3);
784nzimm += R_nzimm_7.read(ba) << 7;
785static BitArrayRange R_nzimm_6(5, 5);
786nzimm += R_nzimm_6.read(ba) << 6;
787static BitArrayRange R_nzimm_4(6, 6);
788nzimm += R_nzimm_4.read(ba) << 4;
789static BitArrayRange R_nzimm_9(12, 12);
790nzimm += R_nzimm_9.read(ba) << 9;
791
792// -----------------------------------------------------------------------------
793
794 {
795 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
796
797 cp.code() = std::string("//CADDI16SP\n");
798
799// -----------------------------------------------------------------------------
800cp.code() += "etiss_coverage_count(1, 50);\n";
801{ // block
802cp.code() += "etiss_coverage_count(1, 1169);\n";
803cp.code() += "{ // block\n";
804cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
805cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
806cp.code() += "} // block\n";
807} // block
808cp.code() += "etiss_coverage_count(1, 2464);\n";
809if (nzimm) { // conditional
810cp.code() += "etiss_coverage_count(1, 2465);\n";
811cp.code() += "*((RV32IMACFD*)cpu)->X[2ULL] = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)nzimm) << (6)) >> (6))) + "LL;\n";
812cp.code() += "etiss_coverage_count(8, 2476, 2468, 2467, 2475, 2471, 2470, 2474, 2472);\n";
813} // conditional
814else { // conditional
815{ // procedure
816cp.code() += "{ // procedure\n";
817cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";
818cp.code() += "etiss_coverage_count(2, 2479, 2477);\n";
819cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
820cp.code() += "} // procedure\n";
821} // procedure
822} // conditional
823cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
824cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
825// -----------------------------------------------------------------------------
826 cp.getAffectedRegisters().add("instructionPointer", 32);
827 }
828 {
829 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
830
831 cp.code() = std::string("//CADDI16SP\n");
832
833// -----------------------------------------------------------------------------
834cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
835// -----------------------------------------------------------------------------
836 }
837
838 return true;
839 },
840 0,
841 [] (BitArray & ba, Instruction & instr)
842 {
843// -----------------------------------------------------------------------------
844etiss_uint16 nzimm = 0;
845static BitArrayRange R_nzimm_5(2, 2);
846nzimm += R_nzimm_5.read(ba) << 5;
847static BitArrayRange R_nzimm_7(4, 3);
848nzimm += R_nzimm_7.read(ba) << 7;
849static BitArrayRange R_nzimm_6(5, 5);
850nzimm += R_nzimm_6.read(ba) << 6;
851static BitArrayRange R_nzimm_4(6, 6);
852nzimm += R_nzimm_4.read(ba) << 4;
853static BitArrayRange R_nzimm_9(12, 12);
854nzimm += R_nzimm_9.read(ba) << 9;
855
856// -----------------------------------------------------------------------------
857
858 std::stringstream ss;
859// -----------------------------------------------------------------------------
860ss << "caddi16sp" << " # " << ba << (" [nzimm=" + std::to_string(nzimm) + "]");
861// -----------------------------------------------------------------------------
862 return ss.str();
863 }
864);
865
866// __reserved_clui -------------------------------------------------------------
867static InstructionDefinition __reserved_clui_rd (
868 ISA16_RV32IMACFD,
869 "__reserved_clui",
870 (uint16_t) 0x6001,
871 (uint16_t) 0xf07f,
872 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
873 {
874
875// -----------------------------------------------------------------------------
876
877// -----------------------------------------------------------------------------
878
879// -----------------------------------------------------------------------------
880etiss_uint8 rd = 0;
881static BitArrayRange R_rd_0(11, 7);
882rd += R_rd_0.read(ba) << 0;
883
884// -----------------------------------------------------------------------------
885
886 {
887 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
888
889 cp.code() = std::string("//__reserved_clui\n");
890
891// -----------------------------------------------------------------------------
892cp.code() += "etiss_coverage_count(1, 51);\n";
893{ // block
894cp.code() += "etiss_coverage_count(1, 1169);\n";
895cp.code() += "{ // block\n";
896cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
897cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
898cp.code() += "} // block\n";
899} // block
900{ // procedure
901cp.code() += "{ // procedure\n";
902cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";
903cp.code() += "etiss_coverage_count(2, 2482, 2480);\n";
904cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
905cp.code() += "} // procedure\n";
906} // procedure
907cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
908cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
909// -----------------------------------------------------------------------------
910 cp.getAffectedRegisters().add("instructionPointer", 32);
911 }
912 {
913 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
914
915 cp.code() = std::string("//__reserved_clui\n");
916
917// -----------------------------------------------------------------------------
918cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
919// -----------------------------------------------------------------------------
920 }
921
922 return true;
923 },
924 0,
925 [] (BitArray & ba, Instruction & instr)
926 {
927// -----------------------------------------------------------------------------
928etiss_uint8 rd = 0;
929static BitArrayRange R_rd_0(11, 7);
930rd += R_rd_0.read(ba) << 0;
931
932// -----------------------------------------------------------------------------
933
934 std::stringstream ss;
935// -----------------------------------------------------------------------------
936ss << "__reserved_clui" << " # " << ba << (" [rd=" + std::to_string(rd) + "]");
937// -----------------------------------------------------------------------------
938 return ss.str();
939 }
940);
941
942// CSRLI -----------------------------------------------------------------------
943static InstructionDefinition csrli_shamt_rs1 (
944 ISA16_RV32IMACFD,
945 "csrli",
946 (uint16_t) 0x8001,
947 (uint16_t) 0xfc03,
948 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
949 {
950
951// -----------------------------------------------------------------------------
952
953// -----------------------------------------------------------------------------
954
955// -----------------------------------------------------------------------------
956etiss_uint8 shamt = 0;
957static BitArrayRange R_shamt_0(6, 2);
958shamt += R_shamt_0.read(ba) << 0;
959etiss_uint8 rs1 = 0;
960static BitArrayRange R_rs1_0(9, 7);
961rs1 += R_rs1_0.read(ba) << 0;
962
963// -----------------------------------------------------------------------------
964
965 {
966 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
967
968 cp.code() = std::string("//CSRLI\n");
969
970// -----------------------------------------------------------------------------
971cp.code() += "etiss_coverage_count(1, 52);\n";
972{ // block
973cp.code() += "etiss_coverage_count(1, 1169);\n";
974cp.code() += "{ // block\n";
975cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
976cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
977cp.code() += "} // block\n";
978} // block
979{ // block
980cp.code() += "etiss_coverage_count(1, 2496);\n";
981cp.code() += "{ // block\n";
982cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] >> " + std::to_string(shamt) + "ULL;\n";
983cp.code() += "etiss_coverage_count(11, 2495, 2487, 2486, 2484, 2485, 2494, 2492, 2491, 2489, 2490, 2493);\n";
984cp.code() += "} // block\n";
985} // block
986cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
987cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
988// -----------------------------------------------------------------------------
989 cp.getAffectedRegisters().add("instructionPointer", 32);
990 }
991
992 return true;
993 },
994 0,
995 [] (BitArray & ba, Instruction & instr)
996 {
997// -----------------------------------------------------------------------------
998etiss_uint8 shamt = 0;
999static BitArrayRange R_shamt_0(6, 2);
1000shamt += R_shamt_0.read(ba) << 0;
1001etiss_uint8 rs1 = 0;
1002static BitArrayRange R_rs1_0(9, 7);
1003rs1 += R_rs1_0.read(ba) << 0;
1004
1005// -----------------------------------------------------------------------------
1006
1007 std::stringstream ss;
1008// -----------------------------------------------------------------------------
1009ss << "csrli" << " # " << ba << (" [shamt=" + std::to_string(shamt) + " | rs1=" + std::to_string(rs1) + "]");
1010// -----------------------------------------------------------------------------
1011 return ss.str();
1012 }
1013);
1014
1015// CSRAI -----------------------------------------------------------------------
1016static InstructionDefinition csrai_shamt_rs1 (
1017 ISA16_RV32IMACFD,
1018 "csrai",
1019 (uint16_t) 0x8401,
1020 (uint16_t) 0xfc03,
1021 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1022 {
1023
1024// -----------------------------------------------------------------------------
1025
1026// -----------------------------------------------------------------------------
1027
1028// -----------------------------------------------------------------------------
1029etiss_uint8 shamt = 0;
1030static BitArrayRange R_shamt_0(6, 2);
1031shamt += R_shamt_0.read(ba) << 0;
1032etiss_uint8 rs1 = 0;
1033static BitArrayRange R_rs1_0(9, 7);
1034rs1 += R_rs1_0.read(ba) << 0;
1035
1036// -----------------------------------------------------------------------------
1037
1038 {
1039 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1040
1041 cp.code() = std::string("//CSRAI\n");
1042
1043// -----------------------------------------------------------------------------
1044cp.code() += "etiss_coverage_count(1, 53);\n";
1045{ // block
1046cp.code() += "etiss_coverage_count(1, 1169);\n";
1047cp.code() += "{ // block\n";
1048cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1049cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1050cp.code() += "} // block\n";
1051} // block
1052{ // block
1053cp.code() += "etiss_coverage_count(1, 2536);\n";
1054cp.code() += "{ // block\n";
1055cp.code() += "etiss_coverage_count(1, 2497);\n";
1056if (shamt) { // conditional
1057cp.code() += "etiss_coverage_count(1, 2498);\n";
1058{ // block
1059cp.code() += "etiss_coverage_count(1, 2518);\n";
1060cp.code() += "{ // block\n";
1061cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = ((etiss_int32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL])) >> " + std::to_string(shamt) + "ULL;\n";
1062cp.code() += "etiss_coverage_count(13, 2517, 2506, 2505, 2503, 2504, 2516, 2513, 2511, 2510, 2508, 2509, 2514, 2515);\n";
1063cp.code() += "} // block\n";
1064} // block
1065} // conditional
1066cp.code() += "} // block\n";
1067} // block
1068cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1069cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1070// -----------------------------------------------------------------------------
1071 cp.getAffectedRegisters().add("instructionPointer", 32);
1072 }
1073
1074 return true;
1075 },
1076 0,
1077 [] (BitArray & ba, Instruction & instr)
1078 {
1079// -----------------------------------------------------------------------------
1080etiss_uint8 shamt = 0;
1081static BitArrayRange R_shamt_0(6, 2);
1082shamt += R_shamt_0.read(ba) << 0;
1083etiss_uint8 rs1 = 0;
1084static BitArrayRange R_rs1_0(9, 7);
1085rs1 += R_rs1_0.read(ba) << 0;
1086
1087// -----------------------------------------------------------------------------
1088
1089 std::stringstream ss;
1090// -----------------------------------------------------------------------------
1091ss << "csrai" << " # " << ba << (" [shamt=" + std::to_string(shamt) + " | rs1=" + std::to_string(rs1) + "]");
1092// -----------------------------------------------------------------------------
1093 return ss.str();
1094 }
1095);
1096
1097// CANDI -----------------------------------------------------------------------
1098static InstructionDefinition candi_imm_rs1 (
1099 ISA16_RV32IMACFD,
1100 "candi",
1101 (uint16_t) 0x8801,
1102 (uint16_t) 0xec03,
1103 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1104 {
1105
1106// -----------------------------------------------------------------------------
1107
1108// -----------------------------------------------------------------------------
1109
1110// -----------------------------------------------------------------------------
1111etiss_uint8 imm = 0;
1112static BitArrayRange R_imm_0(6, 2);
1113imm += R_imm_0.read(ba) << 0;
1114etiss_uint8 rs1 = 0;
1115static BitArrayRange R_rs1_0(9, 7);
1116rs1 += R_rs1_0.read(ba) << 0;
1117static BitArrayRange R_imm_5(12, 12);
1118imm += R_imm_5.read(ba) << 5;
1119
1120// -----------------------------------------------------------------------------
1121
1122 {
1123 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1124
1125 cp.code() = std::string("//CANDI\n");
1126
1127// -----------------------------------------------------------------------------
1128cp.code() += "etiss_coverage_count(1, 54);\n";
1129{ // block
1130cp.code() += "etiss_coverage_count(1, 1169);\n";
1131cp.code() += "{ // block\n";
1132cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1133cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1134cp.code() += "} // block\n";
1135} // block
1136{ // block
1137cp.code() += "etiss_coverage_count(1, 2552);\n";
1138cp.code() += "{ // block\n";
1139cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] & " + std::to_string(((etiss_int8)(((etiss_int8)imm) << (2)) >> (2))) + "LL;\n";
1140cp.code() += "etiss_coverage_count(12, 2551, 2541, 2540, 2538, 2539, 2550, 2546, 2545, 2543, 2544, 2549, 2547);\n";
1141cp.code() += "} // block\n";
1142} // block
1143cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1144cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1145// -----------------------------------------------------------------------------
1146 cp.getAffectedRegisters().add("instructionPointer", 32);
1147 }
1148
1149 return true;
1150 },
1151 0,
1152 [] (BitArray & ba, Instruction & instr)
1153 {
1154// -----------------------------------------------------------------------------
1155etiss_uint8 imm = 0;
1156static BitArrayRange R_imm_0(6, 2);
1157imm += R_imm_0.read(ba) << 0;
1158etiss_uint8 rs1 = 0;
1159static BitArrayRange R_rs1_0(9, 7);
1160rs1 += R_rs1_0.read(ba) << 0;
1161static BitArrayRange R_imm_5(12, 12);
1162imm += R_imm_5.read(ba) << 5;
1163
1164// -----------------------------------------------------------------------------
1165
1166 std::stringstream ss;
1167// -----------------------------------------------------------------------------
1168ss << "candi" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + "]");
1169// -----------------------------------------------------------------------------
1170 return ss.str();
1171 }
1172);
1173
1174// CSUB ------------------------------------------------------------------------
1175static InstructionDefinition csub_rs2_rd (
1176 ISA16_RV32IMACFD,
1177 "csub",
1178 (uint16_t) 0x8c01,
1179 (uint16_t) 0xfc63,
1180 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1181 {
1182
1183// -----------------------------------------------------------------------------
1184
1185// -----------------------------------------------------------------------------
1186
1187// -----------------------------------------------------------------------------
1188etiss_uint8 rs2 = 0;
1189static BitArrayRange R_rs2_0(4, 2);
1190rs2 += R_rs2_0.read(ba) << 0;
1191etiss_uint8 rd = 0;
1192static BitArrayRange R_rd_0(9, 7);
1193rd += R_rd_0.read(ba) << 0;
1194
1195// -----------------------------------------------------------------------------
1196
1197 {
1198 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1199
1200 cp.code() = std::string("//CSUB\n");
1201
1202// -----------------------------------------------------------------------------
1203cp.code() += "etiss_coverage_count(1, 55);\n";
1204{ // block
1205cp.code() += "etiss_coverage_count(1, 1169);\n";
1206cp.code() += "{ // block\n";
1207cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1208cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1209cp.code() += "} // block\n";
1210} // block
1211{ // block
1212cp.code() += "etiss_coverage_count(1, 2570);\n";
1213cp.code() += "{ // block\n";
1214cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] - *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n";
1215cp.code() += "etiss_coverage_count(14, 2569, 2557, 2556, 2554, 2555, 2568, 2562, 2561, 2559, 2560, 2567, 2566, 2564, 2565);\n";
1216cp.code() += "} // block\n";
1217} // block
1218cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1219cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1220// -----------------------------------------------------------------------------
1221 cp.getAffectedRegisters().add("instructionPointer", 32);
1222 }
1223
1224 return true;
1225 },
1226 0,
1227 [] (BitArray & ba, Instruction & instr)
1228 {
1229// -----------------------------------------------------------------------------
1230etiss_uint8 rs2 = 0;
1231static BitArrayRange R_rs2_0(4, 2);
1232rs2 += R_rs2_0.read(ba) << 0;
1233etiss_uint8 rd = 0;
1234static BitArrayRange R_rd_0(9, 7);
1235rd += R_rd_0.read(ba) << 0;
1236
1237// -----------------------------------------------------------------------------
1238
1239 std::stringstream ss;
1240// -----------------------------------------------------------------------------
1241ss << "csub" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]");
1242// -----------------------------------------------------------------------------
1243 return ss.str();
1244 }
1245);
1246
1247// CXOR ------------------------------------------------------------------------
1248static InstructionDefinition cxor_rs2_rd (
1249 ISA16_RV32IMACFD,
1250 "cxor",
1251 (uint16_t) 0x8c21,
1252 (uint16_t) 0xfc63,
1253 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1254 {
1255
1256// -----------------------------------------------------------------------------
1257
1258// -----------------------------------------------------------------------------
1259
1260// -----------------------------------------------------------------------------
1261etiss_uint8 rs2 = 0;
1262static BitArrayRange R_rs2_0(4, 2);
1263rs2 += R_rs2_0.read(ba) << 0;
1264etiss_uint8 rd = 0;
1265static BitArrayRange R_rd_0(9, 7);
1266rd += R_rd_0.read(ba) << 0;
1267
1268// -----------------------------------------------------------------------------
1269
1270 {
1271 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1272
1273 cp.code() = std::string("//CXOR\n");
1274
1275// -----------------------------------------------------------------------------
1276cp.code() += "etiss_coverage_count(1, 56);\n";
1277{ // block
1278cp.code() += "etiss_coverage_count(1, 1169);\n";
1279cp.code() += "{ // block\n";
1280cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1281cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1282cp.code() += "} // block\n";
1283} // block
1284{ // block
1285cp.code() += "etiss_coverage_count(1, 2588);\n";
1286cp.code() += "{ // block\n";
1287cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] ^ *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n";
1288cp.code() += "etiss_coverage_count(14, 2587, 2575, 2574, 2572, 2573, 2586, 2580, 2579, 2577, 2578, 2585, 2584, 2582, 2583);\n";
1289cp.code() += "} // block\n";
1290} // block
1291cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1292cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1293// -----------------------------------------------------------------------------
1294 cp.getAffectedRegisters().add("instructionPointer", 32);
1295 }
1296
1297 return true;
1298 },
1299 0,
1300 [] (BitArray & ba, Instruction & instr)
1301 {
1302// -----------------------------------------------------------------------------
1303etiss_uint8 rs2 = 0;
1304static BitArrayRange R_rs2_0(4, 2);
1305rs2 += R_rs2_0.read(ba) << 0;
1306etiss_uint8 rd = 0;
1307static BitArrayRange R_rd_0(9, 7);
1308rd += R_rd_0.read(ba) << 0;
1309
1310// -----------------------------------------------------------------------------
1311
1312 std::stringstream ss;
1313// -----------------------------------------------------------------------------
1314ss << "cxor" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]");
1315// -----------------------------------------------------------------------------
1316 return ss.str();
1317 }
1318);
1319
1320// COR -------------------------------------------------------------------------
1321static InstructionDefinition cor_rs2_rd (
1322 ISA16_RV32IMACFD,
1323 "cor",
1324 (uint16_t) 0x8c41,
1325 (uint16_t) 0xfc63,
1326 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1327 {
1328
1329// -----------------------------------------------------------------------------
1330
1331// -----------------------------------------------------------------------------
1332
1333// -----------------------------------------------------------------------------
1334etiss_uint8 rs2 = 0;
1335static BitArrayRange R_rs2_0(4, 2);
1336rs2 += R_rs2_0.read(ba) << 0;
1337etiss_uint8 rd = 0;
1338static BitArrayRange R_rd_0(9, 7);
1339rd += R_rd_0.read(ba) << 0;
1340
1341// -----------------------------------------------------------------------------
1342
1343 {
1344 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1345
1346 cp.code() = std::string("//COR\n");
1347
1348// -----------------------------------------------------------------------------
1349cp.code() += "etiss_coverage_count(1, 57);\n";
1350{ // block
1351cp.code() += "etiss_coverage_count(1, 1169);\n";
1352cp.code() += "{ // block\n";
1353cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1354cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1355cp.code() += "} // block\n";
1356} // block
1357{ // block
1358cp.code() += "etiss_coverage_count(1, 2606);\n";
1359cp.code() += "{ // block\n";
1360cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] | *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n";
1361cp.code() += "etiss_coverage_count(14, 2605, 2593, 2592, 2590, 2591, 2604, 2598, 2597, 2595, 2596, 2603, 2602, 2600, 2601);\n";
1362cp.code() += "} // block\n";
1363} // block
1364cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1365cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1366// -----------------------------------------------------------------------------
1367 cp.getAffectedRegisters().add("instructionPointer", 32);
1368 }
1369
1370 return true;
1371 },
1372 0,
1373 [] (BitArray & ba, Instruction & instr)
1374 {
1375// -----------------------------------------------------------------------------
1376etiss_uint8 rs2 = 0;
1377static BitArrayRange R_rs2_0(4, 2);
1378rs2 += R_rs2_0.read(ba) << 0;
1379etiss_uint8 rd = 0;
1380static BitArrayRange R_rd_0(9, 7);
1381rd += R_rd_0.read(ba) << 0;
1382
1383// -----------------------------------------------------------------------------
1384
1385 std::stringstream ss;
1386// -----------------------------------------------------------------------------
1387ss << "cor" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]");
1388// -----------------------------------------------------------------------------
1389 return ss.str();
1390 }
1391);
1392
1393// CAND ------------------------------------------------------------------------
1394static InstructionDefinition cand_rs2_rd (
1395 ISA16_RV32IMACFD,
1396 "cand",
1397 (uint16_t) 0x8c61,
1398 (uint16_t) 0xfc63,
1399 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1400 {
1401
1402// -----------------------------------------------------------------------------
1403
1404// -----------------------------------------------------------------------------
1405
1406// -----------------------------------------------------------------------------
1407etiss_uint8 rs2 = 0;
1408static BitArrayRange R_rs2_0(4, 2);
1409rs2 += R_rs2_0.read(ba) << 0;
1410etiss_uint8 rd = 0;
1411static BitArrayRange R_rd_0(9, 7);
1412rd += R_rd_0.read(ba) << 0;
1413
1414// -----------------------------------------------------------------------------
1415
1416 {
1417 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1418
1419 cp.code() = std::string("//CAND\n");
1420
1421// -----------------------------------------------------------------------------
1422cp.code() += "etiss_coverage_count(1, 58);\n";
1423{ // block
1424cp.code() += "etiss_coverage_count(1, 1169);\n";
1425cp.code() += "{ // block\n";
1426cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1427cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1428cp.code() += "} // block\n";
1429} // block
1430{ // block
1431cp.code() += "etiss_coverage_count(1, 2624);\n";
1432cp.code() += "{ // block\n";
1433cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd + 8ULL) + "ULL] & *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 + 8ULL) + "ULL];\n";
1434cp.code() += "etiss_coverage_count(14, 2623, 2611, 2610, 2608, 2609, 2622, 2616, 2615, 2613, 2614, 2621, 2620, 2618, 2619);\n";
1435cp.code() += "} // block\n";
1436} // block
1437cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1438cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1439// -----------------------------------------------------------------------------
1440 cp.getAffectedRegisters().add("instructionPointer", 32);
1441 }
1442
1443 return true;
1444 },
1445 0,
1446 [] (BitArray & ba, Instruction & instr)
1447 {
1448// -----------------------------------------------------------------------------
1449etiss_uint8 rs2 = 0;
1450static BitArrayRange R_rs2_0(4, 2);
1451rs2 += R_rs2_0.read(ba) << 0;
1452etiss_uint8 rd = 0;
1453static BitArrayRange R_rd_0(9, 7);
1454rd += R_rd_0.read(ba) << 0;
1455
1456// -----------------------------------------------------------------------------
1457
1458 std::stringstream ss;
1459// -----------------------------------------------------------------------------
1460ss << "cand" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]");
1461// -----------------------------------------------------------------------------
1462 return ss.str();
1463 }
1464);
1465
1466// CJ --------------------------------------------------------------------------
1467static InstructionDefinition cj_imm (
1468 ISA16_RV32IMACFD,
1469 "cj",
1470 (uint16_t) 0xa001,
1471 (uint16_t) 0xe003,
1472 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1473 {
1474
1475// -----------------------------------------------------------------------------
1476
1477// -----------------------------------------------------------------------------
1478
1479// -----------------------------------------------------------------------------
1480etiss_uint16 imm = 0;
1481static BitArrayRange R_imm_5(2, 2);
1482imm += R_imm_5.read(ba) << 5;
1483static BitArrayRange R_imm_1(5, 3);
1484imm += R_imm_1.read(ba) << 1;
1485static BitArrayRange R_imm_7(6, 6);
1486imm += R_imm_7.read(ba) << 7;
1487static BitArrayRange R_imm_6(7, 7);
1488imm += R_imm_6.read(ba) << 6;
1489static BitArrayRange R_imm_10(8, 8);
1490imm += R_imm_10.read(ba) << 10;
1491static BitArrayRange R_imm_8(10, 9);
1492imm += R_imm_8.read(ba) << 8;
1493static BitArrayRange R_imm_4(11, 11);
1494imm += R_imm_4.read(ba) << 4;
1495static BitArrayRange R_imm_11(12, 12);
1496imm += R_imm_11.read(ba) << 11;
1497
1498// -----------------------------------------------------------------------------
1499
1500 {
1501 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1502
1503 cp.code() = std::string("//CJ\n");
1504
1505// -----------------------------------------------------------------------------
1506cp.code() += "etiss_coverage_count(1, 59);\n";
1507{ // block
1508cp.code() += "etiss_coverage_count(1, 1169);\n";
1509cp.code() += "{ // block\n";
1510cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1511cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1512cp.code() += "} // block\n";
1513} // block
1514cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
1515cp.code() += "etiss_coverage_count(6, 2631, 2625, 2630, 2626, 2629, 2627);\n";
1516cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1517cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1518// -----------------------------------------------------------------------------
1519 cp.getAffectedRegisters().add("instructionPointer", 32);
1520 }
1521 {
1522 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1523
1524 cp.code() = std::string("//CJ\n");
1525
1526// -----------------------------------------------------------------------------
1527cp.code() += "return cpu->exception;\n";
1528// -----------------------------------------------------------------------------
1529 }
1530
1531 return true;
1532 },
1533 0,
1534 [] (BitArray & ba, Instruction & instr)
1535 {
1536// -----------------------------------------------------------------------------
1537etiss_uint16 imm = 0;
1538static BitArrayRange R_imm_5(2, 2);
1539imm += R_imm_5.read(ba) << 5;
1540static BitArrayRange R_imm_1(5, 3);
1541imm += R_imm_1.read(ba) << 1;
1542static BitArrayRange R_imm_7(6, 6);
1543imm += R_imm_7.read(ba) << 7;
1544static BitArrayRange R_imm_6(7, 7);
1545imm += R_imm_6.read(ba) << 6;
1546static BitArrayRange R_imm_10(8, 8);
1547imm += R_imm_10.read(ba) << 10;
1548static BitArrayRange R_imm_8(10, 9);
1549imm += R_imm_8.read(ba) << 8;
1550static BitArrayRange R_imm_4(11, 11);
1551imm += R_imm_4.read(ba) << 4;
1552static BitArrayRange R_imm_11(12, 12);
1553imm += R_imm_11.read(ba) << 11;
1554
1555// -----------------------------------------------------------------------------
1556
1557 std::stringstream ss;
1558// -----------------------------------------------------------------------------
1559ss << "cj" << " # " << ba << (" [imm=" + std::to_string(imm) + "]");
1560// -----------------------------------------------------------------------------
1561 return ss.str();
1562 }
1563);
1564
1565// CBEQZ -----------------------------------------------------------------------
1566static InstructionDefinition cbeqz_imm_rs1 (
1567 ISA16_RV32IMACFD,
1568 "cbeqz",
1569 (uint16_t) 0xc001,
1570 (uint16_t) 0xe003,
1571 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1572 {
1573
1574// -----------------------------------------------------------------------------
1575
1576// -----------------------------------------------------------------------------
1577
1578// -----------------------------------------------------------------------------
1579etiss_uint16 imm = 0;
1580static BitArrayRange R_imm_5(2, 2);
1581imm += R_imm_5.read(ba) << 5;
1582static BitArrayRange R_imm_1(4, 3);
1583imm += R_imm_1.read(ba) << 1;
1584static BitArrayRange R_imm_6(6, 5);
1585imm += R_imm_6.read(ba) << 6;
1586etiss_uint8 rs1 = 0;
1587static BitArrayRange R_rs1_0(9, 7);
1588rs1 += R_rs1_0.read(ba) << 0;
1589static BitArrayRange R_imm_3(11, 10);
1590imm += R_imm_3.read(ba) << 3;
1591static BitArrayRange R_imm_8(12, 12);
1592imm += R_imm_8.read(ba) << 8;
1593
1594// -----------------------------------------------------------------------------
1595
1596 {
1597 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1598
1599 cp.code() = std::string("//CBEQZ\n");
1600
1601// -----------------------------------------------------------------------------
1602cp.code() += "etiss_coverage_count(1, 60);\n";
1603{ // block
1604cp.code() += "etiss_coverage_count(1, 1169);\n";
1605cp.code() += "{ // block\n";
1606cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1607cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1608cp.code() += "} // block\n";
1609} // block
1610cp.code() += "etiss_coverage_count(1, 2632);\n";
1611cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] == 0LL) { // conditional\n";
1612cp.code() += "etiss_coverage_count(6, 2639, 2637, 2636, 2634, 2635, 2638);\n";
1613cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (7)) >> (7))) + "LL;\n";
1614cp.code() += "etiss_coverage_count(6, 2646, 2640, 2645, 2641, 2644, 2642);\n";
1615cp.code() += "} // conditional\n";
1616cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1617cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1618// -----------------------------------------------------------------------------
1619 cp.getAffectedRegisters().add("instructionPointer", 32);
1620 }
1621 {
1622 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1623
1624 cp.code() = std::string("//CBEQZ\n");
1625
1626// -----------------------------------------------------------------------------
1627cp.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + "ULL) return cpu->exception;\n";
1628// -----------------------------------------------------------------------------
1629 }
1630
1631 return true;
1632 },
1633 0,
1634 [] (BitArray & ba, Instruction & instr)
1635 {
1636// -----------------------------------------------------------------------------
1637etiss_uint16 imm = 0;
1638static BitArrayRange R_imm_5(2, 2);
1639imm += R_imm_5.read(ba) << 5;
1640static BitArrayRange R_imm_1(4, 3);
1641imm += R_imm_1.read(ba) << 1;
1642static BitArrayRange R_imm_6(6, 5);
1643imm += R_imm_6.read(ba) << 6;
1644etiss_uint8 rs1 = 0;
1645static BitArrayRange R_rs1_0(9, 7);
1646rs1 += R_rs1_0.read(ba) << 0;
1647static BitArrayRange R_imm_3(11, 10);
1648imm += R_imm_3.read(ba) << 3;
1649static BitArrayRange R_imm_8(12, 12);
1650imm += R_imm_8.read(ba) << 8;
1651
1652// -----------------------------------------------------------------------------
1653
1654 std::stringstream ss;
1655// -----------------------------------------------------------------------------
1656ss << "cbeqz" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + "]");
1657// -----------------------------------------------------------------------------
1658 return ss.str();
1659 }
1660);
1661
1662// CBNEZ -----------------------------------------------------------------------
1663static InstructionDefinition cbnez_imm_rs1 (
1664 ISA16_RV32IMACFD,
1665 "cbnez",
1666 (uint16_t) 0xe001,
1667 (uint16_t) 0xe003,
1668 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1669 {
1670
1671// -----------------------------------------------------------------------------
1672
1673// -----------------------------------------------------------------------------
1674
1675// -----------------------------------------------------------------------------
1676etiss_uint16 imm = 0;
1677static BitArrayRange R_imm_5(2, 2);
1678imm += R_imm_5.read(ba) << 5;
1679static BitArrayRange R_imm_1(4, 3);
1680imm += R_imm_1.read(ba) << 1;
1681static BitArrayRange R_imm_6(6, 5);
1682imm += R_imm_6.read(ba) << 6;
1683etiss_uint8 rs1 = 0;
1684static BitArrayRange R_rs1_0(9, 7);
1685rs1 += R_rs1_0.read(ba) << 0;
1686static BitArrayRange R_imm_3(11, 10);
1687imm += R_imm_3.read(ba) << 3;
1688static BitArrayRange R_imm_8(12, 12);
1689imm += R_imm_8.read(ba) << 8;
1690
1691// -----------------------------------------------------------------------------
1692
1693 {
1694 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1695
1696 cp.code() = std::string("//CBNEZ\n");
1697
1698// -----------------------------------------------------------------------------
1699cp.code() += "etiss_coverage_count(1, 61);\n";
1700{ // block
1701cp.code() += "etiss_coverage_count(1, 1169);\n";
1702cp.code() += "{ // block\n";
1703cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1704cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1705cp.code() += "} // block\n";
1706} // block
1707cp.code() += "etiss_coverage_count(1, 2647);\n";
1708cp.code() += "if (*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] != 0LL) { // conditional\n";
1709cp.code() += "etiss_coverage_count(6, 2654, 2652, 2651, 2649, 2650, 2653);\n";
1710cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + ((etiss_int16)(((etiss_int16)imm) << (7)) >> (7))) + "LL;\n";
1711cp.code() += "etiss_coverage_count(6, 2661, 2655, 2660, 2656, 2659, 2657);\n";
1712cp.code() += "} // conditional\n";
1713cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1714cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1715// -----------------------------------------------------------------------------
1716 cp.getAffectedRegisters().add("instructionPointer", 32);
1717 }
1718 {
1719 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1720
1721 cp.code() = std::string("//CBNEZ\n");
1722
1723// -----------------------------------------------------------------------------
1724cp.code() += "if (cpu->nextPc != " + std::to_string(ic.current_address_ + 2) + "ULL) return cpu->exception;\n";
1725// -----------------------------------------------------------------------------
1726 }
1727
1728 return true;
1729 },
1730 0,
1731 [] (BitArray & ba, Instruction & instr)
1732 {
1733// -----------------------------------------------------------------------------
1734etiss_uint16 imm = 0;
1735static BitArrayRange R_imm_5(2, 2);
1736imm += R_imm_5.read(ba) << 5;
1737static BitArrayRange R_imm_1(4, 3);
1738imm += R_imm_1.read(ba) << 1;
1739static BitArrayRange R_imm_6(6, 5);
1740imm += R_imm_6.read(ba) << 6;
1741etiss_uint8 rs1 = 0;
1742static BitArrayRange R_rs1_0(9, 7);
1743rs1 += R_rs1_0.read(ba) << 0;
1744static BitArrayRange R_imm_3(11, 10);
1745imm += R_imm_3.read(ba) << 3;
1746static BitArrayRange R_imm_8(12, 12);
1747imm += R_imm_8.read(ba) << 8;
1748
1749// -----------------------------------------------------------------------------
1750
1751 std::stringstream ss;
1752// -----------------------------------------------------------------------------
1753ss << "cbnez" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + "]");
1754// -----------------------------------------------------------------------------
1755 return ss.str();
1756 }
1757);
1758
1759// CSLLI -----------------------------------------------------------------------
1760static InstructionDefinition cslli_nzuimm_rs1 (
1761 ISA16_RV32IMACFD,
1762 "cslli",
1763 (uint16_t) 0x02,
1764 (uint16_t) 0xf003,
1765 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1766 {
1767
1768// -----------------------------------------------------------------------------
1769
1770// -----------------------------------------------------------------------------
1771
1772// -----------------------------------------------------------------------------
1773etiss_uint8 nzuimm = 0;
1774static BitArrayRange R_nzuimm_0(6, 2);
1775nzuimm += R_nzuimm_0.read(ba) << 0;
1776etiss_uint8 rs1 = 0;
1777static BitArrayRange R_rs1_0(11, 7);
1778rs1 += R_rs1_0.read(ba) << 0;
1779
1780// -----------------------------------------------------------------------------
1781
1782 {
1783 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1784
1785 cp.code() = std::string("//CSLLI\n");
1786
1787// -----------------------------------------------------------------------------
1788cp.code() += "etiss_coverage_count(1, 62);\n";
1789{ // block
1790cp.code() += "etiss_coverage_count(1, 1169);\n";
1791cp.code() += "{ // block\n";
1792cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1793cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1794cp.code() += "} // block\n";
1795} // block
1796cp.code() += "etiss_coverage_count(1, 2662);\n";
1797if (nzuimm) { // conditional
1798cp.code() += "etiss_coverage_count(1, 2663);\n";
1799cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] << " + std::to_string(nzuimm) + "ULL;\n";
1800cp.code() += "etiss_coverage_count(9, 2676, 2668, 2667, 2665, 2675, 2673, 2672, 2670, 2674);\n";
1801} // conditional
1802cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1803cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1804// -----------------------------------------------------------------------------
1805 cp.getAffectedRegisters().add("instructionPointer", 32);
1806 }
1807
1808 return true;
1809 },
1810 0,
1811 [] (BitArray & ba, Instruction & instr)
1812 {
1813// -----------------------------------------------------------------------------
1814etiss_uint8 nzuimm = 0;
1815static BitArrayRange R_nzuimm_0(6, 2);
1816nzuimm += R_nzuimm_0.read(ba) << 0;
1817etiss_uint8 rs1 = 0;
1818static BitArrayRange R_rs1_0(11, 7);
1819rs1 += R_rs1_0.read(ba) << 0;
1820
1821// -----------------------------------------------------------------------------
1822
1823 std::stringstream ss;
1824// -----------------------------------------------------------------------------
1825ss << "cslli" << " # " << ba << (" [nzuimm=" + std::to_string(nzuimm) + " | rs1=" + std::to_string(rs1) + "]");
1826// -----------------------------------------------------------------------------
1827 return ss.str();
1828 }
1829);
1830
1831// CLWSP -----------------------------------------------------------------------
1832static InstructionDefinition clwsp_uimm_rd (
1833 ISA16_RV32IMACFD,
1834 "clwsp",
1835 (uint16_t) 0x4002,
1836 (uint16_t) 0xe003,
1837 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1838 {
1839
1840// -----------------------------------------------------------------------------
1841
1842// -----------------------------------------------------------------------------
1843
1844// -----------------------------------------------------------------------------
1845etiss_uint8 uimm = 0;
1846static BitArrayRange R_uimm_6(3, 2);
1847uimm += R_uimm_6.read(ba) << 6;
1848static BitArrayRange R_uimm_2(6, 4);
1849uimm += R_uimm_2.read(ba) << 2;
1850etiss_uint8 rd = 0;
1851static BitArrayRange R_rd_0(11, 7);
1852rd += R_rd_0.read(ba) << 0;
1853static BitArrayRange R_uimm_5(12, 12);
1854uimm += R_uimm_5.read(ba) << 5;
1855
1856// -----------------------------------------------------------------------------
1857
1858 {
1859 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1860
1861 cp.code() = std::string("//CLWSP\n");
1862
1863// -----------------------------------------------------------------------------
1864cp.code() += "etiss_coverage_count(1, 63);\n";
1865{ // block
1866cp.code() += "etiss_coverage_count(1, 1169);\n";
1867cp.code() += "{ // block\n";
1868cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1869cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1870cp.code() += "} // block\n";
1871} // block
1872{ // block
1873cp.code() += "etiss_coverage_count(1, 2703);\n";
1874cp.code() += "{ // block\n";
1875cp.code() += "etiss_coverage_count(1, 2677);\n";
1876if (rd % 32ULL) { // conditional
1877cp.code() += "etiss_coverage_count(2, 2680, 2678);\n";
1878{ // block
1879cp.code() += "etiss_coverage_count(1, 2699);\n";
1880cp.code() += "{ // block\n";
1881cp.code() += "etiss_uint32 mem_val_0;\n";
1882cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL, (etiss_uint8*)&mem_val_0, 4);\n";
1883cp.code() += "if (cpu->exception) { // conditional\n";
1884{ // procedure
1885cp.code() += "{ // procedure\n";
1886cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
1887cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1888cp.code() += "} // procedure\n";
1889} // procedure
1890cp.code() += "} // conditional\n";
1891cp.code() += "etiss_int32 res = mem_val_0;\n";
1892cp.code() += "etiss_coverage_count(6, 2689, 2688, 2687, 2685, 2684, 2686);\n";
1893cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_int32)(res);\n";
1894cp.code() += "etiss_coverage_count(6, 2698, 2694, 2693, 2691, 2697, 2695);\n";
1895cp.code() += "} // block\n";
1896} // block
1897} // conditional
1898else { // conditional
1899{ // procedure
1900cp.code() += "{ // procedure\n";
1901cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2ULL);\n";
1902cp.code() += "etiss_coverage_count(3, 2702, 2700, 2701);\n";
1903cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
1904cp.code() += "} // procedure\n";
1905} // procedure
1906} // conditional
1907cp.code() += "} // block\n";
1908} // block
1909cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1910cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1911// -----------------------------------------------------------------------------
1912 cp.getAffectedRegisters().add("instructionPointer", 32);
1913 }
1914 {
1915 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
1916
1917 cp.code() = std::string("//CLWSP\n");
1918
1919// -----------------------------------------------------------------------------
1920cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
1921// -----------------------------------------------------------------------------
1922 }
1923
1924 return true;
1925 },
1926 0,
1927 [] (BitArray & ba, Instruction & instr)
1928 {
1929// -----------------------------------------------------------------------------
1930etiss_uint8 uimm = 0;
1931static BitArrayRange R_uimm_6(3, 2);
1932uimm += R_uimm_6.read(ba) << 6;
1933static BitArrayRange R_uimm_2(6, 4);
1934uimm += R_uimm_2.read(ba) << 2;
1935etiss_uint8 rd = 0;
1936static BitArrayRange R_rd_0(11, 7);
1937rd += R_rd_0.read(ba) << 0;
1938static BitArrayRange R_uimm_5(12, 12);
1939uimm += R_uimm_5.read(ba) << 5;
1940
1941// -----------------------------------------------------------------------------
1942
1943 std::stringstream ss;
1944// -----------------------------------------------------------------------------
1945ss << "clwsp" << " # " << ba << (" [uimm=" + std::to_string(uimm) + " | rd=" + std::to_string(rd) + "]");
1946// -----------------------------------------------------------------------------
1947 return ss.str();
1948 }
1949);
1950
1951// CMV -------------------------------------------------------------------------
1952static InstructionDefinition cmv_rs2_rd (
1953 ISA16_RV32IMACFD,
1954 "cmv",
1955 (uint16_t) 0x8002,
1956 (uint16_t) 0xf003,
1957 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1958 {
1959
1960// -----------------------------------------------------------------------------
1961
1962// -----------------------------------------------------------------------------
1963
1964// -----------------------------------------------------------------------------
1965etiss_uint8 rs2 = 0;
1966static BitArrayRange R_rs2_0(6, 2);
1967rs2 += R_rs2_0.read(ba) << 0;
1968etiss_uint8 rd = 0;
1969static BitArrayRange R_rd_0(11, 7);
1970rd += R_rd_0.read(ba) << 0;
1971
1972// -----------------------------------------------------------------------------
1973
1974 {
1975 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1976
1977 cp.code() = std::string("//CMV\n");
1978
1979// -----------------------------------------------------------------------------
1980cp.code() += "etiss_coverage_count(1, 64);\n";
1981{ // block
1982cp.code() += "etiss_coverage_count(1, 1169);\n";
1983cp.code() += "{ // block\n";
1984cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
1985cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1986cp.code() += "} // block\n";
1987} // block
1988cp.code() += "etiss_coverage_count(1, 2704);\n";
1989if ((rd % 32ULL) != 0LL) { // conditional
1990cp.code() += "etiss_coverage_count(5, 2710, 2707, 2705, 2708, 2709);\n";
1991cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
1992cp.code() += "etiss_coverage_count(7, 2721, 2715, 2714, 2712, 2720, 2719, 2717);\n";
1993} // conditional
1994cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1995cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1996// -----------------------------------------------------------------------------
1997 cp.getAffectedRegisters().add("instructionPointer", 32);
1998 }
1999
2000 return true;
2001 },
2002 0,
2003 [] (BitArray & ba, Instruction & instr)
2004 {
2005// -----------------------------------------------------------------------------
2006etiss_uint8 rs2 = 0;
2007static BitArrayRange R_rs2_0(6, 2);
2008rs2 += R_rs2_0.read(ba) << 0;
2009etiss_uint8 rd = 0;
2010static BitArrayRange R_rd_0(11, 7);
2011rd += R_rd_0.read(ba) << 0;
2012
2013// -----------------------------------------------------------------------------
2014
2015 std::stringstream ss;
2016// -----------------------------------------------------------------------------
2017ss << "cmv" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]");
2018// -----------------------------------------------------------------------------
2019 return ss.str();
2020 }
2021);
2022
2023// CJR -------------------------------------------------------------------------
2024static InstructionDefinition cjr_rs1 (
2025 ISA16_RV32IMACFD,
2026 "cjr",
2027 (uint16_t) 0x8002,
2028 (uint16_t) 0xf07f,
2029 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2030 {
2031
2032// -----------------------------------------------------------------------------
2033
2034// -----------------------------------------------------------------------------
2035
2036// -----------------------------------------------------------------------------
2037etiss_uint8 rs1 = 0;
2038static BitArrayRange R_rs1_0(11, 7);
2039rs1 += R_rs1_0.read(ba) << 0;
2040
2041// -----------------------------------------------------------------------------
2042
2043 {
2044 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2045
2046 cp.code() = std::string("//CJR\n");
2047
2048// -----------------------------------------------------------------------------
2049cp.code() += "etiss_coverage_count(1, 65);\n";
2050{ // block
2051cp.code() += "etiss_coverage_count(1, 1169);\n";
2052cp.code() += "{ // block\n";
2053cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
2054cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2055cp.code() += "} // block\n";
2056} // block
2057cp.code() += "etiss_coverage_count(1, 2722);\n";
2058if (rs1) { // conditional
2059cp.code() += "etiss_coverage_count(1, 2723);\n";
2060cp.code() += "cpu->nextPc = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] & -2LL;\n";
2061cp.code() += "etiss_coverage_count(6, 2733, 2724, 2732, 2729, 2728, 2726);\n";
2062} // conditional
2063else { // conditional
2064{ // procedure
2065cp.code() += "{ // procedure\n";
2066cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2ULL);\n";
2067cp.code() += "etiss_coverage_count(3, 2736, 2734, 2735);\n";
2068cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
2069cp.code() += "} // procedure\n";
2070} // procedure
2071} // conditional
2072cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2073cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2074// -----------------------------------------------------------------------------
2075 cp.getAffectedRegisters().add("instructionPointer", 32);
2076 }
2077 {
2078 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
2079
2080 cp.code() = std::string("//CJR\n");
2081
2082// -----------------------------------------------------------------------------
2083cp.code() += "return cpu->exception;\n";
2084// -----------------------------------------------------------------------------
2085 }
2086
2087 return true;
2088 },
2089 0,
2090 [] (BitArray & ba, Instruction & instr)
2091 {
2092// -----------------------------------------------------------------------------
2093etiss_uint8 rs1 = 0;
2094static BitArrayRange R_rs1_0(11, 7);
2095rs1 += R_rs1_0.read(ba) << 0;
2096
2097// -----------------------------------------------------------------------------
2098
2099 std::stringstream ss;
2100// -----------------------------------------------------------------------------
2101ss << "cjr" << " # " << ba << (" [rs1=" + std::to_string(rs1) + "]");
2102// -----------------------------------------------------------------------------
2103 return ss.str();
2104 }
2105);
2106
2107// __reserved_cmv --------------------------------------------------------------
2108static InstructionDefinition __reserved_cmv_ (
2109 ISA16_RV32IMACFD,
2110 "__reserved_cmv",
2111 (uint16_t) 0x8002,
2112 (uint16_t) 0xffff,
2113 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2114 {
2115
2116// -----------------------------------------------------------------------------
2117
2118// -----------------------------------------------------------------------------
2119
2120// -----------------------------------------------------------------------------
2121
2122// -----------------------------------------------------------------------------
2123
2124 {
2125 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2126
2127 cp.code() = std::string("//__reserved_cmv\n");
2128
2129// -----------------------------------------------------------------------------
2130cp.code() += "etiss_coverage_count(1, 66);\n";
2131{ // block
2132cp.code() += "etiss_coverage_count(1, 1169);\n";
2133cp.code() += "{ // block\n";
2134cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
2135cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2136cp.code() += "} // block\n";
2137} // block
2138{ // procedure
2139cp.code() += "{ // procedure\n";
2140cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2ULL);\n";
2141cp.code() += "etiss_coverage_count(3, 2739, 2737, 2738);\n";
2142cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
2143cp.code() += "} // procedure\n";
2144} // procedure
2145cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2146cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2147// -----------------------------------------------------------------------------
2148 cp.getAffectedRegisters().add("instructionPointer", 32);
2149 }
2150 {
2151 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
2152
2153 cp.code() = std::string("//__reserved_cmv\n");
2154
2155// -----------------------------------------------------------------------------
2156cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
2157// -----------------------------------------------------------------------------
2158 }
2159
2160 return true;
2161 },
2162 0,
2163 [] (BitArray & ba, Instruction & instr)
2164 {
2165// -----------------------------------------------------------------------------
2166
2167// -----------------------------------------------------------------------------
2168
2169 std::stringstream ss;
2170// -----------------------------------------------------------------------------
2171ss << "__reserved_cmv" << " # " << ba << (" []");
2172// -----------------------------------------------------------------------------
2173 return ss.str();
2174 }
2175);
2176
2177// CADD ------------------------------------------------------------------------
2178static InstructionDefinition cadd_rs2_rd (
2179 ISA16_RV32IMACFD,
2180 "cadd",
2181 (uint16_t) 0x9002,
2182 (uint16_t) 0xf003,
2183 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2184 {
2185
2186// -----------------------------------------------------------------------------
2187
2188// -----------------------------------------------------------------------------
2189
2190// -----------------------------------------------------------------------------
2191etiss_uint8 rs2 = 0;
2192static BitArrayRange R_rs2_0(6, 2);
2193rs2 += R_rs2_0.read(ba) << 0;
2194etiss_uint8 rd = 0;
2195static BitArrayRange R_rd_0(11, 7);
2196rd += R_rd_0.read(ba) << 0;
2197
2198// -----------------------------------------------------------------------------
2199
2200 {
2201 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2202
2203 cp.code() = std::string("//CADD\n");
2204
2205// -----------------------------------------------------------------------------
2206cp.code() += "etiss_coverage_count(1, 67);\n";
2207{ // block
2208cp.code() += "etiss_coverage_count(1, 1169);\n";
2209cp.code() += "{ // block\n";
2210cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
2211cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2212cp.code() += "} // block\n";
2213} // block
2214cp.code() += "etiss_coverage_count(1, 2740);\n";
2215if ((rd % 32ULL) != 0LL) { // conditional
2216cp.code() += "etiss_coverage_count(5, 2746, 2743, 2741, 2744, 2745);\n";
2217cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = *((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] + *((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL];\n";
2218cp.code() += "etiss_coverage_count(11, 2763, 2751, 2750, 2748, 2762, 2756, 2755, 2753, 2761, 2760, 2758);\n";
2219} // conditional
2220cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2221cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2222// -----------------------------------------------------------------------------
2223 cp.getAffectedRegisters().add("instructionPointer", 32);
2224 }
2225
2226 return true;
2227 },
2228 0,
2229 [] (BitArray & ba, Instruction & instr)
2230 {
2231// -----------------------------------------------------------------------------
2232etiss_uint8 rs2 = 0;
2233static BitArrayRange R_rs2_0(6, 2);
2234rs2 += R_rs2_0.read(ba) << 0;
2235etiss_uint8 rd = 0;
2236static BitArrayRange R_rd_0(11, 7);
2237rd += R_rd_0.read(ba) << 0;
2238
2239// -----------------------------------------------------------------------------
2240
2241 std::stringstream ss;
2242// -----------------------------------------------------------------------------
2243ss << "cadd" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | rd=" + std::to_string(rd) + "]");
2244// -----------------------------------------------------------------------------
2245 return ss.str();
2246 }
2247);
2248
2249// CJALR -----------------------------------------------------------------------
2250static InstructionDefinition cjalr_rs1 (
2251 ISA16_RV32IMACFD,
2252 "cjalr",
2253 (uint16_t) 0x9002,
2254 (uint16_t) 0xf07f,
2255 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2256 {
2257
2258// -----------------------------------------------------------------------------
2259
2260// -----------------------------------------------------------------------------
2261
2262// -----------------------------------------------------------------------------
2263etiss_uint8 rs1 = 0;
2264static BitArrayRange R_rs1_0(11, 7);
2265rs1 += R_rs1_0.read(ba) << 0;
2266
2267// -----------------------------------------------------------------------------
2268
2269 {
2270 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2271
2272 cp.code() = std::string("//CJALR\n");
2273
2274// -----------------------------------------------------------------------------
2275cp.code() += "etiss_coverage_count(1, 68);\n";
2276{ // block
2277cp.code() += "etiss_coverage_count(1, 1169);\n";
2278cp.code() += "{ // block\n";
2279cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
2280cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2281cp.code() += "} // block\n";
2282} // block
2283{ // block
2284cp.code() += "etiss_coverage_count(1, 2784);\n";
2285cp.code() += "{ // block\n";
2286cp.code() += "etiss_uint32 new_pc = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL];\n";
2287cp.code() += "etiss_coverage_count(4, 2770, 2769, 2768, 2766);\n";
2288cp.code() += "*((RV32IMACFD*)cpu)->X[1ULL] = " + std::to_string(ic.current_address_ + 2ULL) + "ULL;\n";
2289cp.code() += "etiss_coverage_count(6, 2777, 2773, 2772, 2776, 2774, 2775);\n";
2290cp.code() += "cpu->nextPc = new_pc & -2LL;\n";
2291cp.code() += "etiss_coverage_count(4, 2783, 2778, 2782, 2779);\n";
2292cp.code() += "} // block\n";
2293} // block
2294cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2295cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2296// -----------------------------------------------------------------------------
2297 cp.getAffectedRegisters().add("instructionPointer", 32);
2298 }
2299 {
2300 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
2301
2302 cp.code() = std::string("//CJALR\n");
2303
2304// -----------------------------------------------------------------------------
2305cp.code() += "return cpu->exception;\n";
2306// -----------------------------------------------------------------------------
2307 }
2308
2309 return true;
2310 },
2311 0,
2312 [] (BitArray & ba, Instruction & instr)
2313 {
2314// -----------------------------------------------------------------------------
2315etiss_uint8 rs1 = 0;
2316static BitArrayRange R_rs1_0(11, 7);
2317rs1 += R_rs1_0.read(ba) << 0;
2318
2319// -----------------------------------------------------------------------------
2320
2321 std::stringstream ss;
2322// -----------------------------------------------------------------------------
2323ss << "cjalr" << " # " << ba << (" [rs1=" + std::to_string(rs1) + "]");
2324// -----------------------------------------------------------------------------
2325 return ss.str();
2326 }
2327);
2328
2329// CEBREAK ---------------------------------------------------------------------
2330static InstructionDefinition cebreak_ (
2331 ISA16_RV32IMACFD,
2332 "cebreak",
2333 (uint16_t) 0x9002,
2334 (uint16_t) 0xffff,
2335 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2336 {
2337
2338// -----------------------------------------------------------------------------
2339
2340// -----------------------------------------------------------------------------
2341
2342// -----------------------------------------------------------------------------
2343
2344// -----------------------------------------------------------------------------
2345
2346 {
2347 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2348
2349 cp.code() = std::string("//CEBREAK\n");
2350
2351// -----------------------------------------------------------------------------
2352cp.code() += "etiss_coverage_count(1, 69);\n";
2353{ // block
2354cp.code() += "etiss_coverage_count(1, 1169);\n";
2355cp.code() += "{ // block\n";
2356cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
2357cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2358cp.code() += "} // block\n";
2359} // block
2360{ // procedure
2361cp.code() += "{ // procedure\n";
2362cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 3LL);\n";
2363cp.code() += "etiss_coverage_count(2, 2787, 2785);\n";
2364cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
2365cp.code() += "} // procedure\n";
2366} // procedure
2367cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2368cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2369// -----------------------------------------------------------------------------
2370 cp.getAffectedRegisters().add("instructionPointer", 32);
2371 }
2372 {
2373 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
2374
2375 cp.code() = std::string("//CEBREAK\n");
2376
2377// -----------------------------------------------------------------------------
2378cp.code() += "return cpu->exception;\n";
2379// -----------------------------------------------------------------------------
2380 }
2381
2382 return true;
2383 },
2384 0,
2385 [] (BitArray & ba, Instruction & instr)
2386 {
2387// -----------------------------------------------------------------------------
2388
2389// -----------------------------------------------------------------------------
2390
2391 std::stringstream ss;
2392// -----------------------------------------------------------------------------
2393ss << "cebreak" << " # " << ba << (" []");
2394// -----------------------------------------------------------------------------
2395 return ss.str();
2396 }
2397);
2398
2399// CSWSP -----------------------------------------------------------------------
2400static InstructionDefinition cswsp_rs2_uimm (
2401 ISA16_RV32IMACFD,
2402 "cswsp",
2403 (uint16_t) 0xc002,
2404 (uint16_t) 0xe003,
2405 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2406 {
2407
2408// -----------------------------------------------------------------------------
2409
2410// -----------------------------------------------------------------------------
2411
2412// -----------------------------------------------------------------------------
2413etiss_uint8 rs2 = 0;
2414static BitArrayRange R_rs2_0(6, 2);
2415rs2 += R_rs2_0.read(ba) << 0;
2416etiss_uint8 uimm = 0;
2417static BitArrayRange R_uimm_6(8, 7);
2418uimm += R_uimm_6.read(ba) << 6;
2419static BitArrayRange R_uimm_2(12, 9);
2420uimm += R_uimm_2.read(ba) << 2;
2421
2422// -----------------------------------------------------------------------------
2423
2424 {
2425 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2426
2427 cp.code() = std::string("//CSWSP\n");
2428
2429// -----------------------------------------------------------------------------
2430cp.code() += "etiss_coverage_count(1, 70);\n";
2431{ // block
2432cp.code() += "etiss_coverage_count(1, 1169);\n";
2433cp.code() += "{ // block\n";
2434cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
2435cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2436cp.code() += "} // block\n";
2437} // block
2438{ // block
2439cp.code() += "etiss_coverage_count(1, 2806);\n";
2440cp.code() += "{ // block\n";
2441cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
2442cp.code() += "etiss_coverage_count(5, 2794, 2793, 2791, 2790, 2792);\n";
2443cp.code() += "etiss_uint32 mem_val_0;\n";
2444cp.code() += "mem_val_0 = (etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs2 % 32ULL) + "ULL]);\n";
2445cp.code() += "etiss_coverage_count(7, 2805, 2797, 2796, 2804, 2802, 2801, 2799);\n";
2446cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
2447cp.code() += "if (cpu->exception) { // conditional\n";
2448{ // procedure
2449cp.code() += "{ // procedure\n";
2450cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
2451cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
2452cp.code() += "} // procedure\n";
2453} // procedure
2454cp.code() += "} // conditional\n";
2455cp.code() += "} // block\n";
2456} // block
2457cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2458cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2459// -----------------------------------------------------------------------------
2460 cp.getAffectedRegisters().add("instructionPointer", 32);
2461 }
2462 {
2463 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
2464
2465 cp.code() = std::string("//CSWSP\n");
2466
2467// -----------------------------------------------------------------------------
2468cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
2469// -----------------------------------------------------------------------------
2470 }
2471
2472 return true;
2473 },
2474 0,
2475 [] (BitArray & ba, Instruction & instr)
2476 {
2477// -----------------------------------------------------------------------------
2478etiss_uint8 rs2 = 0;
2479static BitArrayRange R_rs2_0(6, 2);
2480rs2 += R_rs2_0.read(ba) << 0;
2481etiss_uint8 uimm = 0;
2482static BitArrayRange R_uimm_6(8, 7);
2483uimm += R_uimm_6.read(ba) << 6;
2484static BitArrayRange R_uimm_2(12, 9);
2485uimm += R_uimm_2.read(ba) << 2;
2486
2487// -----------------------------------------------------------------------------
2488
2489 std::stringstream ss;
2490// -----------------------------------------------------------------------------
2491ss << "cswsp" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | uimm=" + std::to_string(uimm) + "]");
2492// -----------------------------------------------------------------------------
2493 return ss.str();
2494 }
2495);
2496
2497// DII -------------------------------------------------------------------------
2498static InstructionDefinition dii_ (
2499 ISA16_RV32IMACFD,
2500 "dii",
2501 (uint16_t) 0x00,
2502 (uint16_t) 0xffff,
2503 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2504 {
2505
2506// -----------------------------------------------------------------------------
2507
2508// -----------------------------------------------------------------------------
2509
2510// -----------------------------------------------------------------------------
2511
2512// -----------------------------------------------------------------------------
2513
2514 {
2515 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2516
2517 cp.code() = std::string("//DII\n");
2518
2519// -----------------------------------------------------------------------------
2520cp.code() += "etiss_coverage_count(1, 71);\n";
2521{ // block
2522cp.code() += "etiss_coverage_count(1, 1169);\n";
2523cp.code() += "{ // block\n";
2524cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
2525cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2526cp.code() += "} // block\n";
2527} // block
2528{ // procedure
2529cp.code() += "{ // procedure\n";
2530cp.code() += "RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";
2531cp.code() += "etiss_coverage_count(2, 2809, 2807);\n";
2532cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
2533cp.code() += "} // procedure\n";
2534} // procedure
2535cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2536cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2537// -----------------------------------------------------------------------------
2538 cp.getAffectedRegisters().add("instructionPointer", 32);
2539 }
2540 {
2541 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
2542
2543 cp.code() = std::string("//DII\n");
2544
2545// -----------------------------------------------------------------------------
2546cp.code() += "return cpu->exception;\n";
2547// -----------------------------------------------------------------------------
2548 }
2549
2550 return true;
2551 },
2552 0,
2553 [] (BitArray & ba, Instruction & instr)
2554 {
2555// -----------------------------------------------------------------------------
2556
2557// -----------------------------------------------------------------------------
2558
2559 std::stringstream ss;
2560// -----------------------------------------------------------------------------
2561ss << "dii" << " # " << ba << (" []");
2562// -----------------------------------------------------------------------------
2563 return ss.str();
2564 }
2565);
ISA16_RV32IMACFD
etiss::instr::InstructionGroup ISA16_RV32IMACFD("ISA16_RV32IMACFD", 16)
candi_imm_rs1
static InstructionDefinition candi_imm_rs1(ISA16_RV32IMACFD, "candi",(uint16_t) 0x8801,(uint16_t) 0xec03, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 imm=0;static BitArrayRange R_imm_0(6, 2);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_5(12, 12);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CANDI\n");cp.code()+="etiss_coverage_count(1, 54);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2552);\n";cp.code()+="{ // block\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] & "+std::to_string(((etiss_int8)(((etiss_int8) imm)<<(2)) > >(2)))+"LL;\n";cp.code()+="etiss_coverage_count(12, 2551, 2541, 2540, 2538, 2539, 2550, 2546, 2545, 2543, 2544, 2549, 2547);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 imm=0;static BitArrayRange R_imm_0(6, 2);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_5(12, 12);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "candi"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
cswsp_rs2_uimm
static InstructionDefinition cswsp_rs2_uimm(ISA16_RV32IMACFD, "cswsp",(uint16_t) 0xc002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(8, 7);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(12, 9);uimm+=R_uimm_2.read(ba)<< 2;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSWSP\n");cp.code()+="etiss_coverage_count(1, 70);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2806);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 2794, 2793, 2791, 2790, 2792);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_uint32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(7, 2805, 2797, 2796, 2804, 2802, 2801, 2799);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CSWSP\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(8, 7);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(12, 9);uimm+=R_uimm_2.read(ba)<< 2;std::stringstream ss;ss<< "cswsp"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | uimm="+std::to_string(uimm)+"]");return ss.str();})
dii_
static InstructionDefinition dii_(ISA16_RV32IMACFD, "dii",(uint16_t) 0x00,(uint16_t) 0xffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//DII\n");cp.code()+="etiss_coverage_count(1, 71);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="etiss_coverage_count(2, 2809, 2807);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//DII\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "dii"<< " # "<< ba<<(" []");return ss.str();})
csub_rs2_rd
static InstructionDefinition csub_rs2_rd(ISA16_RV32IMACFD, "csub",(uint16_t) 0x8c01,(uint16_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSUB\n");cp.code()+="etiss_coverage_count(1, 55);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2570);\n";cp.code()+="{ // block\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] - *((RV32IMACFD*)cpu)->X["+std::to_string(rs2+8ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(14, 2569, 2557, 2556, 2554, 2555, 2568, 2562, 2561, 2559, 2560, 2567, 2566, 2564, 2565);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "csub"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | rd="+std::to_string(rd)+"]");return ss.str();})
cnop_nzimm
static InstructionDefinition cnop_nzimm(ISA16_RV32IMACFD, "cnop",(uint16_t) 0x01,(uint16_t) 0xef83, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 nzimm=0;static BitArrayRange R_nzimm_0(6, 2);nzimm+=R_nzimm_0.read(ba)<< 0;static BitArrayRange R_nzimm_5(12, 12);nzimm+=R_nzimm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CNOP\n");cp.code()+="etiss_coverage_count(1, 46);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2407);\n";cp.code()+="{ // block\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 nzimm=0;static BitArrayRange R_nzimm_0(6, 2);nzimm+=R_nzimm_0.read(ba)<< 0;static BitArrayRange R_nzimm_5(12, 12);nzimm+=R_nzimm_5.read(ba)<< 5;std::stringstream ss;ss<< "cnop"<< " # "<< ba<<(" [nzimm="+std::to_string(nzimm)+"]");return ss.str();})
caddi16sp_nzimm
static InstructionDefinition caddi16sp_nzimm(ISA16_RV32IMACFD, "caddi16sp",(uint16_t) 0x6101,(uint16_t) 0xef83, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 nzimm=0;static BitArrayRange R_nzimm_5(2, 2);nzimm+=R_nzimm_5.read(ba)<< 5;static BitArrayRange R_nzimm_7(4, 3);nzimm+=R_nzimm_7.read(ba)<< 7;static BitArrayRange R_nzimm_6(5, 5);nzimm+=R_nzimm_6.read(ba)<< 6;static BitArrayRange R_nzimm_4(6, 6);nzimm+=R_nzimm_4.read(ba)<< 4;static BitArrayRange R_nzimm_9(12, 12);nzimm+=R_nzimm_9.read(ba)<< 9;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CADDI16SP\n");cp.code()+="etiss_coverage_count(1, 50);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2464);\n";if(nzimm) { cp.code()+="etiss_coverage_count(1, 2465);\n";cp.code()+="*((RV32IMACFD*)cpu)->X[2ULL] = *((RV32IMACFD*)cpu)->X[2ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) nzimm)<<(6)) > >(6)))+"LL;\n";cp.code()+="etiss_coverage_count(8, 2476, 2468, 2467, 2475, 2471, 2470, 2474, 2472);\n";} else { { cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="etiss_coverage_count(2, 2479, 2477);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} } cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CADDI16SP\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 nzimm=0;static BitArrayRange R_nzimm_5(2, 2);nzimm+=R_nzimm_5.read(ba)<< 5;static BitArrayRange R_nzimm_7(4, 3);nzimm+=R_nzimm_7.read(ba)<< 7;static BitArrayRange R_nzimm_6(5, 5);nzimm+=R_nzimm_6.read(ba)<< 6;static BitArrayRange R_nzimm_4(6, 6);nzimm+=R_nzimm_4.read(ba)<< 4;static BitArrayRange R_nzimm_9(12, 12);nzimm+=R_nzimm_9.read(ba)<< 9;std::stringstream ss;ss<< "caddi16sp"<< " # "<< ba<<(" [nzimm="+std::to_string(nzimm)+"]");return ss.str();})
caddi4spn_rd_imm
static InstructionDefinition caddi4spn_rd_imm(ISA16_RV32IMACFD, "caddi4spn",(uint16_t) 0x00,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_3(5, 5);imm+=R_imm_3.read(ba)<< 3;static BitArrayRange R_imm_2(6, 6);imm+=R_imm_2.read(ba)<< 2;static BitArrayRange R_imm_6(10, 7);imm+=R_imm_6.read(ba)<< 6;static BitArrayRange R_imm_4(12, 11);imm+=R_imm_4.read(ba)<< 4;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CADDI4SPN\n");cp.code()+="etiss_coverage_count(1, 42);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2327);\n";if(imm) { cp.code()+="etiss_coverage_count(1, 2328);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = *((RV32IMACFD*)cpu)->X[2ULL] + "+std::to_string(imm)+"ULL;\n";cp.code()+="etiss_coverage_count(9, 2339, 2333, 2332, 2330, 2331, 2338, 2336, 2335, 2337);\n";} else { { cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="etiss_coverage_count(2, 2342, 2340);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} } cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CADDI4SPN\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_3(5, 5);imm+=R_imm_3.read(ba)<< 3;static BitArrayRange R_imm_2(6, 6);imm+=R_imm_2.read(ba)<< 2;static BitArrayRange R_imm_6(10, 7);imm+=R_imm_6.read(ba)<< 6;static BitArrayRange R_imm_4(12, 11);imm+=R_imm_4.read(ba)<< 4;std::stringstream ss;ss<< "caddi4spn"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | imm="+std::to_string(imm)+"]");return ss.str();})
clw_rd_uimm_rs1
static InstructionDefinition clw_rd_uimm_rs1(ISA16_RV32IMACFD, "clw",(uint16_t) 0x4000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(5, 5);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 6);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CLW\n");cp.code()+="etiss_coverage_count(1, 43);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2363);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(7, 2351, 2350, 2348, 2347, 2345, 2346, 2349);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = (etiss_int32)(mem_val_0);\n";cp.code()+="etiss_coverage_count(8, 2362, 2356, 2355, 2353, 2354, 2361, 2359, 2358);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CLW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(5, 5);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 6);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;std::stringstream ss;ss<< "clw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | uimm="+std::to_string(uimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
cjal_imm
static InstructionDefinition cjal_imm(ISA16_RV32IMACFD, "cjal",(uint16_t) 0x2001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_5(2, 2);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_1(5, 3);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_7(6, 6);imm+=R_imm_7.read(ba)<< 7;static BitArrayRange R_imm_6(7, 7);imm+=R_imm_6.read(ba)<< 6;static BitArrayRange R_imm_10(8, 8);imm+=R_imm_10.read(ba)<< 10;static BitArrayRange R_imm_8(10, 9);imm+=R_imm_8.read(ba)<< 8;static BitArrayRange R_imm_4(11, 11);imm+=R_imm_4.read(ba)<< 4;static BitArrayRange R_imm_11(12, 12);imm+=R_imm_11.read(ba)<< 11;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CJAL\n");cp.code()+="etiss_coverage_count(1, 47);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2422);\n";cp.code()+="{ // block\n";cp.code()+="*((RV32IMACFD*)cpu)->X[1ULL] = "+std::to_string(ic.current_address_+2ULL)+"ULL;\n";cp.code()+="etiss_coverage_count(6, 2414, 2410, 2409, 2413, 2411, 2412);\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))+"LL;\n";cp.code()+="etiss_coverage_count(6, 2421, 2415, 2420, 2416, 2419, 2417);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CJAL\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_5(2, 2);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_1(5, 3);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_7(6, 6);imm+=R_imm_7.read(ba)<< 7;static BitArrayRange R_imm_6(7, 7);imm+=R_imm_6.read(ba)<< 6;static BitArrayRange R_imm_10(8, 8);imm+=R_imm_10.read(ba)<< 10;static BitArrayRange R_imm_8(10, 9);imm+=R_imm_8.read(ba)<< 8;static BitArrayRange R_imm_4(11, 11);imm+=R_imm_4.read(ba)<< 4;static BitArrayRange R_imm_11(12, 12);imm+=R_imm_11.read(ba)<< 11;std::stringstream ss;ss<< "cjal"<< " # "<< ba<<(" [imm="+std::to_string(imm)+"]");return ss.str();})
cbeqz_imm_rs1
static InstructionDefinition cbeqz_imm_rs1(ISA16_RV32IMACFD, "cbeqz",(uint16_t) 0xc001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_5(2, 2);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_1(4, 3);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_6(6, 5);imm+=R_imm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_3(11, 10);imm+=R_imm_3.read(ba)<< 3;static BitArrayRange R_imm_8(12, 12);imm+=R_imm_8.read(ba)<< 8;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CBEQZ\n");cp.code()+="etiss_coverage_count(1, 60);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2632);\n";cp.code()+="if (*((RV32IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] == 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(6, 2639, 2637, 2636, 2634, 2635, 2638);\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(7)) > >(7)))+"LL;\n";cp.code()+="etiss_coverage_count(6, 2646, 2640, 2645, 2641, 2644, 2642);\n";cp.code()+="} // conditional\n";cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CBEQZ\n");cp.code()+="if (cpu->nextPc != "+std::to_string(ic.current_address_+2)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_5(2, 2);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_1(4, 3);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_6(6, 5);imm+=R_imm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_3(11, 10);imm+=R_imm_3.read(ba)<< 3;static BitArrayRange R_imm_8(12, 12);imm+=R_imm_8.read(ba)<< 8;std::stringstream ss;ss<< "cbeqz"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
__reserved_clui_rd
static InstructionDefinition __reserved_clui_rd(ISA16_RV32IMACFD, "__reserved_clui",(uint16_t) 0x6001,(uint16_t) 0xf07f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//__reserved_clui\n");cp.code()+="etiss_coverage_count(1, 51);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="etiss_coverage_count(2, 2482, 2480);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//__reserved_clui\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "__reserved_clui"<< " # "<< ba<<(" [rd="+std::to_string(rd)+"]");return ss.str();})
cebreak_
static InstructionDefinition cebreak_(ISA16_RV32IMACFD, "cebreak",(uint16_t) 0x9002,(uint16_t) 0xffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CEBREAK\n");cp.code()+="etiss_coverage_count(1, 69);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 3LL);\n";cp.code()+="etiss_coverage_count(2, 2787, 2785);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CEBREAK\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "cebreak"<< " # "<< ba<<(" []");return ss.str();})
clui_imm_rd
static InstructionDefinition clui_imm_rd(ISA16_RV32IMACFD, "clui",(uint16_t) 0x6001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint32 imm=0;static BitArrayRange R_imm_12(6, 2);imm+=R_imm_12.read(ba)<< 12;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_imm_17(12, 12);imm+=R_imm_17.read(ba)<< 17;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CLUI\n");cp.code()+="etiss_coverage_count(1, 49);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2463);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2440);\n";if(imm==0LL) { cp.code()+="etiss_coverage_count(3, 2443, 2441, 2442);\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2LL);\n";cp.code()+="etiss_coverage_count(2, 2446, 2444);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} } cp.code()+="etiss_coverage_count(1, 2447);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2453, 2450, 2448, 2451, 2452);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string(((etiss_int32)(((etiss_int32) imm)<<(14)) > >(14)))+"LL;\n";cp.code()+="etiss_coverage_count(6, 2462, 2458, 2457, 2455, 2461, 2459);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CLUI\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint32 imm=0;static BitArrayRange R_imm_12(6, 2);imm+=R_imm_12.read(ba)<< 12;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_imm_17(12, 12);imm+=R_imm_17.read(ba)<< 17;std::stringstream ss;ss<< "clui"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rd="+std::to_string(rd)+"]");return ss.str();})
clwsp_uimm_rd
static InstructionDefinition clwsp_uimm_rd(ISA16_RV32IMACFD, "clwsp",(uint16_t) 0x4002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(3, 2);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 4);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_uimm_5(12, 12);uimm+=R_uimm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CLWSP\n");cp.code()+="etiss_coverage_count(1, 63);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2703);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2677);\n";if(rd % 32ULL) { cp.code()+="etiss_coverage_count(2, 2680, 2678);\n";{ cp.code()+="etiss_coverage_count(1, 2699);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, *((RV32IMACFD*)cpu)->X[2ULL] + "+std::to_string(uimm)+"ULL, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_int32 res = mem_val_0;\n";cp.code()+="etiss_coverage_count(6, 2689, 2688, 2687, 2685, 2684, 2686);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_int32)(res);\n";cp.code()+="etiss_coverage_count(6, 2698, 2694, 2693, 2691, 2697, 2695);\n";cp.code()+="} // block\n";} } else { { cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2ULL);\n";cp.code()+="etiss_coverage_count(3, 2702, 2700, 2701);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CLWSP\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(3, 2);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 4);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_uimm_5(12, 12);uimm+=R_uimm_5.read(ba)<< 5;std::stringstream ss;ss<< "clwsp"<< " # "<< ba<<(" [uimm="+std::to_string(uimm)+" | rd="+std::to_string(rd)+"]");return ss.str();})
csrli_shamt_rs1
static InstructionDefinition csrli_shamt_rs1(ISA16_RV32IMACFD, "csrli",(uint16_t) 0x8001,(uint16_t) 0xfc03, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(6, 2);shamt+=R_shamt_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRLI\n");cp.code()+="etiss_coverage_count(1, 52);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2496);\n";cp.code()+="{ // block\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] >> "+std::to_string(shamt)+"ULL;\n";cp.code()+="etiss_coverage_count(11, 2495, 2487, 2486, 2484, 2485, 2494, 2492, 2491, 2489, 2490, 2493);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(6, 2);shamt+=R_shamt_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "csrli"<< " # "<< ba<<(" [shamt="+std::to_string(shamt)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
cbnez_imm_rs1
static InstructionDefinition cbnez_imm_rs1(ISA16_RV32IMACFD, "cbnez",(uint16_t) 0xe001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_5(2, 2);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_1(4, 3);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_6(6, 5);imm+=R_imm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_3(11, 10);imm+=R_imm_3.read(ba)<< 3;static BitArrayRange R_imm_8(12, 12);imm+=R_imm_8.read(ba)<< 8;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CBNEZ\n");cp.code()+="etiss_coverage_count(1, 61);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2647);\n";cp.code()+="if (*((RV32IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] != 0LL) { // conditional\n";cp.code()+="etiss_coverage_count(6, 2654, 2652, 2651, 2649, 2650, 2653);\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(7)) > >(7)))+"LL;\n";cp.code()+="etiss_coverage_count(6, 2661, 2655, 2660, 2656, 2659, 2657);\n";cp.code()+="} // conditional\n";cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CBNEZ\n");cp.code()+="if (cpu->nextPc != "+std::to_string(ic.current_address_+2)+"ULL) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_5(2, 2);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_1(4, 3);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_6(6, 5);imm+=R_imm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_3(11, 10);imm+=R_imm_3.read(ba)<< 3;static BitArrayRange R_imm_8(12, 12);imm+=R_imm_8.read(ba)<< 8;std::stringstream ss;ss<< "cbnez"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
cmv_rs2_rd
static InstructionDefinition cmv_rs2_rd(ISA16_RV32IMACFD, "cmv",(uint16_t) 0x8002,(uint16_t) 0xf003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CMV\n");cp.code()+="etiss_coverage_count(1, 64);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2704);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2710, 2707, 2705, 2708, 2709);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(7, 2721, 2715, 2714, 2712, 2720, 2719, 2717);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "cmv"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | rd="+std::to_string(rd)+"]");return ss.str();})
caddi_imm_rs1
static InstructionDefinition caddi_imm_rs1(ISA16_RV32IMACFD, "caddi",(uint16_t) 0x01,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 imm=0;static BitArrayRange R_imm_0(6, 2);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_5(12, 12);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CADDI\n");cp.code()+="etiss_coverage_count(1, 45);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2385);\n";if((rs1 % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2391, 2388, 2386, 2389, 2390);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int8)(((etiss_int8) imm)<<(2)) > >(2)))+"LL;\n";cp.code()+="etiss_coverage_count(10, 2406, 2396, 2395, 2393, 2405, 2401, 2400, 2398, 2404, 2402);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 imm=0;static BitArrayRange R_imm_0(6, 2);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_imm_5(12, 12);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "caddi"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
cxor_rs2_rd
static InstructionDefinition cxor_rs2_rd(ISA16_RV32IMACFD, "cxor",(uint16_t) 0x8c21,(uint16_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CXOR\n");cp.code()+="etiss_coverage_count(1, 56);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2588);\n";cp.code()+="{ // block\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] ^ *((RV32IMACFD*)cpu)->X["+std::to_string(rs2+8ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(14, 2587, 2575, 2574, 2572, 2573, 2586, 2580, 2579, 2577, 2578, 2585, 2584, 2582, 2583);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "cxor"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | rd="+std::to_string(rd)+"]");return ss.str();})
__reserved_cmv_
static InstructionDefinition __reserved_cmv_(ISA16_RV32IMACFD, "__reserved_cmv",(uint16_t) 0x8002,(uint16_t) 0xffff, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { { CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//__reserved_cmv\n");cp.code()+="etiss_coverage_count(1, 66);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2ULL);\n";cp.code()+="etiss_coverage_count(3, 2739, 2737, 2738);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//__reserved_cmv\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { std::stringstream ss;ss<< "__reserved_cmv"<< " # "<< ba<<(" []");return ss.str();})
cslli_nzuimm_rs1
static InstructionDefinition cslli_nzuimm_rs1(ISA16_RV32IMACFD, "cslli",(uint16_t) 0x02,(uint16_t) 0xf003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 nzuimm=0;static BitArrayRange R_nzuimm_0(6, 2);nzuimm+=R_nzuimm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSLLI\n");cp.code()+="etiss_coverage_count(1, 62);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2662);\n";if(nzuimm) { cp.code()+="etiss_coverage_count(1, 2663);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] << "+std::to_string(nzuimm)+"ULL;\n";cp.code()+="etiss_coverage_count(9, 2676, 2668, 2667, 2665, 2675, 2673, 2672, 2670, 2674);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 nzuimm=0;static BitArrayRange R_nzuimm_0(6, 2);nzuimm+=R_nzuimm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "cslli"<< " # "<< ba<<(" [nzuimm="+std::to_string(nzuimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
cjalr_rs1
static InstructionDefinition cjalr_rs1(ISA16_RV32IMACFD, "cjalr",(uint16_t) 0x9002,(uint16_t) 0xf07f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CJALR\n");cp.code()+="etiss_coverage_count(1, 68);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2784);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 new_pc = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(4, 2770, 2769, 2768, 2766);\n";cp.code()+="*((RV32IMACFD*)cpu)->X[1ULL] = "+std::to_string(ic.current_address_+2ULL)+"ULL;\n";cp.code()+="etiss_coverage_count(6, 2777, 2773, 2772, 2776, 2774, 2775);\n";cp.code()+="cpu->nextPc = new_pc & -2LL;\n";cp.code()+="etiss_coverage_count(4, 2783, 2778, 2782, 2779);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CJALR\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "cjalr"<< " # "<< ba<<(" [rs1="+std::to_string(rs1)+"]");return ss.str();})
cand_rs2_rd
static InstructionDefinition cand_rs2_rd(ISA16_RV32IMACFD, "cand",(uint16_t) 0x8c61,(uint16_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CAND\n");cp.code()+="etiss_coverage_count(1, 58);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2624);\n";cp.code()+="{ // block\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] & *((RV32IMACFD*)cpu)->X["+std::to_string(rs2+8ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(14, 2623, 2611, 2610, 2608, 2609, 2622, 2616, 2615, 2613, 2614, 2621, 2620, 2618, 2619);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "cand"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | rd="+std::to_string(rd)+"]");return ss.str();})
cjr_rs1
static InstructionDefinition cjr_rs1(ISA16_RV32IMACFD, "cjr",(uint16_t) 0x8002,(uint16_t) 0xf07f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CJR\n");cp.code()+="etiss_coverage_count(1, 65);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2722);\n";if(rs1) { cp.code()+="etiss_coverage_count(1, 2723);\n";cp.code()+="cpu->nextPc = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] & -2LL;\n";cp.code()+="etiss_coverage_count(6, 2733, 2724, 2732, 2729, 2728, 2726);\n";} else { { cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_raise(cpu, system, plugin_pointers, 0LL, 2ULL);\n";cp.code()+="etiss_coverage_count(3, 2736, 2734, 2735);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} } cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CJR\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(11, 7);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "cjr"<< " # "<< ba<<(" [rs1="+std::to_string(rs1)+"]");return ss.str();})
cadd_rs2_rd
static InstructionDefinition cadd_rs2_rd(ISA16_RV32IMACFD, "cadd",(uint16_t) 0x9002,(uint16_t) 0xf003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CADD\n");cp.code()+="etiss_coverage_count(1, 67);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 2740);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2746, 2743, 2741, 2744, 2745);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] + *((RV32IMACFD*)cpu)->X["+std::to_string(rs2 % 32ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(11, 2763, 2751, 2750, 2748, 2762, 2756, 2755, 2753, 2761, 2760, 2758);\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "cadd"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | rd="+std::to_string(rd)+"]");return ss.str();})
cj_imm
static InstructionDefinition cj_imm(ISA16_RV32IMACFD, "cj",(uint16_t) 0xa001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_5(2, 2);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_1(5, 3);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_7(6, 6);imm+=R_imm_7.read(ba)<< 7;static BitArrayRange R_imm_6(7, 7);imm+=R_imm_6.read(ba)<< 6;static BitArrayRange R_imm_10(8, 8);imm+=R_imm_10.read(ba)<< 10;static BitArrayRange R_imm_8(10, 9);imm+=R_imm_8.read(ba)<< 8;static BitArrayRange R_imm_4(11, 11);imm+=R_imm_4.read(ba)<< 4;static BitArrayRange R_imm_11(12, 12);imm+=R_imm_11.read(ba)<< 11;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CJ\n");cp.code()+="etiss_coverage_count(1, 59);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))+"LL;\n";cp.code()+="etiss_coverage_count(6, 2631, 2625, 2630, 2626, 2629, 2627);\n";cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CJ\n");cp.code()+="return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_5(2, 2);imm+=R_imm_5.read(ba)<< 5;static BitArrayRange R_imm_1(5, 3);imm+=R_imm_1.read(ba)<< 1;static BitArrayRange R_imm_7(6, 6);imm+=R_imm_7.read(ba)<< 7;static BitArrayRange R_imm_6(7, 7);imm+=R_imm_6.read(ba)<< 6;static BitArrayRange R_imm_10(8, 8);imm+=R_imm_10.read(ba)<< 10;static BitArrayRange R_imm_8(10, 9);imm+=R_imm_8.read(ba)<< 8;static BitArrayRange R_imm_4(11, 11);imm+=R_imm_4.read(ba)<< 4;static BitArrayRange R_imm_11(12, 12);imm+=R_imm_11.read(ba)<< 11;std::stringstream ss;ss<< "cj"<< " # "<< ba<<(" [imm="+std::to_string(imm)+"]");return ss.str();})
csrai_shamt_rs1
static InstructionDefinition csrai_shamt_rs1(ISA16_RV32IMACFD, "csrai",(uint16_t) 0x8401,(uint16_t) 0xfc03, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(6, 2);shamt+=R_shamt_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSRAI\n");cp.code()+="etiss_coverage_count(1, 53);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2536);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2497);\n";if(shamt) { cp.code()+="etiss_coverage_count(1, 2498);\n";{ cp.code()+="etiss_coverage_count(1, 2518);\n";cp.code()+="{ // block\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] = ((etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL])) >> "+std::to_string(shamt)+"ULL;\n";cp.code()+="etiss_coverage_count(13, 2517, 2506, 2505, 2503, 2504, 2516, 2513, 2511, 2510, 2508, 2509, 2514, 2515);\n";cp.code()+="} // block\n";} } cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 shamt=0;static BitArrayRange R_shamt_0(6, 2);shamt+=R_shamt_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "csrai"<< " # "<< ba<<(" [shamt="+std::to_string(shamt)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
cli_imm_rd
static InstructionDefinition cli_imm_rd(ISA16_RV32IMACFD, "cli",(uint16_t) 0x4001,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 imm=0;static BitArrayRange R_imm_0(6, 2);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_imm_5(12, 12);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CLI\n");cp.code()+="etiss_coverage_count(1, 48);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2439);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 2423);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 2429, 2426, 2424, 2427, 2428);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = "+std::to_string(((etiss_int8)(((etiss_int8) imm)<<(2)) > >(2)))+"LL;\n";cp.code()+="etiss_coverage_count(6, 2438, 2434, 2433, 2431, 2437, 2435);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 imm=0;static BitArrayRange R_imm_0(6, 2);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_imm_5(12, 12);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "cli"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rd="+std::to_string(rd)+"]");return ss.str();})
csw_rs2_uimm_rs1
static InstructionDefinition csw_rs2_uimm_rs1(ISA16_RV32IMACFD, "csw",(uint16_t) 0xc000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(5, 5);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 6);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CSW\n");cp.code()+="etiss_coverage_count(1, 44);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2384);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 load_address = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(7, 2372, 2371, 2369, 2368, 2366, 2367, 2370);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_int32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs2+8ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(8, 2383, 2375, 2374, 2382, 2380, 2379, 2377, 2378);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, load_address, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CSW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(5, 5);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 6);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;std::stringstream ss;ss<< "csw"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | uimm="+std::to_string(uimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
cor_rs2_rd
static InstructionDefinition cor_rs2_rd(ISA16_RV32IMACFD, "cor",(uint16_t) 0x8c41,(uint16_t) 0xfc63, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//COR\n");cp.code()+="etiss_coverage_count(1, 57);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 2606);\n";cp.code()+="{ // block\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] = *((RV32IMACFD*)cpu)->X["+std::to_string(rd+8ULL)+"ULL] | *((RV32IMACFD*)cpu)->X["+std::to_string(rs2+8ULL)+"ULL];\n";cp.code()+="etiss_coverage_count(14, 2605, 2593, 2592, 2590, 2591, 2604, 2598, 2597, 2595, 2596, 2603, 2602, 2600, 2601);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rd=0;static BitArrayRange R_rd_0(9, 7);rd+=R_rd_0.read(ba)<< 0;std::stringstream ss;ss<< "cor"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | rd="+std::to_string(rd)+"]");return ss.str();})
etiss_int16
int16_t etiss_int16
Definition types.h:89
etiss_uint32
uint32_t etiss_uint32
Definition types.h:93
etiss_int8
int8_t etiss_int8
Definition types.h:86
etiss_uint8
uint8_t etiss_uint8
Definition types.h:87
etiss_int32
int32_t etiss_int32
Definition types.h:92
etiss_uint16
uint16_t etiss_uint16
Definition types.h:90
etiss::CodePart
Contains a small code snipped.
Definition CodePart.h:386
etiss::CodePart::APPENDEDRETURNINGREQUIRED
@ APPENDEDRETURNINGREQUIRED
Definition CodePart.h:402
etiss::CodePart::code
std::string & code()
Definition CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition Benchmark.h:53
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