ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV32IMACFD_RV32FInstr.cpp
Go to the documentation of this file.
1 
8 #include "RV32IMACFDArch.h"
9 #include "RV32IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // FLW -------------------------------------------------------------------------
16 static InstructionDefinition flw_rd_rs1_imm (
17  ISA32_RV32IMACFD,
18  "flw",
19  (uint32_t) 0x002007,
20  (uint32_t) 0x00707f,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 etiss_uint8 rd = 0;
30 static BitArrayRange R_rd_0(11, 7);
31 rd += R_rd_0.read(ba) << 0;
32 etiss_uint8 rs1 = 0;
33 static BitArrayRange R_rs1_0(19, 15);
34 rs1 += R_rs1_0.read(ba) << 0;
35 etiss_uint16 imm = 0;
36 static BitArrayRange R_imm_0(31, 20);
37 imm += R_imm_0.read(ba) << 0;
38 
39 // -----------------------------------------------------------------------------
40 
41  {
42  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
43 
44  cp.code() = std::string("//FLW\n");
45 
46 // -----------------------------------------------------------------------------
47 { // block
48 cp.code() += "{ // block\n";
49 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
50 cp.code() += "} // block\n";
51 } // block
52 { // block
53 cp.code() += "{ // block\n";
54 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
55 cp.code() += "etiss_uint32 mem_val_0;\n";
56 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
57 cp.code() += "if (cpu->exception) { // conditional\n";
58 { // procedure
59 cp.code() += "{ // procedure\n";
60 cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
61 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
62 cp.code() += "} // procedure\n";
63 } // procedure
64 cp.code() += "} // conditional\n";
65 cp.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
66 { // block
67 cp.code() += "{ // block\n";
68 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
69 cp.code() += "} // block\n";
70 } // block
71 cp.code() += "} // block\n";
72 } // block
73 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
74 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
75 // -----------------------------------------------------------------------------
76  cp.getAffectedRegisters().add("instructionPointer", 32);
77  }
78  {
79  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
80 
81  cp.code() = std::string("//FLW\n");
82 
83 // -----------------------------------------------------------------------------
84 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
85 // -----------------------------------------------------------------------------
86  }
87 
88  return true;
89  },
90  0,
91  [] (BitArray & ba, Instruction & instr)
92  {
93 // -----------------------------------------------------------------------------
94 etiss_uint8 rd = 0;
95 static BitArrayRange R_rd_0(11, 7);
96 rd += R_rd_0.read(ba) << 0;
97 etiss_uint8 rs1 = 0;
98 static BitArrayRange R_rs1_0(19, 15);
99 rs1 += R_rs1_0.read(ba) << 0;
100 etiss_uint16 imm = 0;
101 static BitArrayRange R_imm_0(31, 20);
102 imm += R_imm_0.read(ba) << 0;
103 
104 // -----------------------------------------------------------------------------
105 
106  std::stringstream ss;
107 // -----------------------------------------------------------------------------
108 ss << "flw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
109 // -----------------------------------------------------------------------------
110  return ss.str();
111  }
112 );
113 
114 // FSW -------------------------------------------------------------------------
115 static InstructionDefinition fsw_imm_rs1_rs2 (
116  ISA32_RV32IMACFD,
117  "fsw",
118  (uint32_t) 0x002027,
119  (uint32_t) 0x00707f,
120  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
121  {
122 
123 // -----------------------------------------------------------------------------
124 
125 // -----------------------------------------------------------------------------
126 
127 // -----------------------------------------------------------------------------
128 etiss_uint16 imm = 0;
129 static BitArrayRange R_imm_0(11, 7);
130 imm += R_imm_0.read(ba) << 0;
131 etiss_uint8 rs1 = 0;
132 static BitArrayRange R_rs1_0(19, 15);
133 rs1 += R_rs1_0.read(ba) << 0;
134 etiss_uint8 rs2 = 0;
135 static BitArrayRange R_rs2_0(24, 20);
136 rs2 += R_rs2_0.read(ba) << 0;
137 static BitArrayRange R_imm_5(31, 25);
138 imm += R_imm_5.read(ba) << 5;
139 
140 // -----------------------------------------------------------------------------
141 
142  {
143  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
144 
145  cp.code() = std::string("//FSW\n");
146 
147 // -----------------------------------------------------------------------------
148 { // block
149 cp.code() += "{ // block\n";
150 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
151 cp.code() += "} // block\n";
152 } // block
153 { // block
154 cp.code() += "{ // block\n";
155 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
156 cp.code() += "etiss_uint32 mem_val_0;\n";
157 cp.code() += "mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
158 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
159 cp.code() += "if (cpu->exception) { // conditional\n";
160 { // procedure
161 cp.code() += "{ // procedure\n";
162 cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
163 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
164 cp.code() += "} // procedure\n";
165 } // procedure
166 cp.code() += "} // conditional\n";
167 cp.code() += "} // block\n";
168 } // block
169 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
170 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
171 // -----------------------------------------------------------------------------
172  cp.getAffectedRegisters().add("instructionPointer", 32);
173  }
174  {
175  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
176 
177  cp.code() = std::string("//FSW\n");
178 
179 // -----------------------------------------------------------------------------
180 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
181 // -----------------------------------------------------------------------------
182  }
183 
184  return true;
185  },
186  0,
187  [] (BitArray & ba, Instruction & instr)
188  {
189 // -----------------------------------------------------------------------------
190 etiss_uint16 imm = 0;
191 static BitArrayRange R_imm_0(11, 7);
192 imm += R_imm_0.read(ba) << 0;
193 etiss_uint8 rs1 = 0;
194 static BitArrayRange R_rs1_0(19, 15);
195 rs1 += R_rs1_0.read(ba) << 0;
196 etiss_uint8 rs2 = 0;
197 static BitArrayRange R_rs2_0(24, 20);
198 rs2 += R_rs2_0.read(ba) << 0;
199 static BitArrayRange R_imm_5(31, 25);
200 imm += R_imm_5.read(ba) << 5;
201 
202 // -----------------------------------------------------------------------------
203 
204  std::stringstream ss;
205 // -----------------------------------------------------------------------------
206 ss << "fsw" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
207 // -----------------------------------------------------------------------------
208  return ss.str();
209  }
210 );
211 
212 // FMADD_S ---------------------------------------------------------------------
213 static InstructionDefinition fmadd_s_rd_rm_rs1_rs2_rs3 (
214  ISA32_RV32IMACFD,
215  "fmadd_s",
216  (uint32_t) 0x000043,
217  (uint32_t) 0x600007f,
218  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
219  {
220 
221 // -----------------------------------------------------------------------------
222 
223 // -----------------------------------------------------------------------------
224 
225 // -----------------------------------------------------------------------------
226 etiss_uint8 rd = 0;
227 static BitArrayRange R_rd_0(11, 7);
228 rd += R_rd_0.read(ba) << 0;
229 etiss_uint8 rm = 0;
230 static BitArrayRange R_rm_0(14, 12);
231 rm += R_rm_0.read(ba) << 0;
232 etiss_uint8 rs1 = 0;
233 static BitArrayRange R_rs1_0(19, 15);
234 rs1 += R_rs1_0.read(ba) << 0;
235 etiss_uint8 rs2 = 0;
236 static BitArrayRange R_rs2_0(24, 20);
237 rs2 += R_rs2_0.read(ba) << 0;
238 etiss_uint8 rs3 = 0;
239 static BitArrayRange R_rs3_0(31, 27);
240 rs3 += R_rs3_0.read(ba) << 0;
241 
242 // -----------------------------------------------------------------------------
243 
244  {
245  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
246 
247  cp.code() = std::string("//FMADD_S\n");
248 
249 // -----------------------------------------------------------------------------
250 { // block
251 cp.code() += "{ // block\n";
252 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
253 cp.code() += "} // block\n";
254 } // block
255 { // block
256 cp.code() += "{ // block\n";
257 { // block
258 cp.code() += "{ // block\n";
259 cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0LL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
260 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
261 cp.code() += "} // block\n";
262 } // block
263 cp.code() += "etiss_uint32 flags = fget_flags();\n";
264 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
265 cp.code() += "} // block\n";
266 } // block
267 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
268 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
269 // -----------------------------------------------------------------------------
270  cp.getAffectedRegisters().add("instructionPointer", 32);
271  }
272 
273  return true;
274  },
275  0,
276  [] (BitArray & ba, Instruction & instr)
277  {
278 // -----------------------------------------------------------------------------
279 etiss_uint8 rd = 0;
280 static BitArrayRange R_rd_0(11, 7);
281 rd += R_rd_0.read(ba) << 0;
282 etiss_uint8 rm = 0;
283 static BitArrayRange R_rm_0(14, 12);
284 rm += R_rm_0.read(ba) << 0;
285 etiss_uint8 rs1 = 0;
286 static BitArrayRange R_rs1_0(19, 15);
287 rs1 += R_rs1_0.read(ba) << 0;
288 etiss_uint8 rs2 = 0;
289 static BitArrayRange R_rs2_0(24, 20);
290 rs2 += R_rs2_0.read(ba) << 0;
291 etiss_uint8 rs3 = 0;
292 static BitArrayRange R_rs3_0(31, 27);
293 rs3 += R_rs3_0.read(ba) << 0;
294 
295 // -----------------------------------------------------------------------------
296 
297  std::stringstream ss;
298 // -----------------------------------------------------------------------------
299 ss << "fmadd_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]");
300 // -----------------------------------------------------------------------------
301  return ss.str();
302  }
303 );
304 
305 // FMSUB_S ---------------------------------------------------------------------
306 static InstructionDefinition fmsub_s_rd_rm_rs1_rs2_rs3 (
307  ISA32_RV32IMACFD,
308  "fmsub_s",
309  (uint32_t) 0x000047,
310  (uint32_t) 0x600007f,
311  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
312  {
313 
314 // -----------------------------------------------------------------------------
315 
316 // -----------------------------------------------------------------------------
317 
318 // -----------------------------------------------------------------------------
319 etiss_uint8 rd = 0;
320 static BitArrayRange R_rd_0(11, 7);
321 rd += R_rd_0.read(ba) << 0;
322 etiss_uint8 rm = 0;
323 static BitArrayRange R_rm_0(14, 12);
324 rm += R_rm_0.read(ba) << 0;
325 etiss_uint8 rs1 = 0;
326 static BitArrayRange R_rs1_0(19, 15);
327 rs1 += R_rs1_0.read(ba) << 0;
328 etiss_uint8 rs2 = 0;
329 static BitArrayRange R_rs2_0(24, 20);
330 rs2 += R_rs2_0.read(ba) << 0;
331 etiss_uint8 rs3 = 0;
332 static BitArrayRange R_rs3_0(31, 27);
333 rs3 += R_rs3_0.read(ba) << 0;
334 
335 // -----------------------------------------------------------------------------
336 
337  {
338  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
339 
340  cp.code() = std::string("//FMSUB_S\n");
341 
342 // -----------------------------------------------------------------------------
343 { // block
344 cp.code() += "{ // block\n";
345 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
346 cp.code() += "} // block\n";
347 } // block
348 { // block
349 cp.code() += "{ // block\n";
350 { // block
351 cp.code() += "{ // block\n";
352 cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
353 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
354 cp.code() += "} // block\n";
355 } // block
356 cp.code() += "etiss_uint32 flags = fget_flags();\n";
357 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
358 cp.code() += "} // block\n";
359 } // block
360 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
361 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
362 // -----------------------------------------------------------------------------
363  cp.getAffectedRegisters().add("instructionPointer", 32);
364  }
365 
366  return true;
367  },
368  0,
369  [] (BitArray & ba, Instruction & instr)
370  {
371 // -----------------------------------------------------------------------------
372 etiss_uint8 rd = 0;
373 static BitArrayRange R_rd_0(11, 7);
374 rd += R_rd_0.read(ba) << 0;
375 etiss_uint8 rm = 0;
376 static BitArrayRange R_rm_0(14, 12);
377 rm += R_rm_0.read(ba) << 0;
378 etiss_uint8 rs1 = 0;
379 static BitArrayRange R_rs1_0(19, 15);
380 rs1 += R_rs1_0.read(ba) << 0;
381 etiss_uint8 rs2 = 0;
382 static BitArrayRange R_rs2_0(24, 20);
383 rs2 += R_rs2_0.read(ba) << 0;
384 etiss_uint8 rs3 = 0;
385 static BitArrayRange R_rs3_0(31, 27);
386 rs3 += R_rs3_0.read(ba) << 0;
387 
388 // -----------------------------------------------------------------------------
389 
390  std::stringstream ss;
391 // -----------------------------------------------------------------------------
392 ss << "fmsub_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]");
393 // -----------------------------------------------------------------------------
394  return ss.str();
395  }
396 );
397 
398 // FNMADD_S --------------------------------------------------------------------
399 static InstructionDefinition fnmadd_s_rd_rm_rs1_rs2_rs3 (
400  ISA32_RV32IMACFD,
401  "fnmadd_s",
402  (uint32_t) 0x00004f,
403  (uint32_t) 0x600007f,
404  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
405  {
406 
407 // -----------------------------------------------------------------------------
408 
409 // -----------------------------------------------------------------------------
410 
411 // -----------------------------------------------------------------------------
412 etiss_uint8 rd = 0;
413 static BitArrayRange R_rd_0(11, 7);
414 rd += R_rd_0.read(ba) << 0;
415 etiss_uint8 rm = 0;
416 static BitArrayRange R_rm_0(14, 12);
417 rm += R_rm_0.read(ba) << 0;
418 etiss_uint8 rs1 = 0;
419 static BitArrayRange R_rs1_0(19, 15);
420 rs1 += R_rs1_0.read(ba) << 0;
421 etiss_uint8 rs2 = 0;
422 static BitArrayRange R_rs2_0(24, 20);
423 rs2 += R_rs2_0.read(ba) << 0;
424 etiss_uint8 rs3 = 0;
425 static BitArrayRange R_rs3_0(31, 27);
426 rs3 += R_rs3_0.read(ba) << 0;
427 
428 // -----------------------------------------------------------------------------
429 
430  {
431  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
432 
433  cp.code() = std::string("//FNMADD_S\n");
434 
435 // -----------------------------------------------------------------------------
436 { // block
437 cp.code() += "{ // block\n";
438 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
439 cp.code() += "} // block\n";
440 } // block
441 { // block
442 cp.code() += "{ // block\n";
443 { // block
444 cp.code() += "{ // block\n";
445 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
446 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
447 cp.code() += "etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]);\n";
448 cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
449 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
450 cp.code() += "} // block\n";
451 } // block
452 cp.code() += "etiss_uint32 flags = fget_flags();\n";
453 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
454 cp.code() += "} // block\n";
455 } // block
456 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
457 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
458 // -----------------------------------------------------------------------------
459  cp.getAffectedRegisters().add("instructionPointer", 32);
460  }
461 
462  return true;
463  },
464  0,
465  [] (BitArray & ba, Instruction & instr)
466  {
467 // -----------------------------------------------------------------------------
468 etiss_uint8 rd = 0;
469 static BitArrayRange R_rd_0(11, 7);
470 rd += R_rd_0.read(ba) << 0;
471 etiss_uint8 rm = 0;
472 static BitArrayRange R_rm_0(14, 12);
473 rm += R_rm_0.read(ba) << 0;
474 etiss_uint8 rs1 = 0;
475 static BitArrayRange R_rs1_0(19, 15);
476 rs1 += R_rs1_0.read(ba) << 0;
477 etiss_uint8 rs2 = 0;
478 static BitArrayRange R_rs2_0(24, 20);
479 rs2 += R_rs2_0.read(ba) << 0;
480 etiss_uint8 rs3 = 0;
481 static BitArrayRange R_rs3_0(31, 27);
482 rs3 += R_rs3_0.read(ba) << 0;
483 
484 // -----------------------------------------------------------------------------
485 
486  std::stringstream ss;
487 // -----------------------------------------------------------------------------
488 ss << "fnmadd_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]");
489 // -----------------------------------------------------------------------------
490  return ss.str();
491  }
492 );
493 
494 // FNMSUB_S --------------------------------------------------------------------
495 static InstructionDefinition fnmsub_s_rd_rm_rs1_rs2_rs3 (
496  ISA32_RV32IMACFD,
497  "fnmsub_s",
498  (uint32_t) 0x00004b,
499  (uint32_t) 0x600007f,
500  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
501  {
502 
503 // -----------------------------------------------------------------------------
504 
505 // -----------------------------------------------------------------------------
506 
507 // -----------------------------------------------------------------------------
508 etiss_uint8 rd = 0;
509 static BitArrayRange R_rd_0(11, 7);
510 rd += R_rd_0.read(ba) << 0;
511 etiss_uint8 rm = 0;
512 static BitArrayRange R_rm_0(14, 12);
513 rm += R_rm_0.read(ba) << 0;
514 etiss_uint8 rs1 = 0;
515 static BitArrayRange R_rs1_0(19, 15);
516 rs1 += R_rs1_0.read(ba) << 0;
517 etiss_uint8 rs2 = 0;
518 static BitArrayRange R_rs2_0(24, 20);
519 rs2 += R_rs2_0.read(ba) << 0;
520 etiss_uint8 rs3 = 0;
521 static BitArrayRange R_rs3_0(31, 27);
522 rs3 += R_rs3_0.read(ba) << 0;
523 
524 // -----------------------------------------------------------------------------
525 
526  {
527  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
528 
529  cp.code() = std::string("//FNMSUB_S\n");
530 
531 // -----------------------------------------------------------------------------
532 { // block
533 cp.code() += "{ // block\n";
534 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
535 cp.code() += "} // block\n";
536 } // block
537 { // block
538 cp.code() += "{ // block\n";
539 { // block
540 cp.code() += "{ // block\n";
541 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
542 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
543 cp.code() += "etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]);\n";
544 cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
545 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
546 cp.code() += "} // block\n";
547 } // block
548 cp.code() += "etiss_uint32 flags = fget_flags();\n";
549 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
550 cp.code() += "} // block\n";
551 } // block
552 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
553 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
554 // -----------------------------------------------------------------------------
555  cp.getAffectedRegisters().add("instructionPointer", 32);
556  }
557 
558  return true;
559  },
560  0,
561  [] (BitArray & ba, Instruction & instr)
562  {
563 // -----------------------------------------------------------------------------
564 etiss_uint8 rd = 0;
565 static BitArrayRange R_rd_0(11, 7);
566 rd += R_rd_0.read(ba) << 0;
567 etiss_uint8 rm = 0;
568 static BitArrayRange R_rm_0(14, 12);
569 rm += R_rm_0.read(ba) << 0;
570 etiss_uint8 rs1 = 0;
571 static BitArrayRange R_rs1_0(19, 15);
572 rs1 += R_rs1_0.read(ba) << 0;
573 etiss_uint8 rs2 = 0;
574 static BitArrayRange R_rs2_0(24, 20);
575 rs2 += R_rs2_0.read(ba) << 0;
576 etiss_uint8 rs3 = 0;
577 static BitArrayRange R_rs3_0(31, 27);
578 rs3 += R_rs3_0.read(ba) << 0;
579 
580 // -----------------------------------------------------------------------------
581 
582  std::stringstream ss;
583 // -----------------------------------------------------------------------------
584 ss << "fnmsub_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]");
585 // -----------------------------------------------------------------------------
586  return ss.str();
587  }
588 );
589 
590 // FADD_S ----------------------------------------------------------------------
591 static InstructionDefinition fadd_s_rd_rm_rs1_rs2 (
592  ISA32_RV32IMACFD,
593  "fadd_s",
594  (uint32_t) 0x000053,
595  (uint32_t) 0xfe00007f,
596  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
597  {
598 
599 // -----------------------------------------------------------------------------
600 
601 // -----------------------------------------------------------------------------
602 
603 // -----------------------------------------------------------------------------
604 etiss_uint8 rd = 0;
605 static BitArrayRange R_rd_0(11, 7);
606 rd += R_rd_0.read(ba) << 0;
607 etiss_uint8 rm = 0;
608 static BitArrayRange R_rm_0(14, 12);
609 rm += R_rm_0.read(ba) << 0;
610 etiss_uint8 rs1 = 0;
611 static BitArrayRange R_rs1_0(19, 15);
612 rs1 += R_rs1_0.read(ba) << 0;
613 etiss_uint8 rs2 = 0;
614 static BitArrayRange R_rs2_0(24, 20);
615 rs2 += R_rs2_0.read(ba) << 0;
616 
617 // -----------------------------------------------------------------------------
618 
619  {
620  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
621 
622  cp.code() = std::string("//FADD_S\n");
623 
624 // -----------------------------------------------------------------------------
625 { // block
626 cp.code() += "{ // block\n";
627 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
628 cp.code() += "} // block\n";
629 } // block
630 { // block
631 cp.code() += "{ // block\n";
632 { // block
633 cp.code() += "{ // block\n";
634 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
635 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
636 cp.code() += "etiss_uint32 res = fadd_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
637 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
638 cp.code() += "} // block\n";
639 } // block
640 cp.code() += "etiss_uint32 flags = fget_flags();\n";
641 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
642 cp.code() += "} // block\n";
643 } // block
644 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
645 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
646 // -----------------------------------------------------------------------------
647  cp.getAffectedRegisters().add("instructionPointer", 32);
648  }
649 
650  return true;
651  },
652  0,
653  [] (BitArray & ba, Instruction & instr)
654  {
655 // -----------------------------------------------------------------------------
656 etiss_uint8 rd = 0;
657 static BitArrayRange R_rd_0(11, 7);
658 rd += R_rd_0.read(ba) << 0;
659 etiss_uint8 rm = 0;
660 static BitArrayRange R_rm_0(14, 12);
661 rm += R_rm_0.read(ba) << 0;
662 etiss_uint8 rs1 = 0;
663 static BitArrayRange R_rs1_0(19, 15);
664 rs1 += R_rs1_0.read(ba) << 0;
665 etiss_uint8 rs2 = 0;
666 static BitArrayRange R_rs2_0(24, 20);
667 rs2 += R_rs2_0.read(ba) << 0;
668 
669 // -----------------------------------------------------------------------------
670 
671  std::stringstream ss;
672 // -----------------------------------------------------------------------------
673 ss << "fadd_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
674 // -----------------------------------------------------------------------------
675  return ss.str();
676  }
677 );
678 
679 // FSUB_S ----------------------------------------------------------------------
680 static InstructionDefinition fsub_s_rd_rm_rs1_rs2 (
681  ISA32_RV32IMACFD,
682  "fsub_s",
683  (uint32_t) 0x8000053,
684  (uint32_t) 0xfe00007f,
685  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
686  {
687 
688 // -----------------------------------------------------------------------------
689 
690 // -----------------------------------------------------------------------------
691 
692 // -----------------------------------------------------------------------------
693 etiss_uint8 rd = 0;
694 static BitArrayRange R_rd_0(11, 7);
695 rd += R_rd_0.read(ba) << 0;
696 etiss_uint8 rm = 0;
697 static BitArrayRange R_rm_0(14, 12);
698 rm += R_rm_0.read(ba) << 0;
699 etiss_uint8 rs1 = 0;
700 static BitArrayRange R_rs1_0(19, 15);
701 rs1 += R_rs1_0.read(ba) << 0;
702 etiss_uint8 rs2 = 0;
703 static BitArrayRange R_rs2_0(24, 20);
704 rs2 += R_rs2_0.read(ba) << 0;
705 
706 // -----------------------------------------------------------------------------
707 
708  {
709  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
710 
711  cp.code() = std::string("//FSUB_S\n");
712 
713 // -----------------------------------------------------------------------------
714 { // block
715 cp.code() += "{ // block\n";
716 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
717 cp.code() += "} // block\n";
718 } // block
719 { // block
720 cp.code() += "{ // block\n";
721 { // block
722 cp.code() += "{ // block\n";
723 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
724 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
725 cp.code() += "etiss_uint32 res = fsub_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
726 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
727 cp.code() += "} // block\n";
728 } // block
729 cp.code() += "etiss_uint32 flags = fget_flags();\n";
730 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
731 cp.code() += "} // block\n";
732 } // block
733 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
734 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
735 // -----------------------------------------------------------------------------
736  cp.getAffectedRegisters().add("instructionPointer", 32);
737  }
738 
739  return true;
740  },
741  0,
742  [] (BitArray & ba, Instruction & instr)
743  {
744 // -----------------------------------------------------------------------------
745 etiss_uint8 rd = 0;
746 static BitArrayRange R_rd_0(11, 7);
747 rd += R_rd_0.read(ba) << 0;
748 etiss_uint8 rm = 0;
749 static BitArrayRange R_rm_0(14, 12);
750 rm += R_rm_0.read(ba) << 0;
751 etiss_uint8 rs1 = 0;
752 static BitArrayRange R_rs1_0(19, 15);
753 rs1 += R_rs1_0.read(ba) << 0;
754 etiss_uint8 rs2 = 0;
755 static BitArrayRange R_rs2_0(24, 20);
756 rs2 += R_rs2_0.read(ba) << 0;
757 
758 // -----------------------------------------------------------------------------
759 
760  std::stringstream ss;
761 // -----------------------------------------------------------------------------
762 ss << "fsub_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
763 // -----------------------------------------------------------------------------
764  return ss.str();
765  }
766 );
767 
768 // FMUL_S ----------------------------------------------------------------------
769 static InstructionDefinition fmul_s_rd_rm_rs1_rs2 (
770  ISA32_RV32IMACFD,
771  "fmul_s",
772  (uint32_t) 0x10000053,
773  (uint32_t) 0xfe00007f,
774  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
775  {
776 
777 // -----------------------------------------------------------------------------
778 
779 // -----------------------------------------------------------------------------
780 
781 // -----------------------------------------------------------------------------
782 etiss_uint8 rd = 0;
783 static BitArrayRange R_rd_0(11, 7);
784 rd += R_rd_0.read(ba) << 0;
785 etiss_uint8 rm = 0;
786 static BitArrayRange R_rm_0(14, 12);
787 rm += R_rm_0.read(ba) << 0;
788 etiss_uint8 rs1 = 0;
789 static BitArrayRange R_rs1_0(19, 15);
790 rs1 += R_rs1_0.read(ba) << 0;
791 etiss_uint8 rs2 = 0;
792 static BitArrayRange R_rs2_0(24, 20);
793 rs2 += R_rs2_0.read(ba) << 0;
794 
795 // -----------------------------------------------------------------------------
796 
797  {
798  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
799 
800  cp.code() = std::string("//FMUL_S\n");
801 
802 // -----------------------------------------------------------------------------
803 { // block
804 cp.code() += "{ // block\n";
805 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
806 cp.code() += "} // block\n";
807 } // block
808 { // block
809 cp.code() += "{ // block\n";
810 { // block
811 cp.code() += "{ // block\n";
812 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
813 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
814 cp.code() += "etiss_uint32 res = fmul_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
815 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
816 cp.code() += "} // block\n";
817 } // block
818 cp.code() += "etiss_uint32 flags = fget_flags();\n";
819 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
820 cp.code() += "} // block\n";
821 } // block
822 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
823 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
824 // -----------------------------------------------------------------------------
825  cp.getAffectedRegisters().add("instructionPointer", 32);
826  }
827 
828  return true;
829  },
830  0,
831  [] (BitArray & ba, Instruction & instr)
832  {
833 // -----------------------------------------------------------------------------
834 etiss_uint8 rd = 0;
835 static BitArrayRange R_rd_0(11, 7);
836 rd += R_rd_0.read(ba) << 0;
837 etiss_uint8 rm = 0;
838 static BitArrayRange R_rm_0(14, 12);
839 rm += R_rm_0.read(ba) << 0;
840 etiss_uint8 rs1 = 0;
841 static BitArrayRange R_rs1_0(19, 15);
842 rs1 += R_rs1_0.read(ba) << 0;
843 etiss_uint8 rs2 = 0;
844 static BitArrayRange R_rs2_0(24, 20);
845 rs2 += R_rs2_0.read(ba) << 0;
846 
847 // -----------------------------------------------------------------------------
848 
849  std::stringstream ss;
850 // -----------------------------------------------------------------------------
851 ss << "fmul_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
852 // -----------------------------------------------------------------------------
853  return ss.str();
854  }
855 );
856 
857 // FDIV_S ----------------------------------------------------------------------
858 static InstructionDefinition fdiv_s_rd_rm_rs1_rs2 (
859  ISA32_RV32IMACFD,
860  "fdiv_s",
861  (uint32_t) 0x18000053,
862  (uint32_t) 0xfe00007f,
863  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
864  {
865 
866 // -----------------------------------------------------------------------------
867 
868 // -----------------------------------------------------------------------------
869 
870 // -----------------------------------------------------------------------------
871 etiss_uint8 rd = 0;
872 static BitArrayRange R_rd_0(11, 7);
873 rd += R_rd_0.read(ba) << 0;
874 etiss_uint8 rm = 0;
875 static BitArrayRange R_rm_0(14, 12);
876 rm += R_rm_0.read(ba) << 0;
877 etiss_uint8 rs1 = 0;
878 static BitArrayRange R_rs1_0(19, 15);
879 rs1 += R_rs1_0.read(ba) << 0;
880 etiss_uint8 rs2 = 0;
881 static BitArrayRange R_rs2_0(24, 20);
882 rs2 += R_rs2_0.read(ba) << 0;
883 
884 // -----------------------------------------------------------------------------
885 
886  {
887  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
888 
889  cp.code() = std::string("//FDIV_S\n");
890 
891 // -----------------------------------------------------------------------------
892 { // block
893 cp.code() += "{ // block\n";
894 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
895 cp.code() += "} // block\n";
896 } // block
897 { // block
898 cp.code() += "{ // block\n";
899 { // block
900 cp.code() += "{ // block\n";
901 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
902 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
903 cp.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
904 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
905 cp.code() += "} // block\n";
906 } // block
907 cp.code() += "etiss_uint32 flags = fget_flags();\n";
908 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
909 cp.code() += "} // block\n";
910 } // block
911 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
912 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
913 // -----------------------------------------------------------------------------
914  cp.getAffectedRegisters().add("instructionPointer", 32);
915  }
916 
917  return true;
918  },
919  0,
920  [] (BitArray & ba, Instruction & instr)
921  {
922 // -----------------------------------------------------------------------------
923 etiss_uint8 rd = 0;
924 static BitArrayRange R_rd_0(11, 7);
925 rd += R_rd_0.read(ba) << 0;
926 etiss_uint8 rm = 0;
927 static BitArrayRange R_rm_0(14, 12);
928 rm += R_rm_0.read(ba) << 0;
929 etiss_uint8 rs1 = 0;
930 static BitArrayRange R_rs1_0(19, 15);
931 rs1 += R_rs1_0.read(ba) << 0;
932 etiss_uint8 rs2 = 0;
933 static BitArrayRange R_rs2_0(24, 20);
934 rs2 += R_rs2_0.read(ba) << 0;
935 
936 // -----------------------------------------------------------------------------
937 
938  std::stringstream ss;
939 // -----------------------------------------------------------------------------
940 ss << "fdiv_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
941 // -----------------------------------------------------------------------------
942  return ss.str();
943  }
944 );
945 
946 // FSQRT_S ---------------------------------------------------------------------
947 static InstructionDefinition fsqrt_s_rd_rm_rs1 (
948  ISA32_RV32IMACFD,
949  "fsqrt_s",
950  (uint32_t) 0x58000053,
951  (uint32_t) 0xfff0007f,
952  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
953  {
954 
955 // -----------------------------------------------------------------------------
956 
957 // -----------------------------------------------------------------------------
958 
959 // -----------------------------------------------------------------------------
960 etiss_uint8 rd = 0;
961 static BitArrayRange R_rd_0(11, 7);
962 rd += R_rd_0.read(ba) << 0;
963 etiss_uint8 rm = 0;
964 static BitArrayRange R_rm_0(14, 12);
965 rm += R_rm_0.read(ba) << 0;
966 etiss_uint8 rs1 = 0;
967 static BitArrayRange R_rs1_0(19, 15);
968 rs1 += R_rs1_0.read(ba) << 0;
969 
970 // -----------------------------------------------------------------------------
971 
972  {
973  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
974 
975  cp.code() = std::string("//FSQRT_S\n");
976 
977 // -----------------------------------------------------------------------------
978 { // block
979 cp.code() += "{ // block\n";
980 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
981 cp.code() += "} // block\n";
982 } // block
983 { // block
984 cp.code() += "{ // block\n";
985 { // block
986 cp.code() += "{ // block\n";
987 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
988 cp.code() += "etiss_uint32 res = fsqrt_s(frs1, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
989 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
990 cp.code() += "} // block\n";
991 } // block
992 cp.code() += "etiss_uint32 flags = fget_flags();\n";
993 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
994 cp.code() += "} // block\n";
995 } // block
996 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
997 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
998 // -----------------------------------------------------------------------------
999  cp.getAffectedRegisters().add("instructionPointer", 32);
1000  }
1001 
1002  return true;
1003  },
1004  0,
1005  [] (BitArray & ba, Instruction & instr)
1006  {
1007 // -----------------------------------------------------------------------------
1008 etiss_uint8 rd = 0;
1009 static BitArrayRange R_rd_0(11, 7);
1010 rd += R_rd_0.read(ba) << 0;
1011 etiss_uint8 rm = 0;
1012 static BitArrayRange R_rm_0(14, 12);
1013 rm += R_rm_0.read(ba) << 0;
1014 etiss_uint8 rs1 = 0;
1015 static BitArrayRange R_rs1_0(19, 15);
1016 rs1 += R_rs1_0.read(ba) << 0;
1017 
1018 // -----------------------------------------------------------------------------
1019 
1020  std::stringstream ss;
1021 // -----------------------------------------------------------------------------
1022 ss << "fsqrt_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
1023 // -----------------------------------------------------------------------------
1024  return ss.str();
1025  }
1026 );
1027 
1028 // FSGNJ_S ---------------------------------------------------------------------
1029 static InstructionDefinition fsgnj_s_rd_rs1_rs2 (
1030  ISA32_RV32IMACFD,
1031  "fsgnj_s",
1032  (uint32_t) 0x20000053,
1033  (uint32_t) 0xfe00707f,
1034  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1035  {
1036 
1037 // -----------------------------------------------------------------------------
1038 
1039 // -----------------------------------------------------------------------------
1040 
1041 // -----------------------------------------------------------------------------
1042 etiss_uint8 rd = 0;
1043 static BitArrayRange R_rd_0(11, 7);
1044 rd += R_rd_0.read(ba) << 0;
1045 etiss_uint8 rs1 = 0;
1046 static BitArrayRange R_rs1_0(19, 15);
1047 rs1 += R_rs1_0.read(ba) << 0;
1048 etiss_uint8 rs2 = 0;
1049 static BitArrayRange R_rs2_0(24, 20);
1050 rs2 += R_rs2_0.read(ba) << 0;
1051 
1052 // -----------------------------------------------------------------------------
1053 
1054  {
1055  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1056 
1057  cp.code() = std::string("//FSGNJ_S\n");
1058 
1059 // -----------------------------------------------------------------------------
1060 { // block
1061 cp.code() += "{ // block\n";
1062 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1063 cp.code() += "} // block\n";
1064 } // block
1065 { // block
1066 cp.code() += "{ // block\n";
1067 { // block
1068 cp.code() += "{ // block\n";
1069 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
1070 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
1071 cp.code() += "etiss_uint32 res = ((((((frs2) >> (31ULL)) & 1ULL)) << 31) | ((((frs1) >> (0LL)) & 2147483647ULL)));\n";
1072 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
1073 cp.code() += "} // block\n";
1074 } // block
1075 cp.code() += "} // block\n";
1076 } // block
1077 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1078 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1079 // -----------------------------------------------------------------------------
1080  cp.getAffectedRegisters().add("instructionPointer", 32);
1081  }
1082 
1083  return true;
1084  },
1085  0,
1086  [] (BitArray & ba, Instruction & instr)
1087  {
1088 // -----------------------------------------------------------------------------
1089 etiss_uint8 rd = 0;
1090 static BitArrayRange R_rd_0(11, 7);
1091 rd += R_rd_0.read(ba) << 0;
1092 etiss_uint8 rs1 = 0;
1093 static BitArrayRange R_rs1_0(19, 15);
1094 rs1 += R_rs1_0.read(ba) << 0;
1095 etiss_uint8 rs2 = 0;
1096 static BitArrayRange R_rs2_0(24, 20);
1097 rs2 += R_rs2_0.read(ba) << 0;
1098 
1099 // -----------------------------------------------------------------------------
1100 
1101  std::stringstream ss;
1102 // -----------------------------------------------------------------------------
1103 ss << "fsgnj_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1104 // -----------------------------------------------------------------------------
1105  return ss.str();
1106  }
1107 );
1108 
1109 // FSGNJN_S --------------------------------------------------------------------
1110 static InstructionDefinition fsgnjn_s_rd_rs1_rs2 (
1111  ISA32_RV32IMACFD,
1112  "fsgnjn_s",
1113  (uint32_t) 0x20001053,
1114  (uint32_t) 0xfe00707f,
1115  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1116  {
1117 
1118 // -----------------------------------------------------------------------------
1119 
1120 // -----------------------------------------------------------------------------
1121 
1122 // -----------------------------------------------------------------------------
1123 etiss_uint8 rd = 0;
1124 static BitArrayRange R_rd_0(11, 7);
1125 rd += R_rd_0.read(ba) << 0;
1126 etiss_uint8 rs1 = 0;
1127 static BitArrayRange R_rs1_0(19, 15);
1128 rs1 += R_rs1_0.read(ba) << 0;
1129 etiss_uint8 rs2 = 0;
1130 static BitArrayRange R_rs2_0(24, 20);
1131 rs2 += R_rs2_0.read(ba) << 0;
1132 
1133 // -----------------------------------------------------------------------------
1134 
1135  {
1136  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1137 
1138  cp.code() = std::string("//FSGNJN_S\n");
1139 
1140 // -----------------------------------------------------------------------------
1141 { // block
1142 cp.code() += "{ // block\n";
1143 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1144 cp.code() += "} // block\n";
1145 } // block
1146 { // block
1147 cp.code() += "{ // block\n";
1148 { // block
1149 cp.code() += "{ // block\n";
1150 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
1151 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
1152 cp.code() += "etiss_uint32 res = (((~((((frs2) >> (31ULL)) & 1ULL))) << 31) | ((((frs1) >> (0LL)) & 2147483647ULL)));\n";
1153 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
1154 cp.code() += "} // block\n";
1155 } // block
1156 cp.code() += "} // block\n";
1157 } // block
1158 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1159 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1160 // -----------------------------------------------------------------------------
1161  cp.getAffectedRegisters().add("instructionPointer", 32);
1162  }
1163 
1164  return true;
1165  },
1166  0,
1167  [] (BitArray & ba, Instruction & instr)
1168  {
1169 // -----------------------------------------------------------------------------
1170 etiss_uint8 rd = 0;
1171 static BitArrayRange R_rd_0(11, 7);
1172 rd += R_rd_0.read(ba) << 0;
1173 etiss_uint8 rs1 = 0;
1174 static BitArrayRange R_rs1_0(19, 15);
1175 rs1 += R_rs1_0.read(ba) << 0;
1176 etiss_uint8 rs2 = 0;
1177 static BitArrayRange R_rs2_0(24, 20);
1178 rs2 += R_rs2_0.read(ba) << 0;
1179 
1180 // -----------------------------------------------------------------------------
1181 
1182  std::stringstream ss;
1183 // -----------------------------------------------------------------------------
1184 ss << "fsgnjn_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1185 // -----------------------------------------------------------------------------
1186  return ss.str();
1187  }
1188 );
1189 
1190 // FSGNJX_S --------------------------------------------------------------------
1191 static InstructionDefinition fsgnjx_s_rd_rs1_rs2 (
1192  ISA32_RV32IMACFD,
1193  "fsgnjx_s",
1194  (uint32_t) 0x20002053,
1195  (uint32_t) 0xfe00707f,
1196  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1197  {
1198 
1199 // -----------------------------------------------------------------------------
1200 
1201 // -----------------------------------------------------------------------------
1202 
1203 // -----------------------------------------------------------------------------
1204 etiss_uint8 rd = 0;
1205 static BitArrayRange R_rd_0(11, 7);
1206 rd += R_rd_0.read(ba) << 0;
1207 etiss_uint8 rs1 = 0;
1208 static BitArrayRange R_rs1_0(19, 15);
1209 rs1 += R_rs1_0.read(ba) << 0;
1210 etiss_uint8 rs2 = 0;
1211 static BitArrayRange R_rs2_0(24, 20);
1212 rs2 += R_rs2_0.read(ba) << 0;
1213 
1214 // -----------------------------------------------------------------------------
1215 
1216  {
1217  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1218 
1219  cp.code() = std::string("//FSGNJX_S\n");
1220 
1221 // -----------------------------------------------------------------------------
1222 { // block
1223 cp.code() += "{ // block\n";
1224 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1225 cp.code() += "} // block\n";
1226 } // block
1227 { // block
1228 cp.code() += "{ // block\n";
1229 { // block
1230 cp.code() += "{ // block\n";
1231 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
1232 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
1233 cp.code() += "etiss_uint32 res = frs1 ^ (frs2 & 2147483648ULL);\n";
1234 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
1235 cp.code() += "} // block\n";
1236 } // block
1237 cp.code() += "} // block\n";
1238 } // block
1239 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1240 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1241 // -----------------------------------------------------------------------------
1242  cp.getAffectedRegisters().add("instructionPointer", 32);
1243  }
1244 
1245  return true;
1246  },
1247  0,
1248  [] (BitArray & ba, Instruction & instr)
1249  {
1250 // -----------------------------------------------------------------------------
1251 etiss_uint8 rd = 0;
1252 static BitArrayRange R_rd_0(11, 7);
1253 rd += R_rd_0.read(ba) << 0;
1254 etiss_uint8 rs1 = 0;
1255 static BitArrayRange R_rs1_0(19, 15);
1256 rs1 += R_rs1_0.read(ba) << 0;
1257 etiss_uint8 rs2 = 0;
1258 static BitArrayRange R_rs2_0(24, 20);
1259 rs2 += R_rs2_0.read(ba) << 0;
1260 
1261 // -----------------------------------------------------------------------------
1262 
1263  std::stringstream ss;
1264 // -----------------------------------------------------------------------------
1265 ss << "fsgnjx_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1266 // -----------------------------------------------------------------------------
1267  return ss.str();
1268  }
1269 );
1270 
1271 // FMIN_S ----------------------------------------------------------------------
1272 static InstructionDefinition fmin_s_rd_rs1_rs2 (
1273  ISA32_RV32IMACFD,
1274  "fmin_s",
1275  (uint32_t) 0x28000053,
1276  (uint32_t) 0xfe00707f,
1277  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1278  {
1279 
1280 // -----------------------------------------------------------------------------
1281 
1282 // -----------------------------------------------------------------------------
1283 
1284 // -----------------------------------------------------------------------------
1285 etiss_uint8 rd = 0;
1286 static BitArrayRange R_rd_0(11, 7);
1287 rd += R_rd_0.read(ba) << 0;
1288 etiss_uint8 rs1 = 0;
1289 static BitArrayRange R_rs1_0(19, 15);
1290 rs1 += R_rs1_0.read(ba) << 0;
1291 etiss_uint8 rs2 = 0;
1292 static BitArrayRange R_rs2_0(24, 20);
1293 rs2 += R_rs2_0.read(ba) << 0;
1294 
1295 // -----------------------------------------------------------------------------
1296 
1297  {
1298  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1299 
1300  cp.code() = std::string("//FMIN_S\n");
1301 
1302 // -----------------------------------------------------------------------------
1303 { // block
1304 cp.code() += "{ // block\n";
1305 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1306 cp.code() += "} // block\n";
1307 } // block
1308 { // block
1309 cp.code() += "{ // block\n";
1310 { // block
1311 cp.code() += "{ // block\n";
1312 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
1313 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
1314 cp.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 0LL);\n";
1315 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
1316 cp.code() += "} // block\n";
1317 } // block
1318 cp.code() += "etiss_uint32 flags = fget_flags();\n";
1319 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1320 cp.code() += "} // block\n";
1321 } // block
1322 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1323 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1324 // -----------------------------------------------------------------------------
1325  cp.getAffectedRegisters().add("instructionPointer", 32);
1326  }
1327 
1328  return true;
1329  },
1330  0,
1331  [] (BitArray & ba, Instruction & instr)
1332  {
1333 // -----------------------------------------------------------------------------
1334 etiss_uint8 rd = 0;
1335 static BitArrayRange R_rd_0(11, 7);
1336 rd += R_rd_0.read(ba) << 0;
1337 etiss_uint8 rs1 = 0;
1338 static BitArrayRange R_rs1_0(19, 15);
1339 rs1 += R_rs1_0.read(ba) << 0;
1340 etiss_uint8 rs2 = 0;
1341 static BitArrayRange R_rs2_0(24, 20);
1342 rs2 += R_rs2_0.read(ba) << 0;
1343 
1344 // -----------------------------------------------------------------------------
1345 
1346  std::stringstream ss;
1347 // -----------------------------------------------------------------------------
1348 ss << "fmin_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1349 // -----------------------------------------------------------------------------
1350  return ss.str();
1351  }
1352 );
1353 
1354 // FMAX_S ----------------------------------------------------------------------
1355 static InstructionDefinition fmax_s_rd_rs1_rs2 (
1356  ISA32_RV32IMACFD,
1357  "fmax_s",
1358  (uint32_t) 0x28001053,
1359  (uint32_t) 0xfe00707f,
1360  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1361  {
1362 
1363 // -----------------------------------------------------------------------------
1364 
1365 // -----------------------------------------------------------------------------
1366 
1367 // -----------------------------------------------------------------------------
1368 etiss_uint8 rd = 0;
1369 static BitArrayRange R_rd_0(11, 7);
1370 rd += R_rd_0.read(ba) << 0;
1371 etiss_uint8 rs1 = 0;
1372 static BitArrayRange R_rs1_0(19, 15);
1373 rs1 += R_rs1_0.read(ba) << 0;
1374 etiss_uint8 rs2 = 0;
1375 static BitArrayRange R_rs2_0(24, 20);
1376 rs2 += R_rs2_0.read(ba) << 0;
1377 
1378 // -----------------------------------------------------------------------------
1379 
1380  {
1381  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1382 
1383  cp.code() = std::string("//FMAX_S\n");
1384 
1385 // -----------------------------------------------------------------------------
1386 { // block
1387 cp.code() += "{ // block\n";
1388 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1389 cp.code() += "} // block\n";
1390 } // block
1391 { // block
1392 cp.code() += "{ // block\n";
1393 { // block
1394 cp.code() += "{ // block\n";
1395 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
1396 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
1397 cp.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 1ULL);\n";
1398 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
1399 cp.code() += "} // block\n";
1400 } // block
1401 cp.code() += "etiss_uint32 flags = fget_flags();\n";
1402 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1403 cp.code() += "} // block\n";
1404 } // block
1405 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1406 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1407 // -----------------------------------------------------------------------------
1408  cp.getAffectedRegisters().add("instructionPointer", 32);
1409  }
1410 
1411  return true;
1412  },
1413  0,
1414  [] (BitArray & ba, Instruction & instr)
1415  {
1416 // -----------------------------------------------------------------------------
1417 etiss_uint8 rd = 0;
1418 static BitArrayRange R_rd_0(11, 7);
1419 rd += R_rd_0.read(ba) << 0;
1420 etiss_uint8 rs1 = 0;
1421 static BitArrayRange R_rs1_0(19, 15);
1422 rs1 += R_rs1_0.read(ba) << 0;
1423 etiss_uint8 rs2 = 0;
1424 static BitArrayRange R_rs2_0(24, 20);
1425 rs2 += R_rs2_0.read(ba) << 0;
1426 
1427 // -----------------------------------------------------------------------------
1428 
1429  std::stringstream ss;
1430 // -----------------------------------------------------------------------------
1431 ss << "fmax_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1432 // -----------------------------------------------------------------------------
1433  return ss.str();
1434  }
1435 );
1436 
1437 // FCVT_W_S --------------------------------------------------------------------
1438 static InstructionDefinition fcvt_w_s_rd_rm_rs1 (
1439  ISA32_RV32IMACFD,
1440  "fcvt_w_s",
1441  (uint32_t) 0xc0000053,
1442  (uint32_t) 0xfff0007f,
1443  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1444  {
1445 
1446 // -----------------------------------------------------------------------------
1447 
1448 // -----------------------------------------------------------------------------
1449 
1450 // -----------------------------------------------------------------------------
1451 etiss_uint8 rd = 0;
1452 static BitArrayRange R_rd_0(11, 7);
1453 rd += R_rd_0.read(ba) << 0;
1454 etiss_uint8 rm = 0;
1455 static BitArrayRange R_rm_0(14, 12);
1456 rm += R_rm_0.read(ba) << 0;
1457 etiss_uint8 rs1 = 0;
1458 static BitArrayRange R_rs1_0(19, 15);
1459 rs1 += R_rs1_0.read(ba) << 0;
1460 
1461 // -----------------------------------------------------------------------------
1462 
1463  {
1464  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1465 
1466  cp.code() = std::string("//FCVT_W_S\n");
1467 
1468 // -----------------------------------------------------------------------------
1469 { // block
1470 cp.code() += "{ // block\n";
1471 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1472 cp.code() += "} // block\n";
1473 } // block
1474 { // block
1475 cp.code() += "{ // block\n";
1476 cp.code() += "etiss_int32 res = 0LL;\n";
1477 { // block
1478 cp.code() += "{ // block\n";
1479 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
1480 cp.code() += "res = fcvt_s(frs1, 0LL, " + std::to_string(rm) + "ULL);\n";
1481 cp.code() += "} // block\n";
1482 } // block
1483 if ((rd % 32ULL) != 0LL) { // conditional
1484 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
1485 } // conditional
1486 cp.code() += "etiss_uint32 flags = fget_flags();\n";
1487 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1488 cp.code() += "} // block\n";
1489 } // block
1490 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1491 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1492 // -----------------------------------------------------------------------------
1493  cp.getAffectedRegisters().add("instructionPointer", 32);
1494  }
1495 
1496  return true;
1497  },
1498  0,
1499  [] (BitArray & ba, Instruction & instr)
1500  {
1501 // -----------------------------------------------------------------------------
1502 etiss_uint8 rd = 0;
1503 static BitArrayRange R_rd_0(11, 7);
1504 rd += R_rd_0.read(ba) << 0;
1505 etiss_uint8 rm = 0;
1506 static BitArrayRange R_rm_0(14, 12);
1507 rm += R_rm_0.read(ba) << 0;
1508 etiss_uint8 rs1 = 0;
1509 static BitArrayRange R_rs1_0(19, 15);
1510 rs1 += R_rs1_0.read(ba) << 0;
1511 
1512 // -----------------------------------------------------------------------------
1513 
1514  std::stringstream ss;
1515 // -----------------------------------------------------------------------------
1516 ss << "fcvt_w_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
1517 // -----------------------------------------------------------------------------
1518  return ss.str();
1519  }
1520 );
1521 
1522 // FCVT_WU_S -------------------------------------------------------------------
1523 static InstructionDefinition fcvt_wu_s_rd_rm_rs1 (
1524  ISA32_RV32IMACFD,
1525  "fcvt_wu_s",
1526  (uint32_t) 0xc0100053,
1527  (uint32_t) 0xfff0007f,
1528  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1529  {
1530 
1531 // -----------------------------------------------------------------------------
1532 
1533 // -----------------------------------------------------------------------------
1534 
1535 // -----------------------------------------------------------------------------
1536 etiss_uint8 rd = 0;
1537 static BitArrayRange R_rd_0(11, 7);
1538 rd += R_rd_0.read(ba) << 0;
1539 etiss_uint8 rm = 0;
1540 static BitArrayRange R_rm_0(14, 12);
1541 rm += R_rm_0.read(ba) << 0;
1542 etiss_uint8 rs1 = 0;
1543 static BitArrayRange R_rs1_0(19, 15);
1544 rs1 += R_rs1_0.read(ba) << 0;
1545 
1546 // -----------------------------------------------------------------------------
1547 
1548  {
1549  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1550 
1551  cp.code() = std::string("//FCVT_WU_S\n");
1552 
1553 // -----------------------------------------------------------------------------
1554 { // block
1555 cp.code() += "{ // block\n";
1556 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1557 cp.code() += "} // block\n";
1558 } // block
1559 { // block
1560 cp.code() += "{ // block\n";
1561 cp.code() += "etiss_uint32 res = 0LL;\n";
1562 { // block
1563 cp.code() += "{ // block\n";
1564 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
1565 cp.code() += "res = fcvt_s(frs1, 1ULL, " + std::to_string(rm) + "ULL);\n";
1566 cp.code() += "} // block\n";
1567 } // block
1568 if ((rd % 32ULL) != 0LL) { // conditional
1569 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)((etiss_int32)(res));\n";
1570 } // conditional
1571 cp.code() += "etiss_uint32 flags = fget_flags();\n";
1572 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1573 cp.code() += "} // block\n";
1574 } // block
1575 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1576 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1577 // -----------------------------------------------------------------------------
1578  cp.getAffectedRegisters().add("instructionPointer", 32);
1579  }
1580 
1581  return true;
1582  },
1583  0,
1584  [] (BitArray & ba, Instruction & instr)
1585  {
1586 // -----------------------------------------------------------------------------
1587 etiss_uint8 rd = 0;
1588 static BitArrayRange R_rd_0(11, 7);
1589 rd += R_rd_0.read(ba) << 0;
1590 etiss_uint8 rm = 0;
1591 static BitArrayRange R_rm_0(14, 12);
1592 rm += R_rm_0.read(ba) << 0;
1593 etiss_uint8 rs1 = 0;
1594 static BitArrayRange R_rs1_0(19, 15);
1595 rs1 += R_rs1_0.read(ba) << 0;
1596 
1597 // -----------------------------------------------------------------------------
1598 
1599  std::stringstream ss;
1600 // -----------------------------------------------------------------------------
1601 ss << "fcvt_wu_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
1602 // -----------------------------------------------------------------------------
1603  return ss.str();
1604  }
1605 );
1606 
1607 // FEQ_S -----------------------------------------------------------------------
1608 static InstructionDefinition feq_s_rd_rs1_rs2 (
1609  ISA32_RV32IMACFD,
1610  "feq_s",
1611  (uint32_t) 0xa0002053,
1612  (uint32_t) 0xfe00707f,
1613  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1614  {
1615 
1616 // -----------------------------------------------------------------------------
1617 
1618 // -----------------------------------------------------------------------------
1619 
1620 // -----------------------------------------------------------------------------
1621 etiss_uint8 rd = 0;
1622 static BitArrayRange R_rd_0(11, 7);
1623 rd += R_rd_0.read(ba) << 0;
1624 etiss_uint8 rs1 = 0;
1625 static BitArrayRange R_rs1_0(19, 15);
1626 rs1 += R_rs1_0.read(ba) << 0;
1627 etiss_uint8 rs2 = 0;
1628 static BitArrayRange R_rs2_0(24, 20);
1629 rs2 += R_rs2_0.read(ba) << 0;
1630 
1631 // -----------------------------------------------------------------------------
1632 
1633  {
1634  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1635 
1636  cp.code() = std::string("//FEQ_S\n");
1637 
1638 // -----------------------------------------------------------------------------
1639 { // block
1640 cp.code() += "{ // block\n";
1641 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1642 cp.code() += "} // block\n";
1643 } // block
1644 { // block
1645 cp.code() += "{ // block\n";
1646 cp.code() += "etiss_uint32 res = 0LL;\n";
1647 { // block
1648 cp.code() += "{ // block\n";
1649 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
1650 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
1651 cp.code() += "res = fcmp_s(frs1, frs2, 0LL);\n";
1652 cp.code() += "} // block\n";
1653 } // block
1654 if ((rd % 32ULL) != 0LL) { // conditional
1655 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
1656 } // conditional
1657 cp.code() += "etiss_uint32 flags = fget_flags();\n";
1658 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1659 cp.code() += "} // block\n";
1660 } // block
1661 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1662 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1663 // -----------------------------------------------------------------------------
1664  cp.getAffectedRegisters().add("instructionPointer", 32);
1665  }
1666 
1667  return true;
1668  },
1669  0,
1670  [] (BitArray & ba, Instruction & instr)
1671  {
1672 // -----------------------------------------------------------------------------
1673 etiss_uint8 rd = 0;
1674 static BitArrayRange R_rd_0(11, 7);
1675 rd += R_rd_0.read(ba) << 0;
1676 etiss_uint8 rs1 = 0;
1677 static BitArrayRange R_rs1_0(19, 15);
1678 rs1 += R_rs1_0.read(ba) << 0;
1679 etiss_uint8 rs2 = 0;
1680 static BitArrayRange R_rs2_0(24, 20);
1681 rs2 += R_rs2_0.read(ba) << 0;
1682 
1683 // -----------------------------------------------------------------------------
1684 
1685  std::stringstream ss;
1686 // -----------------------------------------------------------------------------
1687 ss << "feq_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1688 // -----------------------------------------------------------------------------
1689  return ss.str();
1690  }
1691 );
1692 
1693 // FLT_S -----------------------------------------------------------------------
1694 static InstructionDefinition flt_s_rd_rs1_rs2 (
1695  ISA32_RV32IMACFD,
1696  "flt_s",
1697  (uint32_t) 0xa0001053,
1698  (uint32_t) 0xfe00707f,
1699  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1700  {
1701 
1702 // -----------------------------------------------------------------------------
1703 
1704 // -----------------------------------------------------------------------------
1705 
1706 // -----------------------------------------------------------------------------
1707 etiss_uint8 rd = 0;
1708 static BitArrayRange R_rd_0(11, 7);
1709 rd += R_rd_0.read(ba) << 0;
1710 etiss_uint8 rs1 = 0;
1711 static BitArrayRange R_rs1_0(19, 15);
1712 rs1 += R_rs1_0.read(ba) << 0;
1713 etiss_uint8 rs2 = 0;
1714 static BitArrayRange R_rs2_0(24, 20);
1715 rs2 += R_rs2_0.read(ba) << 0;
1716 
1717 // -----------------------------------------------------------------------------
1718 
1719  {
1720  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1721 
1722  cp.code() = std::string("//FLT_S\n");
1723 
1724 // -----------------------------------------------------------------------------
1725 { // block
1726 cp.code() += "{ // block\n";
1727 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1728 cp.code() += "} // block\n";
1729 } // block
1730 { // block
1731 cp.code() += "{ // block\n";
1732 cp.code() += "etiss_uint32 res = 0LL;\n";
1733 { // block
1734 cp.code() += "{ // block\n";
1735 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
1736 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
1737 cp.code() += "res = fcmp_s(frs1, frs2, 2ULL);\n";
1738 cp.code() += "} // block\n";
1739 } // block
1740 if ((rd % 32ULL) != 0LL) { // conditional
1741 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
1742 } // conditional
1743 cp.code() += "etiss_uint32 flags = fget_flags();\n";
1744 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1745 cp.code() += "} // block\n";
1746 } // block
1747 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1748 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1749 // -----------------------------------------------------------------------------
1750  cp.getAffectedRegisters().add("instructionPointer", 32);
1751  }
1752 
1753  return true;
1754  },
1755  0,
1756  [] (BitArray & ba, Instruction & instr)
1757  {
1758 // -----------------------------------------------------------------------------
1759 etiss_uint8 rd = 0;
1760 static BitArrayRange R_rd_0(11, 7);
1761 rd += R_rd_0.read(ba) << 0;
1762 etiss_uint8 rs1 = 0;
1763 static BitArrayRange R_rs1_0(19, 15);
1764 rs1 += R_rs1_0.read(ba) << 0;
1765 etiss_uint8 rs2 = 0;
1766 static BitArrayRange R_rs2_0(24, 20);
1767 rs2 += R_rs2_0.read(ba) << 0;
1768 
1769 // -----------------------------------------------------------------------------
1770 
1771  std::stringstream ss;
1772 // -----------------------------------------------------------------------------
1773 ss << "flt_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1774 // -----------------------------------------------------------------------------
1775  return ss.str();
1776  }
1777 );
1778 
1779 // FLE_S -----------------------------------------------------------------------
1780 static InstructionDefinition fle_s_rd_rs1_rs2 (
1781  ISA32_RV32IMACFD,
1782  "fle_s",
1783  (uint32_t) 0xa0000053,
1784  (uint32_t) 0xfe00707f,
1785  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1786  {
1787 
1788 // -----------------------------------------------------------------------------
1789 
1790 // -----------------------------------------------------------------------------
1791 
1792 // -----------------------------------------------------------------------------
1793 etiss_uint8 rd = 0;
1794 static BitArrayRange R_rd_0(11, 7);
1795 rd += R_rd_0.read(ba) << 0;
1796 etiss_uint8 rs1 = 0;
1797 static BitArrayRange R_rs1_0(19, 15);
1798 rs1 += R_rs1_0.read(ba) << 0;
1799 etiss_uint8 rs2 = 0;
1800 static BitArrayRange R_rs2_0(24, 20);
1801 rs2 += R_rs2_0.read(ba) << 0;
1802 
1803 // -----------------------------------------------------------------------------
1804 
1805  {
1806  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1807 
1808  cp.code() = std::string("//FLE_S\n");
1809 
1810 // -----------------------------------------------------------------------------
1811 { // block
1812 cp.code() += "{ // block\n";
1813 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1814 cp.code() += "} // block\n";
1815 } // block
1816 { // block
1817 cp.code() += "{ // block\n";
1818 cp.code() += "etiss_uint32 res = 0LL;\n";
1819 { // block
1820 cp.code() += "{ // block\n";
1821 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
1822 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
1823 cp.code() += "res = fcmp_s(frs1, frs2, 1ULL);\n";
1824 cp.code() += "} // block\n";
1825 } // block
1826 if ((rd % 32ULL) != 0LL) { // conditional
1827 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
1828 } // conditional
1829 cp.code() += "etiss_uint32 flags = fget_flags();\n";
1830 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1831 cp.code() += "} // block\n";
1832 } // block
1833 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1834 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1835 // -----------------------------------------------------------------------------
1836  cp.getAffectedRegisters().add("instructionPointer", 32);
1837  }
1838 
1839  return true;
1840  },
1841  0,
1842  [] (BitArray & ba, Instruction & instr)
1843  {
1844 // -----------------------------------------------------------------------------
1845 etiss_uint8 rd = 0;
1846 static BitArrayRange R_rd_0(11, 7);
1847 rd += R_rd_0.read(ba) << 0;
1848 etiss_uint8 rs1 = 0;
1849 static BitArrayRange R_rs1_0(19, 15);
1850 rs1 += R_rs1_0.read(ba) << 0;
1851 etiss_uint8 rs2 = 0;
1852 static BitArrayRange R_rs2_0(24, 20);
1853 rs2 += R_rs2_0.read(ba) << 0;
1854 
1855 // -----------------------------------------------------------------------------
1856 
1857  std::stringstream ss;
1858 // -----------------------------------------------------------------------------
1859 ss << "fle_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1860 // -----------------------------------------------------------------------------
1861  return ss.str();
1862  }
1863 );
1864 
1865 // FCLASS_S --------------------------------------------------------------------
1866 static InstructionDefinition fclass_s_rd_rs1 (
1867  ISA32_RV32IMACFD,
1868  "fclass_s",
1869  (uint32_t) 0xe0001053,
1870  (uint32_t) 0xfff0707f,
1871  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1872  {
1873 
1874 // -----------------------------------------------------------------------------
1875 
1876 // -----------------------------------------------------------------------------
1877 
1878 // -----------------------------------------------------------------------------
1879 etiss_uint8 rd = 0;
1880 static BitArrayRange R_rd_0(11, 7);
1881 rd += R_rd_0.read(ba) << 0;
1882 etiss_uint8 rs1 = 0;
1883 static BitArrayRange R_rs1_0(19, 15);
1884 rs1 += R_rs1_0.read(ba) << 0;
1885 
1886 // -----------------------------------------------------------------------------
1887 
1888  {
1889  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1890 
1891  cp.code() = std::string("//FCLASS_S\n");
1892 
1893 // -----------------------------------------------------------------------------
1894 { // block
1895 cp.code() += "{ // block\n";
1896 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1897 cp.code() += "} // block\n";
1898 } // block
1899 { // block
1900 cp.code() += "{ // block\n";
1901 cp.code() += "etiss_uint32 res = 0LL;\n";
1902 cp.code() += "res = fclass_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]));\n";
1903 if ((rd % 32ULL) != 0LL) { // conditional
1904 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
1905 } // conditional
1906 cp.code() += "} // block\n";
1907 } // block
1908 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1909 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1910 // -----------------------------------------------------------------------------
1911  cp.getAffectedRegisters().add("instructionPointer", 32);
1912  }
1913 
1914  return true;
1915  },
1916  0,
1917  [] (BitArray & ba, Instruction & instr)
1918  {
1919 // -----------------------------------------------------------------------------
1920 etiss_uint8 rd = 0;
1921 static BitArrayRange R_rd_0(11, 7);
1922 rd += R_rd_0.read(ba) << 0;
1923 etiss_uint8 rs1 = 0;
1924 static BitArrayRange R_rs1_0(19, 15);
1925 rs1 += R_rs1_0.read(ba) << 0;
1926 
1927 // -----------------------------------------------------------------------------
1928 
1929  std::stringstream ss;
1930 // -----------------------------------------------------------------------------
1931 ss << "fclass_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + "]");
1932 // -----------------------------------------------------------------------------
1933  return ss.str();
1934  }
1935 );
1936 
1937 // FCVT_S_W --------------------------------------------------------------------
1938 static InstructionDefinition fcvt_s_w_rd_rm_rs1 (
1939  ISA32_RV32IMACFD,
1940  "fcvt_s_w",
1941  (uint32_t) 0xd0000053,
1942  (uint32_t) 0xfff0007f,
1943  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1944  {
1945 
1946 // -----------------------------------------------------------------------------
1947 
1948 // -----------------------------------------------------------------------------
1949 
1950 // -----------------------------------------------------------------------------
1951 etiss_uint8 rd = 0;
1952 static BitArrayRange R_rd_0(11, 7);
1953 rd += R_rd_0.read(ba) << 0;
1954 etiss_uint8 rm = 0;
1955 static BitArrayRange R_rm_0(14, 12);
1956 rm += R_rm_0.read(ba) << 0;
1957 etiss_uint8 rs1 = 0;
1958 static BitArrayRange R_rs1_0(19, 15);
1959 rs1 += R_rs1_0.read(ba) << 0;
1960 
1961 // -----------------------------------------------------------------------------
1962 
1963  {
1964  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1965 
1966  cp.code() = std::string("//FCVT_S_W\n");
1967 
1968 // -----------------------------------------------------------------------------
1969 { // block
1970 cp.code() += "{ // block\n";
1971 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1972 cp.code() += "} // block\n";
1973 } // block
1974 { // block
1975 cp.code() += "{ // block\n";
1976 { // block
1977 cp.code() += "{ // block\n";
1978 cp.code() += "etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), 2ULL, " + std::to_string(rm) + "ULL);\n";
1979 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
1980 cp.code() += "} // block\n";
1981 } // block
1982 cp.code() += "} // block\n";
1983 } // block
1984 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1985 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1986 // -----------------------------------------------------------------------------
1987  cp.getAffectedRegisters().add("instructionPointer", 32);
1988  }
1989 
1990  return true;
1991  },
1992  0,
1993  [] (BitArray & ba, Instruction & instr)
1994  {
1995 // -----------------------------------------------------------------------------
1996 etiss_uint8 rd = 0;
1997 static BitArrayRange R_rd_0(11, 7);
1998 rd += R_rd_0.read(ba) << 0;
1999 etiss_uint8 rm = 0;
2000 static BitArrayRange R_rm_0(14, 12);
2001 rm += R_rm_0.read(ba) << 0;
2002 etiss_uint8 rs1 = 0;
2003 static BitArrayRange R_rs1_0(19, 15);
2004 rs1 += R_rs1_0.read(ba) << 0;
2005 
2006 // -----------------------------------------------------------------------------
2007 
2008  std::stringstream ss;
2009 // -----------------------------------------------------------------------------
2010 ss << "fcvt_s_w" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
2011 // -----------------------------------------------------------------------------
2012  return ss.str();
2013  }
2014 );
2015 
2016 // FCVT_S_WU -------------------------------------------------------------------
2017 static InstructionDefinition fcvt_s_wu_rd_rm_rs1 (
2018  ISA32_RV32IMACFD,
2019  "fcvt_s_wu",
2020  (uint32_t) 0xd0100053,
2021  (uint32_t) 0xfff0007f,
2022  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2023  {
2024 
2025 // -----------------------------------------------------------------------------
2026 
2027 // -----------------------------------------------------------------------------
2028 
2029 // -----------------------------------------------------------------------------
2030 etiss_uint8 rd = 0;
2031 static BitArrayRange R_rd_0(11, 7);
2032 rd += R_rd_0.read(ba) << 0;
2033 etiss_uint8 rm = 0;
2034 static BitArrayRange R_rm_0(14, 12);
2035 rm += R_rm_0.read(ba) << 0;
2036 etiss_uint8 rs1 = 0;
2037 static BitArrayRange R_rs1_0(19, 15);
2038 rs1 += R_rs1_0.read(ba) << 0;
2039 
2040 // -----------------------------------------------------------------------------
2041 
2042  {
2043  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2044 
2045  cp.code() = std::string("//FCVT_S_WU\n");
2046 
2047 // -----------------------------------------------------------------------------
2048 { // block
2049 cp.code() += "{ // block\n";
2050 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2051 cp.code() += "} // block\n";
2052 } // block
2053 { // block
2054 cp.code() += "{ // block\n";
2055 { // block
2056 cp.code() += "{ // block\n";
2057 cp.code() += "etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), 3ULL, " + std::to_string(rm) + "ULL);\n";
2058 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
2059 cp.code() += "} // block\n";
2060 } // block
2061 cp.code() += "} // block\n";
2062 } // block
2063 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2064 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2065 // -----------------------------------------------------------------------------
2066  cp.getAffectedRegisters().add("instructionPointer", 32);
2067  }
2068 
2069  return true;
2070  },
2071  0,
2072  [] (BitArray & ba, Instruction & instr)
2073  {
2074 // -----------------------------------------------------------------------------
2075 etiss_uint8 rd = 0;
2076 static BitArrayRange R_rd_0(11, 7);
2077 rd += R_rd_0.read(ba) << 0;
2078 etiss_uint8 rm = 0;
2079 static BitArrayRange R_rm_0(14, 12);
2080 rm += R_rm_0.read(ba) << 0;
2081 etiss_uint8 rs1 = 0;
2082 static BitArrayRange R_rs1_0(19, 15);
2083 rs1 += R_rs1_0.read(ba) << 0;
2084 
2085 // -----------------------------------------------------------------------------
2086 
2087  std::stringstream ss;
2088 // -----------------------------------------------------------------------------
2089 ss << "fcvt_s_wu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
2090 // -----------------------------------------------------------------------------
2091  return ss.str();
2092  }
2093 );
2094 
2095 // FMV_X_W ---------------------------------------------------------------------
2096 static InstructionDefinition fmv_x_w_rd_rs1 (
2097  ISA32_RV32IMACFD,
2098  "fmv_x_w",
2099  (uint32_t) 0xe0000053,
2100  (uint32_t) 0xfff0707f,
2101  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2102  {
2103 
2104 // -----------------------------------------------------------------------------
2105 
2106 // -----------------------------------------------------------------------------
2107 
2108 // -----------------------------------------------------------------------------
2109 etiss_uint8 rd = 0;
2110 static BitArrayRange R_rd_0(11, 7);
2111 rd += R_rd_0.read(ba) << 0;
2112 etiss_uint8 rs1 = 0;
2113 static BitArrayRange R_rs1_0(19, 15);
2114 rs1 += R_rs1_0.read(ba) << 0;
2115 
2116 // -----------------------------------------------------------------------------
2117 
2118  {
2119  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2120 
2121  cp.code() = std::string("//FMV_X_W\n");
2122 
2123 // -----------------------------------------------------------------------------
2124 { // block
2125 cp.code() += "{ // block\n";
2126 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2127 cp.code() += "} // block\n";
2128 } // block
2129 { // block
2130 cp.code() += "{ // block\n";
2131 if ((rd % 32ULL) != 0LL) { // conditional
2132 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)((etiss_int32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]));\n";
2133 } // conditional
2134 cp.code() += "} // block\n";
2135 } // block
2136 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2137 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2138 // -----------------------------------------------------------------------------
2139  cp.getAffectedRegisters().add("instructionPointer", 32);
2140  }
2141 
2142  return true;
2143  },
2144  0,
2145  [] (BitArray & ba, Instruction & instr)
2146  {
2147 // -----------------------------------------------------------------------------
2148 etiss_uint8 rd = 0;
2149 static BitArrayRange R_rd_0(11, 7);
2150 rd += R_rd_0.read(ba) << 0;
2151 etiss_uint8 rs1 = 0;
2152 static BitArrayRange R_rs1_0(19, 15);
2153 rs1 += R_rs1_0.read(ba) << 0;
2154 
2155 // -----------------------------------------------------------------------------
2156 
2157  std::stringstream ss;
2158 // -----------------------------------------------------------------------------
2159 ss << "fmv_x_w" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + "]");
2160 // -----------------------------------------------------------------------------
2161  return ss.str();
2162  }
2163 );
2164 
2165 // FMV_W_X ---------------------------------------------------------------------
2166 static InstructionDefinition fmv_w_x_rd_rs1 (
2167  ISA32_RV32IMACFD,
2168  "fmv_w_x",
2169  (uint32_t) 0xf0000053,
2170  (uint32_t) 0xfff0707f,
2171  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2172  {
2173 
2174 // -----------------------------------------------------------------------------
2175 
2176 // -----------------------------------------------------------------------------
2177 
2178 // -----------------------------------------------------------------------------
2179 etiss_uint8 rd = 0;
2180 static BitArrayRange R_rd_0(11, 7);
2181 rd += R_rd_0.read(ba) << 0;
2182 etiss_uint8 rs1 = 0;
2183 static BitArrayRange R_rs1_0(19, 15);
2184 rs1 += R_rs1_0.read(ba) << 0;
2185 
2186 // -----------------------------------------------------------------------------
2187 
2188  {
2189  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2190 
2191  cp.code() = std::string("//FMV_W_X\n");
2192 
2193 // -----------------------------------------------------------------------------
2194 { // block
2195 cp.code() += "{ // block\n";
2196 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2197 cp.code() += "} // block\n";
2198 } // block
2199 { // block
2200 cp.code() += "{ // block\n";
2201 { // block
2202 cp.code() += "{ // block\n";
2203 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]);\n";
2204 cp.code() += "} // block\n";
2205 } // block
2206 cp.code() += "} // block\n";
2207 } // block
2208 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2209 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2210 // -----------------------------------------------------------------------------
2211  cp.getAffectedRegisters().add("instructionPointer", 32);
2212  }
2213 
2214  return true;
2215  },
2216  0,
2217  [] (BitArray & ba, Instruction & instr)
2218  {
2219 // -----------------------------------------------------------------------------
2220 etiss_uint8 rd = 0;
2221 static BitArrayRange R_rd_0(11, 7);
2222 rd += R_rd_0.read(ba) << 0;
2223 etiss_uint8 rs1 = 0;
2224 static BitArrayRange R_rs1_0(19, 15);
2225 rs1 += R_rs1_0.read(ba) << 0;
2226 
2227 // -----------------------------------------------------------------------------
2228 
2229  std::stringstream ss;
2230 // -----------------------------------------------------------------------------
2231 ss << "fmv_w_x" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + "]");
2232 // -----------------------------------------------------------------------------
2233  return ss.str();
2234  }
2235 );
ISA32_RV32IMACFD
etiss::instr::InstructionGroup ISA32_RV32IMACFD("ISA32_RV32IMACFD", 32)
fmin_s_rd_rs1_rs2
static InstructionDefinition fmin_s_rd_rs1_rs2(ISA32_RV32IMACFD, "fmin_s",(uint32_t) 0x28000053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMIN_S\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";{ cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_uint32 res = fsel_s(frs1, frs2, 0LL);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fmin_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fadd_s_rd_rm_rs1_rs2
static InstructionDefinition fadd_s_rd_rm_rs1_rs2(ISA32_RV32IMACFD, "fadd_s",(uint32_t) 0x000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FADD_S\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";{ cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_uint32 res = fadd_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fadd_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fmadd_s_rd_rm_rs1_rs2_rs3
static InstructionDefinition fmadd_s_rd_rm_rs1_rs2_rs3(ISA32_RV32IMACFD, "fmadd_s",(uint32_t) 0x000043,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMADD_S\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";{ cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs3)+"ULL]), 0LL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;std::stringstream ss;ss<< "fmadd_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rs3="+std::to_string(rs3)+"]");return ss.str();})
fcvt_s_wu_rd_rm_rs1
static InstructionDefinition fcvt_s_wu_rd_rm_rs1(ISA32_RV32IMACFD, "fcvt_s_wu",(uint32_t) 0xd0100053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_S_WU\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";{ cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]), 3ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_s_wu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fdiv_s_rd_rm_rs1_rs2
static InstructionDefinition fdiv_s_rd_rm_rs1_rs2(ISA32_RV32IMACFD, "fdiv_s",(uint32_t) 0x18000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FDIV_S\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";{ cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_uint32 res = fdiv_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fdiv_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fsub_s_rd_rm_rs1_rs2
static InstructionDefinition fsub_s_rd_rm_rs1_rs2(ISA32_RV32IMACFD, "fsub_s",(uint32_t) 0x8000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSUB_S\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";{ cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_uint32 res = fsub_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fsub_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fsgnjn_s_rd_rs1_rs2
static InstructionDefinition fsgnjn_s_rd_rs1_rs2(ISA32_RV32IMACFD, "fsgnjn_s",(uint32_t) 0x20001053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSGNJN_S\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";{ cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_uint32 res = (((~((((frs2) >> (31ULL)) & 1ULL))) << 31) | ((((frs1) >> (0LL)) & 2147483647ULL)));\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fsgnjn_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fcvt_wu_s_rd_rm_rs1
static InstructionDefinition fcvt_wu_s_rd_rm_rs1(ISA32_RV32IMACFD, "fcvt_wu_s",(uint32_t) 0xc0100053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_WU_S\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = 0LL;\n";{ cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="res = fcvt_s(frs1, 1ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint32)((etiss_int32)(res));\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_wu_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fnmadd_s_rd_rm_rs1_rs2_rs3
static InstructionDefinition fnmadd_s_rd_rm_rs1_rs2_rs3(ISA32_RV32IMACFD, "fnmadd_s",(uint32_t) 0x00004f,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FNMADD_S\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";{ cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs3)+"ULL]);\n";cp.code()+="etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;std::stringstream ss;ss<< "fnmadd_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rs3="+std::to_string(rs3)+"]");return ss.str();})
fsw_imm_rs1_rs2
static InstructionDefinition fsw_imm_rs1_rs2(ISA32_RV32IMACFD, "fsw",(uint32_t) 0x002027,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint32 offs = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//FSW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "fsw"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fsgnjx_s_rd_rs1_rs2
static InstructionDefinition fsgnjx_s_rd_rs1_rs2(ISA32_RV32IMACFD, "fsgnjx_s",(uint32_t) 0x20002053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSGNJX_S\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";{ cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_uint32 res = frs1 ^ (frs2 & 2147483648ULL);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fsgnjx_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fcvt_w_s_rd_rm_rs1
static InstructionDefinition fcvt_w_s_rd_rm_rs1(ISA32_RV32IMACFD, "fcvt_w_s",(uint32_t) 0xc0000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_W_S\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_int32 res = 0LL;\n";{ cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="res = fcvt_s(frs1, 0LL, "+std::to_string(rm)+"ULL);\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_w_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fmsub_s_rd_rm_rs1_rs2_rs3
static InstructionDefinition fmsub_s_rd_rm_rs1_rs2_rs3(ISA32_RV32IMACFD, "fmsub_s",(uint32_t) 0x000047,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMSUB_S\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";{ cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs3)+"ULL]), 1ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;std::stringstream ss;ss<< "fmsub_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rs3="+std::to_string(rs3)+"]");return ss.str();})
fmv_w_x_rd_rs1
static InstructionDefinition fmv_w_x_rd_rs1(ISA32_RV32IMACFD, "fmv_w_x",(uint32_t) 0xf0000053,(uint32_t) 0xfff0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMV_W_X\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";{ cp.code()+="{ // block\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fmv_w_x"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fclass_s_rd_rs1
static InstructionDefinition fclass_s_rd_rs1(ISA32_RV32IMACFD, "fclass_s",(uint32_t) 0xe0001053,(uint32_t) 0xfff0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCLASS_S\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = 0LL;\n";cp.code()+="res = fclass_s(unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]));\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fclass_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fmax_s_rd_rs1_rs2
static InstructionDefinition fmax_s_rd_rs1_rs2(ISA32_RV32IMACFD, "fmax_s",(uint32_t) 0x28001053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMAX_S\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";{ cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_uint32 res = fsel_s(frs1, frs2, 1ULL);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fmax_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fmv_x_w_rd_rs1
static InstructionDefinition fmv_x_w_rd_rs1(ISA32_RV32IMACFD, "fmv_x_w",(uint32_t) 0xe0000053,(uint32_t) 0xfff0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMV_X_W\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";if((rd % 32ULL) !=0LL) { cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint32)((etiss_int32)(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]));\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fmv_x_w"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fsgnj_s_rd_rs1_rs2
static InstructionDefinition fsgnj_s_rd_rs1_rs2(ISA32_RV32IMACFD, "fsgnj_s",(uint32_t) 0x20000053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSGNJ_S\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";{ cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_uint32 res = ((((((frs2) >> (31ULL)) & 1ULL)) << 31) | ((((frs1) >> (0LL)) & 2147483647ULL)));\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fsgnj_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fcvt_s_w_rd_rm_rs1
static InstructionDefinition fcvt_s_w_rd_rm_rs1(ISA32_RV32IMACFD, "fcvt_s_w",(uint32_t) 0xd0000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_S_W\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";{ cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]), 2ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_s_w"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
feq_s_rd_rs1_rs2
static InstructionDefinition feq_s_rd_rs1_rs2(ISA32_RV32IMACFD, "feq_s",(uint32_t) 0xa0002053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FEQ_S\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = 0LL;\n";{ cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="res = fcmp_s(frs1, frs2, 0LL);\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "feq_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fsqrt_s_rd_rm_rs1
static InstructionDefinition fsqrt_s_rd_rm_rs1(ISA32_RV32IMACFD, "fsqrt_s",(uint32_t) 0x58000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSQRT_S\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";{ cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_uint32 res = fsqrt_s(frs1, RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fsqrt_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
flt_s_rd_rs1_rs2
static InstructionDefinition flt_s_rd_rs1_rs2(ISA32_RV32IMACFD, "flt_s",(uint32_t) 0xa0001053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FLT_S\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = 0LL;\n";{ cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="res = fcmp_s(frs1, frs2, 2ULL);\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "flt_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fnmsub_s_rd_rm_rs1_rs2_rs3
static InstructionDefinition fnmsub_s_rd_rm_rs1_rs2_rs3(ISA32_RV32IMACFD, "fnmsub_s",(uint32_t) 0x00004b,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FNMSUB_S\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";{ cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs3)+"ULL]);\n";cp.code()+="etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;std::stringstream ss;ss<< "fnmsub_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rs3="+std::to_string(rs3)+"]");return ss.str();})
fle_s_rd_rs1_rs2
static InstructionDefinition fle_s_rd_rs1_rs2(ISA32_RV32IMACFD, "fle_s",(uint32_t) 0xa0000053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FLE_S\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = 0LL;\n";{ cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="res = fcmp_s(frs1, frs2, 1ULL);\n";cp.code()+="} // block\n";} if((rd % 32ULL) !=0LL) { cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fle_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
flw_rd_rs1_imm
static InstructionDefinition flw_rd_rs1_imm(ISA32_RV32IMACFD, "flw",(uint32_t) 0x002007,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FLW\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint32 offs = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";{ cp.code()+="{ // block\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//FLW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "flw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
fmul_s_rd_rm_rs1_rs2
static InstructionDefinition fmul_s_rd_rm_rs1_rs2(ISA32_RV32IMACFD, "fmul_s",(uint32_t) 0x10000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMUL_S\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";{ cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_uint32 res = fmul_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fmul_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
uint32_t
static __inline__ uint32_t
Definition: arm_cde.h:25
etiss_int16
int16_t etiss_int16
Definition: types.h:89
etiss_uint8
uint8_t etiss_uint8
Definition: types.h:87
etiss_uint16
uint16_t etiss_uint16
Definition: types.h:90
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:386
etiss::CodePart::APPENDEDRETURNINGREQUIRED
@ APPENDEDRETURNINGREQUIRED
Definition: CodePart.h:402
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition: Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition: Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
Generated on Thu Jul 4 2024 12:41:52 for ETISS 0.8.0 by doxygen 1.9.1