ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV32IMACFD_RV32FInstr.cpp
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1 
8 #include "RV32IMACFDArch.h"
9 #include "RV32IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // FLW -------------------------------------------------------------------------
16 static InstructionDefinition flw_rd_rs1_imm (
17  ISA32_RV32IMACFD,
18  "flw",
19  (uint32_t) 0x002007,
20  (uint32_t) 0x00707f,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 etiss_uint8 rd = 0;
30 static BitArrayRange R_rd_0(11, 7);
31 rd += R_rd_0.read(ba) << 0;
32 etiss_uint8 rs1 = 0;
33 static BitArrayRange R_rs1_0(19, 15);
34 rs1 += R_rs1_0.read(ba) << 0;
35 etiss_uint16 imm = 0;
36 static BitArrayRange R_imm_0(31, 20);
37 imm += R_imm_0.read(ba) << 0;
38 
39 // -----------------------------------------------------------------------------
40 
41  {
42  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
43 
44  cp.code() = std::string("//FLW\n");
45 
46 // -----------------------------------------------------------------------------
47 cp.code() += "etiss_coverage_count(1, 88);\n";
48 { // block
49 cp.code() += "etiss_coverage_count(1, 1169);\n";
50 cp.code() += "{ // block\n";
51 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
52 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
53 cp.code() += "} // block\n";
54 } // block
55 { // block
56 cp.code() += "etiss_coverage_count(1, 3450);\n";
57 cp.code() += "{ // block\n";
58 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
59 cp.code() += "etiss_coverage_count(7, 3417, 3416, 3412, 3411, 3409, 3415, 3413);\n";
60 cp.code() += "etiss_uint32 mem_val_0;\n";
61 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
62 cp.code() += "if (cpu->exception) { // conditional\n";
63 { // procedure
64 cp.code() += "{ // procedure\n";
65 cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
66 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
67 cp.code() += "} // procedure\n";
68 } // procedure
69 cp.code() += "} // conditional\n";
70 cp.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
71 cp.code() += "etiss_coverage_count(4, 3424, 3423, 3421, 3420);\n";
72 { // block
73 cp.code() += "etiss_coverage_count(1, 3449);\n";
74 cp.code() += "{ // block\n";
75 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
76 cp.code() += "etiss_coverage_count(6, 3448, 3436, 3435, 3447, 3446, 3444);\n";
77 cp.code() += "} // block\n";
78 } // block
79 cp.code() += "} // block\n";
80 } // block
81 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
82 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
83 // -----------------------------------------------------------------------------
84  cp.getAffectedRegisters().add("instructionPointer", 32);
85  }
86  {
87  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
88 
89  cp.code() = std::string("//FLW\n");
90 
91 // -----------------------------------------------------------------------------
92 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
93 // -----------------------------------------------------------------------------
94  }
95 
96  return true;
97  },
98  0,
99  [] (BitArray & ba, Instruction & instr)
100  {
101 // -----------------------------------------------------------------------------
102 etiss_uint8 rd = 0;
103 static BitArrayRange R_rd_0(11, 7);
104 rd += R_rd_0.read(ba) << 0;
105 etiss_uint8 rs1 = 0;
106 static BitArrayRange R_rs1_0(19, 15);
107 rs1 += R_rs1_0.read(ba) << 0;
108 etiss_uint16 imm = 0;
109 static BitArrayRange R_imm_0(31, 20);
110 imm += R_imm_0.read(ba) << 0;
111 
112 // -----------------------------------------------------------------------------
113 
114  std::stringstream ss;
115 // -----------------------------------------------------------------------------
116 ss << "flw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
117 // -----------------------------------------------------------------------------
118  return ss.str();
119  }
120 );
121 
122 // FSW -------------------------------------------------------------------------
123 static InstructionDefinition fsw_imm_rs1_rs2 (
124  ISA32_RV32IMACFD,
125  "fsw",
126  (uint32_t) 0x002027,
127  (uint32_t) 0x00707f,
128  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
129  {
130 
131 // -----------------------------------------------------------------------------
132 
133 // -----------------------------------------------------------------------------
134 
135 // -----------------------------------------------------------------------------
136 etiss_uint16 imm = 0;
137 static BitArrayRange R_imm_0(11, 7);
138 imm += R_imm_0.read(ba) << 0;
139 etiss_uint8 rs1 = 0;
140 static BitArrayRange R_rs1_0(19, 15);
141 rs1 += R_rs1_0.read(ba) << 0;
142 etiss_uint8 rs2 = 0;
143 static BitArrayRange R_rs2_0(24, 20);
144 rs2 += R_rs2_0.read(ba) << 0;
145 static BitArrayRange R_imm_5(31, 25);
146 imm += R_imm_5.read(ba) << 5;
147 
148 // -----------------------------------------------------------------------------
149 
150  {
151  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
152 
153  cp.code() = std::string("//FSW\n");
154 
155 // -----------------------------------------------------------------------------
156 cp.code() += "etiss_coverage_count(1, 89);\n";
157 { // block
158 cp.code() += "etiss_coverage_count(1, 1169);\n";
159 cp.code() += "{ // block\n";
160 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
161 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
162 cp.code() += "} // block\n";
163 } // block
164 { // block
165 cp.code() += "etiss_coverage_count(1, 3471);\n";
166 cp.code() += "{ // block\n";
167 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
168 cp.code() += "etiss_coverage_count(7, 3461, 3460, 3456, 3455, 3453, 3459, 3457);\n";
169 cp.code() += "etiss_uint32 mem_val_0;\n";
170 cp.code() += "mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
171 cp.code() += "etiss_coverage_count(6, 3470, 3464, 3463, 3469, 3467, 3466);\n";
172 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
173 cp.code() += "if (cpu->exception) { // conditional\n";
174 { // procedure
175 cp.code() += "{ // procedure\n";
176 cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
177 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
178 cp.code() += "} // procedure\n";
179 } // procedure
180 cp.code() += "} // conditional\n";
181 cp.code() += "} // block\n";
182 } // block
183 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
184 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
185 // -----------------------------------------------------------------------------
186  cp.getAffectedRegisters().add("instructionPointer", 32);
187  }
188  {
189  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
190 
191  cp.code() = std::string("//FSW\n");
192 
193 // -----------------------------------------------------------------------------
194 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
195 // -----------------------------------------------------------------------------
196  }
197 
198  return true;
199  },
200  0,
201  [] (BitArray & ba, Instruction & instr)
202  {
203 // -----------------------------------------------------------------------------
204 etiss_uint16 imm = 0;
205 static BitArrayRange R_imm_0(11, 7);
206 imm += R_imm_0.read(ba) << 0;
207 etiss_uint8 rs1 = 0;
208 static BitArrayRange R_rs1_0(19, 15);
209 rs1 += R_rs1_0.read(ba) << 0;
210 etiss_uint8 rs2 = 0;
211 static BitArrayRange R_rs2_0(24, 20);
212 rs2 += R_rs2_0.read(ba) << 0;
213 static BitArrayRange R_imm_5(31, 25);
214 imm += R_imm_5.read(ba) << 5;
215 
216 // -----------------------------------------------------------------------------
217 
218  std::stringstream ss;
219 // -----------------------------------------------------------------------------
220 ss << "fsw" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
221 // -----------------------------------------------------------------------------
222  return ss.str();
223  }
224 );
225 
226 // FMADD_S ---------------------------------------------------------------------
227 static InstructionDefinition fmadd_s_rd_rm_rs1_rs2_rs3 (
228  ISA32_RV32IMACFD,
229  "fmadd_s",
230  (uint32_t) 0x000043,
231  (uint32_t) 0x600007f,
232  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
233  {
234 
235 // -----------------------------------------------------------------------------
236 
237 // -----------------------------------------------------------------------------
238 
239 // -----------------------------------------------------------------------------
240 etiss_uint8 rd = 0;
241 static BitArrayRange R_rd_0(11, 7);
242 rd += R_rd_0.read(ba) << 0;
243 etiss_uint8 rm = 0;
244 static BitArrayRange R_rm_0(14, 12);
245 rm += R_rm_0.read(ba) << 0;
246 etiss_uint8 rs1 = 0;
247 static BitArrayRange R_rs1_0(19, 15);
248 rs1 += R_rs1_0.read(ba) << 0;
249 etiss_uint8 rs2 = 0;
250 static BitArrayRange R_rs2_0(24, 20);
251 rs2 += R_rs2_0.read(ba) << 0;
252 etiss_uint8 rs3 = 0;
253 static BitArrayRange R_rs3_0(31, 27);
254 rs3 += R_rs3_0.read(ba) << 0;
255 
256 // -----------------------------------------------------------------------------
257 
258  {
259  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
260 
261  cp.code() = std::string("//FMADD_S\n");
262 
263 // -----------------------------------------------------------------------------
264 cp.code() += "etiss_coverage_count(1, 90);\n";
265 { // block
266 cp.code() += "etiss_coverage_count(1, 1169);\n";
267 cp.code() += "{ // block\n";
268 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
269 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
270 cp.code() += "} // block\n";
271 } // block
272 { // block
273 cp.code() += "etiss_coverage_count(1, 3542);\n";
274 cp.code() += "{ // block\n";
275 { // block
276 cp.code() += "etiss_coverage_count(1, 3526);\n";
277 cp.code() += "{ // block\n";
278 cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0LL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
279 cp.code() += "etiss_coverage_count(14, 3510, 3509, 3497, 3496, 3495, 3501, 3500, 3499, 3505, 3504, 3503, 3506, 3508, 3507);\n";
280 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
281 cp.code() += "etiss_coverage_count(6, 3525, 3513, 3512, 3524, 3523, 3521);\n";
282 cp.code() += "} // block\n";
283 } // block
284 cp.code() += "etiss_uint32 flags = fget_flags();\n";
285 cp.code() += "etiss_coverage_count(2, 3529, 3528);\n";
286 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
287 cp.code() += "etiss_coverage_count(9, 3541, 3530, 3540, 3534, 3531, 3535, 3538, 3536, 3539);\n";
288 cp.code() += "} // block\n";
289 } // block
290 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
291 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
292 // -----------------------------------------------------------------------------
293  cp.getAffectedRegisters().add("instructionPointer", 32);
294  }
295 
296  return true;
297  },
298  0,
299  [] (BitArray & ba, Instruction & instr)
300  {
301 // -----------------------------------------------------------------------------
302 etiss_uint8 rd = 0;
303 static BitArrayRange R_rd_0(11, 7);
304 rd += R_rd_0.read(ba) << 0;
305 etiss_uint8 rm = 0;
306 static BitArrayRange R_rm_0(14, 12);
307 rm += R_rm_0.read(ba) << 0;
308 etiss_uint8 rs1 = 0;
309 static BitArrayRange R_rs1_0(19, 15);
310 rs1 += R_rs1_0.read(ba) << 0;
311 etiss_uint8 rs2 = 0;
312 static BitArrayRange R_rs2_0(24, 20);
313 rs2 += R_rs2_0.read(ba) << 0;
314 etiss_uint8 rs3 = 0;
315 static BitArrayRange R_rs3_0(31, 27);
316 rs3 += R_rs3_0.read(ba) << 0;
317 
318 // -----------------------------------------------------------------------------
319 
320  std::stringstream ss;
321 // -----------------------------------------------------------------------------
322 ss << "fmadd_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]");
323 // -----------------------------------------------------------------------------
324  return ss.str();
325  }
326 );
327 
328 // FMSUB_S ---------------------------------------------------------------------
329 static InstructionDefinition fmsub_s_rd_rm_rs1_rs2_rs3 (
330  ISA32_RV32IMACFD,
331  "fmsub_s",
332  (uint32_t) 0x000047,
333  (uint32_t) 0x600007f,
334  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
335  {
336 
337 // -----------------------------------------------------------------------------
338 
339 // -----------------------------------------------------------------------------
340 
341 // -----------------------------------------------------------------------------
342 etiss_uint8 rd = 0;
343 static BitArrayRange R_rd_0(11, 7);
344 rd += R_rd_0.read(ba) << 0;
345 etiss_uint8 rm = 0;
346 static BitArrayRange R_rm_0(14, 12);
347 rm += R_rm_0.read(ba) << 0;
348 etiss_uint8 rs1 = 0;
349 static BitArrayRange R_rs1_0(19, 15);
350 rs1 += R_rs1_0.read(ba) << 0;
351 etiss_uint8 rs2 = 0;
352 static BitArrayRange R_rs2_0(24, 20);
353 rs2 += R_rs2_0.read(ba) << 0;
354 etiss_uint8 rs3 = 0;
355 static BitArrayRange R_rs3_0(31, 27);
356 rs3 += R_rs3_0.read(ba) << 0;
357 
358 // -----------------------------------------------------------------------------
359 
360  {
361  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
362 
363  cp.code() = std::string("//FMSUB_S\n");
364 
365 // -----------------------------------------------------------------------------
366 cp.code() += "etiss_coverage_count(1, 91);\n";
367 { // block
368 cp.code() += "etiss_coverage_count(1, 1169);\n";
369 cp.code() += "{ // block\n";
370 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
371 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
372 cp.code() += "} // block\n";
373 } // block
374 { // block
375 cp.code() += "etiss_coverage_count(1, 3613);\n";
376 cp.code() += "{ // block\n";
377 { // block
378 cp.code() += "etiss_coverage_count(1, 3597);\n";
379 cp.code() += "{ // block\n";
380 cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
381 cp.code() += "etiss_coverage_count(14, 3581, 3580, 3568, 3567, 3566, 3572, 3571, 3570, 3576, 3575, 3574, 3577, 3579, 3578);\n";
382 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
383 cp.code() += "etiss_coverage_count(6, 3596, 3584, 3583, 3595, 3594, 3592);\n";
384 cp.code() += "} // block\n";
385 } // block
386 cp.code() += "etiss_uint32 flags = fget_flags();\n";
387 cp.code() += "etiss_coverage_count(2, 3600, 3599);\n";
388 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
389 cp.code() += "etiss_coverage_count(9, 3612, 3601, 3611, 3605, 3602, 3606, 3609, 3607, 3610);\n";
390 cp.code() += "} // block\n";
391 } // block
392 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
393 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
394 // -----------------------------------------------------------------------------
395  cp.getAffectedRegisters().add("instructionPointer", 32);
396  }
397 
398  return true;
399  },
400  0,
401  [] (BitArray & ba, Instruction & instr)
402  {
403 // -----------------------------------------------------------------------------
404 etiss_uint8 rd = 0;
405 static BitArrayRange R_rd_0(11, 7);
406 rd += R_rd_0.read(ba) << 0;
407 etiss_uint8 rm = 0;
408 static BitArrayRange R_rm_0(14, 12);
409 rm += R_rm_0.read(ba) << 0;
410 etiss_uint8 rs1 = 0;
411 static BitArrayRange R_rs1_0(19, 15);
412 rs1 += R_rs1_0.read(ba) << 0;
413 etiss_uint8 rs2 = 0;
414 static BitArrayRange R_rs2_0(24, 20);
415 rs2 += R_rs2_0.read(ba) << 0;
416 etiss_uint8 rs3 = 0;
417 static BitArrayRange R_rs3_0(31, 27);
418 rs3 += R_rs3_0.read(ba) << 0;
419 
420 // -----------------------------------------------------------------------------
421 
422  std::stringstream ss;
423 // -----------------------------------------------------------------------------
424 ss << "fmsub_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]");
425 // -----------------------------------------------------------------------------
426  return ss.str();
427  }
428 );
429 
430 // FNMADD_S --------------------------------------------------------------------
431 static InstructionDefinition fnmadd_s_rd_rm_rs1_rs2_rs3 (
432  ISA32_RV32IMACFD,
433  "fnmadd_s",
434  (uint32_t) 0x00004f,
435  (uint32_t) 0x600007f,
436  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
437  {
438 
439 // -----------------------------------------------------------------------------
440 
441 // -----------------------------------------------------------------------------
442 
443 // -----------------------------------------------------------------------------
444 etiss_uint8 rd = 0;
445 static BitArrayRange R_rd_0(11, 7);
446 rd += R_rd_0.read(ba) << 0;
447 etiss_uint8 rm = 0;
448 static BitArrayRange R_rm_0(14, 12);
449 rm += R_rm_0.read(ba) << 0;
450 etiss_uint8 rs1 = 0;
451 static BitArrayRange R_rs1_0(19, 15);
452 rs1 += R_rs1_0.read(ba) << 0;
453 etiss_uint8 rs2 = 0;
454 static BitArrayRange R_rs2_0(24, 20);
455 rs2 += R_rs2_0.read(ba) << 0;
456 etiss_uint8 rs3 = 0;
457 static BitArrayRange R_rs3_0(31, 27);
458 rs3 += R_rs3_0.read(ba) << 0;
459 
460 // -----------------------------------------------------------------------------
461 
462  {
463  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
464 
465  cp.code() = std::string("//FNMADD_S\n");
466 
467 // -----------------------------------------------------------------------------
468 cp.code() += "etiss_coverage_count(1, 92);\n";
469 { // block
470 cp.code() += "etiss_coverage_count(1, 1169);\n";
471 cp.code() += "{ // block\n";
472 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
473 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
474 cp.code() += "} // block\n";
475 } // block
476 { // block
477 cp.code() += "etiss_coverage_count(1, 3693);\n";
478 cp.code() += "{ // block\n";
479 { // block
480 cp.code() += "etiss_coverage_count(1, 3677);\n";
481 cp.code() += "{ // block\n";
482 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
483 cp.code() += "etiss_coverage_count(4, 3640, 3639, 3638, 3637);\n";
484 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
485 cp.code() += "etiss_coverage_count(4, 3646, 3645, 3644, 3643);\n";
486 cp.code() += "etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]);\n";
487 cp.code() += "etiss_coverage_count(4, 3652, 3651, 3650, 3649);\n";
488 cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
489 cp.code() += "etiss_coverage_count(8, 3661, 3660, 3654, 3655, 3656, 3657, 3659, 3658);\n";
490 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
491 cp.code() += "etiss_coverage_count(6, 3676, 3664, 3663, 3675, 3674, 3672);\n";
492 cp.code() += "} // block\n";
493 } // block
494 cp.code() += "etiss_uint32 flags = fget_flags();\n";
495 cp.code() += "etiss_coverage_count(2, 3680, 3679);\n";
496 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
497 cp.code() += "etiss_coverage_count(9, 3692, 3681, 3691, 3685, 3682, 3686, 3689, 3687, 3690);\n";
498 cp.code() += "} // block\n";
499 } // block
500 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
501 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
502 // -----------------------------------------------------------------------------
503  cp.getAffectedRegisters().add("instructionPointer", 32);
504  }
505 
506  return true;
507  },
508  0,
509  [] (BitArray & ba, Instruction & instr)
510  {
511 // -----------------------------------------------------------------------------
512 etiss_uint8 rd = 0;
513 static BitArrayRange R_rd_0(11, 7);
514 rd += R_rd_0.read(ba) << 0;
515 etiss_uint8 rm = 0;
516 static BitArrayRange R_rm_0(14, 12);
517 rm += R_rm_0.read(ba) << 0;
518 etiss_uint8 rs1 = 0;
519 static BitArrayRange R_rs1_0(19, 15);
520 rs1 += R_rs1_0.read(ba) << 0;
521 etiss_uint8 rs2 = 0;
522 static BitArrayRange R_rs2_0(24, 20);
523 rs2 += R_rs2_0.read(ba) << 0;
524 etiss_uint8 rs3 = 0;
525 static BitArrayRange R_rs3_0(31, 27);
526 rs3 += R_rs3_0.read(ba) << 0;
527 
528 // -----------------------------------------------------------------------------
529 
530  std::stringstream ss;
531 // -----------------------------------------------------------------------------
532 ss << "fnmadd_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]");
533 // -----------------------------------------------------------------------------
534  return ss.str();
535  }
536 );
537 
538 // FNMSUB_S --------------------------------------------------------------------
539 static InstructionDefinition fnmsub_s_rd_rm_rs1_rs2_rs3 (
540  ISA32_RV32IMACFD,
541  "fnmsub_s",
542  (uint32_t) 0x00004b,
543  (uint32_t) 0x600007f,
544  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
545  {
546 
547 // -----------------------------------------------------------------------------
548 
549 // -----------------------------------------------------------------------------
550 
551 // -----------------------------------------------------------------------------
552 etiss_uint8 rd = 0;
553 static BitArrayRange R_rd_0(11, 7);
554 rd += R_rd_0.read(ba) << 0;
555 etiss_uint8 rm = 0;
556 static BitArrayRange R_rm_0(14, 12);
557 rm += R_rm_0.read(ba) << 0;
558 etiss_uint8 rs1 = 0;
559 static BitArrayRange R_rs1_0(19, 15);
560 rs1 += R_rs1_0.read(ba) << 0;
561 etiss_uint8 rs2 = 0;
562 static BitArrayRange R_rs2_0(24, 20);
563 rs2 += R_rs2_0.read(ba) << 0;
564 etiss_uint8 rs3 = 0;
565 static BitArrayRange R_rs3_0(31, 27);
566 rs3 += R_rs3_0.read(ba) << 0;
567 
568 // -----------------------------------------------------------------------------
569 
570  {
571  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
572 
573  cp.code() = std::string("//FNMSUB_S\n");
574 
575 // -----------------------------------------------------------------------------
576 cp.code() += "etiss_coverage_count(1, 93);\n";
577 { // block
578 cp.code() += "etiss_coverage_count(1, 1169);\n";
579 cp.code() += "{ // block\n";
580 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
581 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
582 cp.code() += "} // block\n";
583 } // block
584 { // block
585 cp.code() += "etiss_coverage_count(1, 3773);\n";
586 cp.code() += "{ // block\n";
587 { // block
588 cp.code() += "etiss_coverage_count(1, 3757);\n";
589 cp.code() += "{ // block\n";
590 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
591 cp.code() += "etiss_coverage_count(4, 3720, 3719, 3718, 3717);\n";
592 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
593 cp.code() += "etiss_coverage_count(4, 3726, 3725, 3724, 3723);\n";
594 cp.code() += "etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]);\n";
595 cp.code() += "etiss_coverage_count(4, 3732, 3731, 3730, 3729);\n";
596 cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
597 cp.code() += "etiss_coverage_count(8, 3741, 3740, 3734, 3735, 3736, 3737, 3739, 3738);\n";
598 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
599 cp.code() += "etiss_coverage_count(6, 3756, 3744, 3743, 3755, 3754, 3752);\n";
600 cp.code() += "} // block\n";
601 } // block
602 cp.code() += "etiss_uint32 flags = fget_flags();\n";
603 cp.code() += "etiss_coverage_count(2, 3760, 3759);\n";
604 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
605 cp.code() += "etiss_coverage_count(9, 3772, 3761, 3771, 3765, 3762, 3766, 3769, 3767, 3770);\n";
606 cp.code() += "} // block\n";
607 } // block
608 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
609 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
610 // -----------------------------------------------------------------------------
611  cp.getAffectedRegisters().add("instructionPointer", 32);
612  }
613 
614  return true;
615  },
616  0,
617  [] (BitArray & ba, Instruction & instr)
618  {
619 // -----------------------------------------------------------------------------
620 etiss_uint8 rd = 0;
621 static BitArrayRange R_rd_0(11, 7);
622 rd += R_rd_0.read(ba) << 0;
623 etiss_uint8 rm = 0;
624 static BitArrayRange R_rm_0(14, 12);
625 rm += R_rm_0.read(ba) << 0;
626 etiss_uint8 rs1 = 0;
627 static BitArrayRange R_rs1_0(19, 15);
628 rs1 += R_rs1_0.read(ba) << 0;
629 etiss_uint8 rs2 = 0;
630 static BitArrayRange R_rs2_0(24, 20);
631 rs2 += R_rs2_0.read(ba) << 0;
632 etiss_uint8 rs3 = 0;
633 static BitArrayRange R_rs3_0(31, 27);
634 rs3 += R_rs3_0.read(ba) << 0;
635 
636 // -----------------------------------------------------------------------------
637 
638  std::stringstream ss;
639 // -----------------------------------------------------------------------------
640 ss << "fnmsub_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]");
641 // -----------------------------------------------------------------------------
642  return ss.str();
643  }
644 );
645 
646 // FADD_S ----------------------------------------------------------------------
647 static InstructionDefinition fadd_s_rd_rm_rs1_rs2 (
648  ISA32_RV32IMACFD,
649  "fadd_s",
650  (uint32_t) 0x000053,
651  (uint32_t) 0xfe00007f,
652  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
653  {
654 
655 // -----------------------------------------------------------------------------
656 
657 // -----------------------------------------------------------------------------
658 
659 // -----------------------------------------------------------------------------
660 etiss_uint8 rd = 0;
661 static BitArrayRange R_rd_0(11, 7);
662 rd += R_rd_0.read(ba) << 0;
663 etiss_uint8 rm = 0;
664 static BitArrayRange R_rm_0(14, 12);
665 rm += R_rm_0.read(ba) << 0;
666 etiss_uint8 rs1 = 0;
667 static BitArrayRange R_rs1_0(19, 15);
668 rs1 += R_rs1_0.read(ba) << 0;
669 etiss_uint8 rs2 = 0;
670 static BitArrayRange R_rs2_0(24, 20);
671 rs2 += R_rs2_0.read(ba) << 0;
672 
673 // -----------------------------------------------------------------------------
674 
675  {
676  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
677 
678  cp.code() = std::string("//FADD_S\n");
679 
680 // -----------------------------------------------------------------------------
681 cp.code() += "etiss_coverage_count(1, 94);\n";
682 { // block
683 cp.code() += "etiss_coverage_count(1, 1169);\n";
684 cp.code() += "{ // block\n";
685 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
686 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
687 cp.code() += "} // block\n";
688 } // block
689 { // block
690 cp.code() += "etiss_coverage_count(1, 3841);\n";
691 cp.code() += "{ // block\n";
692 { // block
693 cp.code() += "etiss_coverage_count(1, 3825);\n";
694 cp.code() += "{ // block\n";
695 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
696 cp.code() += "etiss_coverage_count(4, 3796, 3795, 3794, 3793);\n";
697 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
698 cp.code() += "etiss_coverage_count(4, 3802, 3801, 3800, 3799);\n";
699 cp.code() += "etiss_uint32 res = fadd_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
700 cp.code() += "etiss_coverage_count(6, 3809, 3808, 3804, 3805, 3807, 3806);\n";
701 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
702 cp.code() += "etiss_coverage_count(6, 3824, 3812, 3811, 3823, 3822, 3820);\n";
703 cp.code() += "} // block\n";
704 } // block
705 cp.code() += "etiss_uint32 flags = fget_flags();\n";
706 cp.code() += "etiss_coverage_count(2, 3828, 3827);\n";
707 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
708 cp.code() += "etiss_coverage_count(9, 3840, 3829, 3839, 3833, 3830, 3834, 3837, 3835, 3838);\n";
709 cp.code() += "} // block\n";
710 } // block
711 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
712 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
713 // -----------------------------------------------------------------------------
714  cp.getAffectedRegisters().add("instructionPointer", 32);
715  }
716 
717  return true;
718  },
719  0,
720  [] (BitArray & ba, Instruction & instr)
721  {
722 // -----------------------------------------------------------------------------
723 etiss_uint8 rd = 0;
724 static BitArrayRange R_rd_0(11, 7);
725 rd += R_rd_0.read(ba) << 0;
726 etiss_uint8 rm = 0;
727 static BitArrayRange R_rm_0(14, 12);
728 rm += R_rm_0.read(ba) << 0;
729 etiss_uint8 rs1 = 0;
730 static BitArrayRange R_rs1_0(19, 15);
731 rs1 += R_rs1_0.read(ba) << 0;
732 etiss_uint8 rs2 = 0;
733 static BitArrayRange R_rs2_0(24, 20);
734 rs2 += R_rs2_0.read(ba) << 0;
735 
736 // -----------------------------------------------------------------------------
737 
738  std::stringstream ss;
739 // -----------------------------------------------------------------------------
740 ss << "fadd_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
741 // -----------------------------------------------------------------------------
742  return ss.str();
743  }
744 );
745 
746 // FSUB_S ----------------------------------------------------------------------
747 static InstructionDefinition fsub_s_rd_rm_rs1_rs2 (
748  ISA32_RV32IMACFD,
749  "fsub_s",
750  (uint32_t) 0x8000053,
751  (uint32_t) 0xfe00007f,
752  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
753  {
754 
755 // -----------------------------------------------------------------------------
756 
757 // -----------------------------------------------------------------------------
758 
759 // -----------------------------------------------------------------------------
760 etiss_uint8 rd = 0;
761 static BitArrayRange R_rd_0(11, 7);
762 rd += R_rd_0.read(ba) << 0;
763 etiss_uint8 rm = 0;
764 static BitArrayRange R_rm_0(14, 12);
765 rm += R_rm_0.read(ba) << 0;
766 etiss_uint8 rs1 = 0;
767 static BitArrayRange R_rs1_0(19, 15);
768 rs1 += R_rs1_0.read(ba) << 0;
769 etiss_uint8 rs2 = 0;
770 static BitArrayRange R_rs2_0(24, 20);
771 rs2 += R_rs2_0.read(ba) << 0;
772 
773 // -----------------------------------------------------------------------------
774 
775  {
776  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
777 
778  cp.code() = std::string("//FSUB_S\n");
779 
780 // -----------------------------------------------------------------------------
781 cp.code() += "etiss_coverage_count(1, 95);\n";
782 { // block
783 cp.code() += "etiss_coverage_count(1, 1169);\n";
784 cp.code() += "{ // block\n";
785 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
786 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
787 cp.code() += "} // block\n";
788 } // block
789 { // block
790 cp.code() += "etiss_coverage_count(1, 3909);\n";
791 cp.code() += "{ // block\n";
792 { // block
793 cp.code() += "etiss_coverage_count(1, 3893);\n";
794 cp.code() += "{ // block\n";
795 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
796 cp.code() += "etiss_coverage_count(4, 3864, 3863, 3862, 3861);\n";
797 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
798 cp.code() += "etiss_coverage_count(4, 3870, 3869, 3868, 3867);\n";
799 cp.code() += "etiss_uint32 res = fsub_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
800 cp.code() += "etiss_coverage_count(6, 3877, 3876, 3872, 3873, 3875, 3874);\n";
801 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
802 cp.code() += "etiss_coverage_count(6, 3892, 3880, 3879, 3891, 3890, 3888);\n";
803 cp.code() += "} // block\n";
804 } // block
805 cp.code() += "etiss_uint32 flags = fget_flags();\n";
806 cp.code() += "etiss_coverage_count(2, 3896, 3895);\n";
807 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
808 cp.code() += "etiss_coverage_count(9, 3908, 3897, 3907, 3901, 3898, 3902, 3905, 3903, 3906);\n";
809 cp.code() += "} // block\n";
810 } // block
811 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
812 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
813 // -----------------------------------------------------------------------------
814  cp.getAffectedRegisters().add("instructionPointer", 32);
815  }
816 
817  return true;
818  },
819  0,
820  [] (BitArray & ba, Instruction & instr)
821  {
822 // -----------------------------------------------------------------------------
823 etiss_uint8 rd = 0;
824 static BitArrayRange R_rd_0(11, 7);
825 rd += R_rd_0.read(ba) << 0;
826 etiss_uint8 rm = 0;
827 static BitArrayRange R_rm_0(14, 12);
828 rm += R_rm_0.read(ba) << 0;
829 etiss_uint8 rs1 = 0;
830 static BitArrayRange R_rs1_0(19, 15);
831 rs1 += R_rs1_0.read(ba) << 0;
832 etiss_uint8 rs2 = 0;
833 static BitArrayRange R_rs2_0(24, 20);
834 rs2 += R_rs2_0.read(ba) << 0;
835 
836 // -----------------------------------------------------------------------------
837 
838  std::stringstream ss;
839 // -----------------------------------------------------------------------------
840 ss << "fsub_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
841 // -----------------------------------------------------------------------------
842  return ss.str();
843  }
844 );
845 
846 // FMUL_S ----------------------------------------------------------------------
847 static InstructionDefinition fmul_s_rd_rm_rs1_rs2 (
848  ISA32_RV32IMACFD,
849  "fmul_s",
850  (uint32_t) 0x10000053,
851  (uint32_t) 0xfe00007f,
852  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
853  {
854 
855 // -----------------------------------------------------------------------------
856 
857 // -----------------------------------------------------------------------------
858 
859 // -----------------------------------------------------------------------------
860 etiss_uint8 rd = 0;
861 static BitArrayRange R_rd_0(11, 7);
862 rd += R_rd_0.read(ba) << 0;
863 etiss_uint8 rm = 0;
864 static BitArrayRange R_rm_0(14, 12);
865 rm += R_rm_0.read(ba) << 0;
866 etiss_uint8 rs1 = 0;
867 static BitArrayRange R_rs1_0(19, 15);
868 rs1 += R_rs1_0.read(ba) << 0;
869 etiss_uint8 rs2 = 0;
870 static BitArrayRange R_rs2_0(24, 20);
871 rs2 += R_rs2_0.read(ba) << 0;
872 
873 // -----------------------------------------------------------------------------
874 
875  {
876  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
877 
878  cp.code() = std::string("//FMUL_S\n");
879 
880 // -----------------------------------------------------------------------------
881 cp.code() += "etiss_coverage_count(1, 96);\n";
882 { // block
883 cp.code() += "etiss_coverage_count(1, 1169);\n";
884 cp.code() += "{ // block\n";
885 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
886 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
887 cp.code() += "} // block\n";
888 } // block
889 { // block
890 cp.code() += "etiss_coverage_count(1, 3977);\n";
891 cp.code() += "{ // block\n";
892 { // block
893 cp.code() += "etiss_coverage_count(1, 3961);\n";
894 cp.code() += "{ // block\n";
895 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
896 cp.code() += "etiss_coverage_count(4, 3932, 3931, 3930, 3929);\n";
897 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
898 cp.code() += "etiss_coverage_count(4, 3938, 3937, 3936, 3935);\n";
899 cp.code() += "etiss_uint32 res = fmul_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
900 cp.code() += "etiss_coverage_count(6, 3945, 3944, 3940, 3941, 3943, 3942);\n";
901 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
902 cp.code() += "etiss_coverage_count(6, 3960, 3948, 3947, 3959, 3958, 3956);\n";
903 cp.code() += "} // block\n";
904 } // block
905 cp.code() += "etiss_uint32 flags = fget_flags();\n";
906 cp.code() += "etiss_coverage_count(2, 3964, 3963);\n";
907 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
908 cp.code() += "etiss_coverage_count(9, 3976, 3965, 3975, 3969, 3966, 3970, 3973, 3971, 3974);\n";
909 cp.code() += "} // block\n";
910 } // block
911 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
912 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
913 // -----------------------------------------------------------------------------
914  cp.getAffectedRegisters().add("instructionPointer", 32);
915  }
916 
917  return true;
918  },
919  0,
920  [] (BitArray & ba, Instruction & instr)
921  {
922 // -----------------------------------------------------------------------------
923 etiss_uint8 rd = 0;
924 static BitArrayRange R_rd_0(11, 7);
925 rd += R_rd_0.read(ba) << 0;
926 etiss_uint8 rm = 0;
927 static BitArrayRange R_rm_0(14, 12);
928 rm += R_rm_0.read(ba) << 0;
929 etiss_uint8 rs1 = 0;
930 static BitArrayRange R_rs1_0(19, 15);
931 rs1 += R_rs1_0.read(ba) << 0;
932 etiss_uint8 rs2 = 0;
933 static BitArrayRange R_rs2_0(24, 20);
934 rs2 += R_rs2_0.read(ba) << 0;
935 
936 // -----------------------------------------------------------------------------
937 
938  std::stringstream ss;
939 // -----------------------------------------------------------------------------
940 ss << "fmul_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
941 // -----------------------------------------------------------------------------
942  return ss.str();
943  }
944 );
945 
946 // FDIV_S ----------------------------------------------------------------------
947 static InstructionDefinition fdiv_s_rd_rm_rs1_rs2 (
948  ISA32_RV32IMACFD,
949  "fdiv_s",
950  (uint32_t) 0x18000053,
951  (uint32_t) 0xfe00007f,
952  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
953  {
954 
955 // -----------------------------------------------------------------------------
956 
957 // -----------------------------------------------------------------------------
958 
959 // -----------------------------------------------------------------------------
960 etiss_uint8 rd = 0;
961 static BitArrayRange R_rd_0(11, 7);
962 rd += R_rd_0.read(ba) << 0;
963 etiss_uint8 rm = 0;
964 static BitArrayRange R_rm_0(14, 12);
965 rm += R_rm_0.read(ba) << 0;
966 etiss_uint8 rs1 = 0;
967 static BitArrayRange R_rs1_0(19, 15);
968 rs1 += R_rs1_0.read(ba) << 0;
969 etiss_uint8 rs2 = 0;
970 static BitArrayRange R_rs2_0(24, 20);
971 rs2 += R_rs2_0.read(ba) << 0;
972 
973 // -----------------------------------------------------------------------------
974 
975  {
976  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
977 
978  cp.code() = std::string("//FDIV_S\n");
979 
980 // -----------------------------------------------------------------------------
981 cp.code() += "etiss_coverage_count(1, 97);\n";
982 { // block
983 cp.code() += "etiss_coverage_count(1, 1169);\n";
984 cp.code() += "{ // block\n";
985 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
986 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
987 cp.code() += "} // block\n";
988 } // block
989 { // block
990 cp.code() += "etiss_coverage_count(1, 4045);\n";
991 cp.code() += "{ // block\n";
992 { // block
993 cp.code() += "etiss_coverage_count(1, 4029);\n";
994 cp.code() += "{ // block\n";
995 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
996 cp.code() += "etiss_coverage_count(4, 4000, 3999, 3998, 3997);\n";
997 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
998 cp.code() += "etiss_coverage_count(4, 4006, 4005, 4004, 4003);\n";
999 cp.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
1000 cp.code() += "etiss_coverage_count(6, 4013, 4012, 4008, 4009, 4011, 4010);\n";
1001 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
1002 cp.code() += "etiss_coverage_count(6, 4028, 4016, 4015, 4027, 4026, 4024);\n";
1003 cp.code() += "} // block\n";
1004 } // block
1005 cp.code() += "etiss_uint32 flags = fget_flags();\n";
1006 cp.code() += "etiss_coverage_count(2, 4032, 4031);\n";
1007 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1008 cp.code() += "etiss_coverage_count(9, 4044, 4033, 4043, 4037, 4034, 4038, 4041, 4039, 4042);\n";
1009 cp.code() += "} // block\n";
1010 } // block
1011 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1012 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1013 // -----------------------------------------------------------------------------
1014  cp.getAffectedRegisters().add("instructionPointer", 32);
1015  }
1016 
1017  return true;
1018  },
1019  0,
1020  [] (BitArray & ba, Instruction & instr)
1021  {
1022 // -----------------------------------------------------------------------------
1023 etiss_uint8 rd = 0;
1024 static BitArrayRange R_rd_0(11, 7);
1025 rd += R_rd_0.read(ba) << 0;
1026 etiss_uint8 rm = 0;
1027 static BitArrayRange R_rm_0(14, 12);
1028 rm += R_rm_0.read(ba) << 0;
1029 etiss_uint8 rs1 = 0;
1030 static BitArrayRange R_rs1_0(19, 15);
1031 rs1 += R_rs1_0.read(ba) << 0;
1032 etiss_uint8 rs2 = 0;
1033 static BitArrayRange R_rs2_0(24, 20);
1034 rs2 += R_rs2_0.read(ba) << 0;
1035 
1036 // -----------------------------------------------------------------------------
1037 
1038  std::stringstream ss;
1039 // -----------------------------------------------------------------------------
1040 ss << "fdiv_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1041 // -----------------------------------------------------------------------------
1042  return ss.str();
1043  }
1044 );
1045 
1046 // FSQRT_S ---------------------------------------------------------------------
1047 static InstructionDefinition fsqrt_s_rd_rm_rs1 (
1048  ISA32_RV32IMACFD,
1049  "fsqrt_s",
1050  (uint32_t) 0x58000053,
1051  (uint32_t) 0xfff0007f,
1052  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1053  {
1054 
1055 // -----------------------------------------------------------------------------
1056 
1057 // -----------------------------------------------------------------------------
1058 
1059 // -----------------------------------------------------------------------------
1060 etiss_uint8 rd = 0;
1061 static BitArrayRange R_rd_0(11, 7);
1062 rd += R_rd_0.read(ba) << 0;
1063 etiss_uint8 rm = 0;
1064 static BitArrayRange R_rm_0(14, 12);
1065 rm += R_rm_0.read(ba) << 0;
1066 etiss_uint8 rs1 = 0;
1067 static BitArrayRange R_rs1_0(19, 15);
1068 rs1 += R_rs1_0.read(ba) << 0;
1069 
1070 // -----------------------------------------------------------------------------
1071 
1072  {
1073  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1074 
1075  cp.code() = std::string("//FSQRT_S\n");
1076 
1077 // -----------------------------------------------------------------------------
1078 cp.code() += "etiss_coverage_count(1, 98);\n";
1079 { // block
1080 cp.code() += "etiss_coverage_count(1, 1169);\n";
1081 cp.code() += "{ // block\n";
1082 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1083 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1084 cp.code() += "} // block\n";
1085 } // block
1086 { // block
1087 cp.code() += "etiss_coverage_count(1, 4103);\n";
1088 cp.code() += "{ // block\n";
1089 { // block
1090 cp.code() += "etiss_coverage_count(1, 4087);\n";
1091 cp.code() += "{ // block\n";
1092 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
1093 cp.code() += "etiss_coverage_count(4, 4065, 4064, 4063, 4062);\n";
1094 cp.code() += "etiss_uint32 res = fsqrt_s(frs1, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
1095 cp.code() += "etiss_coverage_count(5, 4071, 4070, 4067, 4069, 4068);\n";
1096 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
1097 cp.code() += "etiss_coverage_count(6, 4086, 4074, 4073, 4085, 4084, 4082);\n";
1098 cp.code() += "} // block\n";
1099 } // block
1100 cp.code() += "etiss_uint32 flags = fget_flags();\n";
1101 cp.code() += "etiss_coverage_count(2, 4090, 4089);\n";
1102 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1103 cp.code() += "etiss_coverage_count(9, 4102, 4091, 4101, 4095, 4092, 4096, 4099, 4097, 4100);\n";
1104 cp.code() += "} // block\n";
1105 } // block
1106 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1107 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1108 // -----------------------------------------------------------------------------
1109  cp.getAffectedRegisters().add("instructionPointer", 32);
1110  }
1111 
1112  return true;
1113  },
1114  0,
1115  [] (BitArray & ba, Instruction & instr)
1116  {
1117 // -----------------------------------------------------------------------------
1118 etiss_uint8 rd = 0;
1119 static BitArrayRange R_rd_0(11, 7);
1120 rd += R_rd_0.read(ba) << 0;
1121 etiss_uint8 rm = 0;
1122 static BitArrayRange R_rm_0(14, 12);
1123 rm += R_rm_0.read(ba) << 0;
1124 etiss_uint8 rs1 = 0;
1125 static BitArrayRange R_rs1_0(19, 15);
1126 rs1 += R_rs1_0.read(ba) << 0;
1127 
1128 // -----------------------------------------------------------------------------
1129 
1130  std::stringstream ss;
1131 // -----------------------------------------------------------------------------
1132 ss << "fsqrt_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
1133 // -----------------------------------------------------------------------------
1134  return ss.str();
1135  }
1136 );
1137 
1138 // FSGNJ_S ---------------------------------------------------------------------
1139 static InstructionDefinition fsgnj_s_rd_rs1_rs2 (
1140  ISA32_RV32IMACFD,
1141  "fsgnj_s",
1142  (uint32_t) 0x20000053,
1143  (uint32_t) 0xfe00707f,
1144  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1145  {
1146 
1147 // -----------------------------------------------------------------------------
1148 
1149 // -----------------------------------------------------------------------------
1150 
1151 // -----------------------------------------------------------------------------
1152 etiss_uint8 rd = 0;
1153 static BitArrayRange R_rd_0(11, 7);
1154 rd += R_rd_0.read(ba) << 0;
1155 etiss_uint8 rs1 = 0;
1156 static BitArrayRange R_rs1_0(19, 15);
1157 rs1 += R_rs1_0.read(ba) << 0;
1158 etiss_uint8 rs2 = 0;
1159 static BitArrayRange R_rs2_0(24, 20);
1160 rs2 += R_rs2_0.read(ba) << 0;
1161 
1162 // -----------------------------------------------------------------------------
1163 
1164  {
1165  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1166 
1167  cp.code() = std::string("//FSGNJ_S\n");
1168 
1169 // -----------------------------------------------------------------------------
1170 cp.code() += "etiss_coverage_count(1, 99);\n";
1171 { // block
1172 cp.code() += "etiss_coverage_count(1, 1169);\n";
1173 cp.code() += "{ // block\n";
1174 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1175 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1176 cp.code() += "} // block\n";
1177 } // block
1178 { // block
1179 cp.code() += "etiss_coverage_count(1, 4162);\n";
1180 cp.code() += "{ // block\n";
1181 { // block
1182 cp.code() += "etiss_coverage_count(1, 4161);\n";
1183 cp.code() += "{ // block\n";
1184 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
1185 cp.code() += "etiss_coverage_count(4, 4130, 4129, 4128, 4127);\n";
1186 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
1187 cp.code() += "etiss_coverage_count(4, 4136, 4135, 4134, 4133);\n";
1188 cp.code() += "etiss_uint32 res = ((((((frs2) >> (31ULL)) & 1ULL)) << 31) | ((((frs1) >> (0LL)) & 2147483647ULL)));\n";
1189 cp.code() += "etiss_coverage_count(10, 4147, 4146, 4141, 4138, 4139, 4140, 4145, 4142, 4143, 4144);\n";
1190 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
1191 cp.code() += "etiss_coverage_count(6, 4160, 4150, 4149, 4159, 4158, 4156);\n";
1192 cp.code() += "} // block\n";
1193 } // block
1194 cp.code() += "} // block\n";
1195 } // block
1196 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1197 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1198 // -----------------------------------------------------------------------------
1199  cp.getAffectedRegisters().add("instructionPointer", 32);
1200  }
1201 
1202  return true;
1203  },
1204  0,
1205  [] (BitArray & ba, Instruction & instr)
1206  {
1207 // -----------------------------------------------------------------------------
1208 etiss_uint8 rd = 0;
1209 static BitArrayRange R_rd_0(11, 7);
1210 rd += R_rd_0.read(ba) << 0;
1211 etiss_uint8 rs1 = 0;
1212 static BitArrayRange R_rs1_0(19, 15);
1213 rs1 += R_rs1_0.read(ba) << 0;
1214 etiss_uint8 rs2 = 0;
1215 static BitArrayRange R_rs2_0(24, 20);
1216 rs2 += R_rs2_0.read(ba) << 0;
1217 
1218 // -----------------------------------------------------------------------------
1219 
1220  std::stringstream ss;
1221 // -----------------------------------------------------------------------------
1222 ss << "fsgnj_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1223 // -----------------------------------------------------------------------------
1224  return ss.str();
1225  }
1226 );
1227 
1228 // FSGNJN_S --------------------------------------------------------------------
1229 static InstructionDefinition fsgnjn_s_rd_rs1_rs2 (
1230  ISA32_RV32IMACFD,
1231  "fsgnjn_s",
1232  (uint32_t) 0x20001053,
1233  (uint32_t) 0xfe00707f,
1234  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1235  {
1236 
1237 // -----------------------------------------------------------------------------
1238 
1239 // -----------------------------------------------------------------------------
1240 
1241 // -----------------------------------------------------------------------------
1242 etiss_uint8 rd = 0;
1243 static BitArrayRange R_rd_0(11, 7);
1244 rd += R_rd_0.read(ba) << 0;
1245 etiss_uint8 rs1 = 0;
1246 static BitArrayRange R_rs1_0(19, 15);
1247 rs1 += R_rs1_0.read(ba) << 0;
1248 etiss_uint8 rs2 = 0;
1249 static BitArrayRange R_rs2_0(24, 20);
1250 rs2 += R_rs2_0.read(ba) << 0;
1251 
1252 // -----------------------------------------------------------------------------
1253 
1254  {
1255  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1256 
1257  cp.code() = std::string("//FSGNJN_S\n");
1258 
1259 // -----------------------------------------------------------------------------
1260 cp.code() += "etiss_coverage_count(1, 100);\n";
1261 { // block
1262 cp.code() += "etiss_coverage_count(1, 1169);\n";
1263 cp.code() += "{ // block\n";
1264 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1265 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1266 cp.code() += "} // block\n";
1267 } // block
1268 { // block
1269 cp.code() += "etiss_coverage_count(1, 4223);\n";
1270 cp.code() += "{ // block\n";
1271 { // block
1272 cp.code() += "etiss_coverage_count(1, 4222);\n";
1273 cp.code() += "{ // block\n";
1274 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
1275 cp.code() += "etiss_coverage_count(4, 4190, 4189, 4188, 4187);\n";
1276 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
1277 cp.code() += "etiss_coverage_count(4, 4196, 4195, 4194, 4193);\n";
1278 cp.code() += "etiss_uint32 res = (((~((((frs2) >> (31ULL)) & 1ULL))) << 31) | ((((frs1) >> (0LL)) & 2147483647ULL)));\n";
1279 cp.code() += "etiss_coverage_count(11, 4208, 4207, 4202, 4201, 4198, 4199, 4200, 4206, 4203, 4204, 4205);\n";
1280 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
1281 cp.code() += "etiss_coverage_count(6, 4221, 4211, 4210, 4220, 4219, 4217);\n";
1282 cp.code() += "} // block\n";
1283 } // block
1284 cp.code() += "} // block\n";
1285 } // block
1286 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1287 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1288 // -----------------------------------------------------------------------------
1289  cp.getAffectedRegisters().add("instructionPointer", 32);
1290  }
1291 
1292  return true;
1293  },
1294  0,
1295  [] (BitArray & ba, Instruction & instr)
1296  {
1297 // -----------------------------------------------------------------------------
1298 etiss_uint8 rd = 0;
1299 static BitArrayRange R_rd_0(11, 7);
1300 rd += R_rd_0.read(ba) << 0;
1301 etiss_uint8 rs1 = 0;
1302 static BitArrayRange R_rs1_0(19, 15);
1303 rs1 += R_rs1_0.read(ba) << 0;
1304 etiss_uint8 rs2 = 0;
1305 static BitArrayRange R_rs2_0(24, 20);
1306 rs2 += R_rs2_0.read(ba) << 0;
1307 
1308 // -----------------------------------------------------------------------------
1309 
1310  std::stringstream ss;
1311 // -----------------------------------------------------------------------------
1312 ss << "fsgnjn_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1313 // -----------------------------------------------------------------------------
1314  return ss.str();
1315  }
1316 );
1317 
1318 // FSGNJX_S --------------------------------------------------------------------
1319 static InstructionDefinition fsgnjx_s_rd_rs1_rs2 (
1320  ISA32_RV32IMACFD,
1321  "fsgnjx_s",
1322  (uint32_t) 0x20002053,
1323  (uint32_t) 0xfe00707f,
1324  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1325  {
1326 
1327 // -----------------------------------------------------------------------------
1328 
1329 // -----------------------------------------------------------------------------
1330 
1331 // -----------------------------------------------------------------------------
1332 etiss_uint8 rd = 0;
1333 static BitArrayRange R_rd_0(11, 7);
1334 rd += R_rd_0.read(ba) << 0;
1335 etiss_uint8 rs1 = 0;
1336 static BitArrayRange R_rs1_0(19, 15);
1337 rs1 += R_rs1_0.read(ba) << 0;
1338 etiss_uint8 rs2 = 0;
1339 static BitArrayRange R_rs2_0(24, 20);
1340 rs2 += R_rs2_0.read(ba) << 0;
1341 
1342 // -----------------------------------------------------------------------------
1343 
1344  {
1345  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1346 
1347  cp.code() = std::string("//FSGNJX_S\n");
1348 
1349 // -----------------------------------------------------------------------------
1350 cp.code() += "etiss_coverage_count(1, 101);\n";
1351 { // block
1352 cp.code() += "etiss_coverage_count(1, 1169);\n";
1353 cp.code() += "{ // block\n";
1354 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1355 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1356 cp.code() += "} // block\n";
1357 } // block
1358 { // block
1359 cp.code() += "etiss_coverage_count(1, 4278);\n";
1360 cp.code() += "{ // block\n";
1361 { // block
1362 cp.code() += "etiss_coverage_count(1, 4277);\n";
1363 cp.code() += "{ // block\n";
1364 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
1365 cp.code() += "etiss_coverage_count(4, 4247, 4246, 4245, 4244);\n";
1366 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
1367 cp.code() += "etiss_coverage_count(4, 4253, 4252, 4251, 4250);\n";
1368 cp.code() += "etiss_uint32 res = frs1 ^ (frs2 & 2147483648ULL);\n";
1369 cp.code() += "etiss_coverage_count(7, 4261, 4260, 4255, 4258, 4256, 4257, 4259);\n";
1370 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
1371 cp.code() += "etiss_coverage_count(6, 4276, 4264, 4263, 4275, 4274, 4272);\n";
1372 cp.code() += "} // block\n";
1373 } // block
1374 cp.code() += "} // block\n";
1375 } // block
1376 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1377 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1378 // -----------------------------------------------------------------------------
1379  cp.getAffectedRegisters().add("instructionPointer", 32);
1380  }
1381 
1382  return true;
1383  },
1384  0,
1385  [] (BitArray & ba, Instruction & instr)
1386  {
1387 // -----------------------------------------------------------------------------
1388 etiss_uint8 rd = 0;
1389 static BitArrayRange R_rd_0(11, 7);
1390 rd += R_rd_0.read(ba) << 0;
1391 etiss_uint8 rs1 = 0;
1392 static BitArrayRange R_rs1_0(19, 15);
1393 rs1 += R_rs1_0.read(ba) << 0;
1394 etiss_uint8 rs2 = 0;
1395 static BitArrayRange R_rs2_0(24, 20);
1396 rs2 += R_rs2_0.read(ba) << 0;
1397 
1398 // -----------------------------------------------------------------------------
1399 
1400  std::stringstream ss;
1401 // -----------------------------------------------------------------------------
1402 ss << "fsgnjx_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1403 // -----------------------------------------------------------------------------
1404  return ss.str();
1405  }
1406 );
1407 
1408 // FMIN_S ----------------------------------------------------------------------
1409 static InstructionDefinition fmin_s_rd_rs1_rs2 (
1410  ISA32_RV32IMACFD,
1411  "fmin_s",
1412  (uint32_t) 0x28000053,
1413  (uint32_t) 0xfe00707f,
1414  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1415  {
1416 
1417 // -----------------------------------------------------------------------------
1418 
1419 // -----------------------------------------------------------------------------
1420 
1421 // -----------------------------------------------------------------------------
1422 etiss_uint8 rd = 0;
1423 static BitArrayRange R_rd_0(11, 7);
1424 rd += R_rd_0.read(ba) << 0;
1425 etiss_uint8 rs1 = 0;
1426 static BitArrayRange R_rs1_0(19, 15);
1427 rs1 += R_rs1_0.read(ba) << 0;
1428 etiss_uint8 rs2 = 0;
1429 static BitArrayRange R_rs2_0(24, 20);
1430 rs2 += R_rs2_0.read(ba) << 0;
1431 
1432 // -----------------------------------------------------------------------------
1433 
1434  {
1435  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1436 
1437  cp.code() = std::string("//FMIN_S\n");
1438 
1439 // -----------------------------------------------------------------------------
1440 cp.code() += "etiss_coverage_count(1, 102);\n";
1441 { // block
1442 cp.code() += "etiss_coverage_count(1, 1169);\n";
1443 cp.code() += "{ // block\n";
1444 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1445 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1446 cp.code() += "} // block\n";
1447 } // block
1448 { // block
1449 cp.code() += "etiss_coverage_count(1, 4344);\n";
1450 cp.code() += "{ // block\n";
1451 { // block
1452 cp.code() += "etiss_coverage_count(1, 4328);\n";
1453 cp.code() += "{ // block\n";
1454 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
1455 cp.code() += "etiss_coverage_count(4, 4300, 4299, 4298, 4297);\n";
1456 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
1457 cp.code() += "etiss_coverage_count(4, 4306, 4305, 4304, 4303);\n";
1458 cp.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 0LL);\n";
1459 cp.code() += "etiss_coverage_count(5, 4312, 4311, 4308, 4309, 4310);\n";
1460 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
1461 cp.code() += "etiss_coverage_count(6, 4327, 4315, 4314, 4326, 4325, 4323);\n";
1462 cp.code() += "} // block\n";
1463 } // block
1464 cp.code() += "etiss_uint32 flags = fget_flags();\n";
1465 cp.code() += "etiss_coverage_count(2, 4331, 4330);\n";
1466 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1467 cp.code() += "etiss_coverage_count(9, 4343, 4332, 4342, 4336, 4333, 4337, 4340, 4338, 4341);\n";
1468 cp.code() += "} // block\n";
1469 } // block
1470 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1471 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1472 // -----------------------------------------------------------------------------
1473  cp.getAffectedRegisters().add("instructionPointer", 32);
1474  }
1475 
1476  return true;
1477  },
1478  0,
1479  [] (BitArray & ba, Instruction & instr)
1480  {
1481 // -----------------------------------------------------------------------------
1482 etiss_uint8 rd = 0;
1483 static BitArrayRange R_rd_0(11, 7);
1484 rd += R_rd_0.read(ba) << 0;
1485 etiss_uint8 rs1 = 0;
1486 static BitArrayRange R_rs1_0(19, 15);
1487 rs1 += R_rs1_0.read(ba) << 0;
1488 etiss_uint8 rs2 = 0;
1489 static BitArrayRange R_rs2_0(24, 20);
1490 rs2 += R_rs2_0.read(ba) << 0;
1491 
1492 // -----------------------------------------------------------------------------
1493 
1494  std::stringstream ss;
1495 // -----------------------------------------------------------------------------
1496 ss << "fmin_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1497 // -----------------------------------------------------------------------------
1498  return ss.str();
1499  }
1500 );
1501 
1502 // FMAX_S ----------------------------------------------------------------------
1503 static InstructionDefinition fmax_s_rd_rs1_rs2 (
1504  ISA32_RV32IMACFD,
1505  "fmax_s",
1506  (uint32_t) 0x28001053,
1507  (uint32_t) 0xfe00707f,
1508  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1509  {
1510 
1511 // -----------------------------------------------------------------------------
1512 
1513 // -----------------------------------------------------------------------------
1514 
1515 // -----------------------------------------------------------------------------
1516 etiss_uint8 rd = 0;
1517 static BitArrayRange R_rd_0(11, 7);
1518 rd += R_rd_0.read(ba) << 0;
1519 etiss_uint8 rs1 = 0;
1520 static BitArrayRange R_rs1_0(19, 15);
1521 rs1 += R_rs1_0.read(ba) << 0;
1522 etiss_uint8 rs2 = 0;
1523 static BitArrayRange R_rs2_0(24, 20);
1524 rs2 += R_rs2_0.read(ba) << 0;
1525 
1526 // -----------------------------------------------------------------------------
1527 
1528  {
1529  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1530 
1531  cp.code() = std::string("//FMAX_S\n");
1532 
1533 // -----------------------------------------------------------------------------
1534 cp.code() += "etiss_coverage_count(1, 103);\n";
1535 { // block
1536 cp.code() += "etiss_coverage_count(1, 1169);\n";
1537 cp.code() += "{ // block\n";
1538 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1539 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1540 cp.code() += "} // block\n";
1541 } // block
1542 { // block
1543 cp.code() += "etiss_coverage_count(1, 4410);\n";
1544 cp.code() += "{ // block\n";
1545 { // block
1546 cp.code() += "etiss_coverage_count(1, 4394);\n";
1547 cp.code() += "{ // block\n";
1548 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
1549 cp.code() += "etiss_coverage_count(4, 4366, 4365, 4364, 4363);\n";
1550 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
1551 cp.code() += "etiss_coverage_count(4, 4372, 4371, 4370, 4369);\n";
1552 cp.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 1ULL);\n";
1553 cp.code() += "etiss_coverage_count(5, 4378, 4377, 4374, 4375, 4376);\n";
1554 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
1555 cp.code() += "etiss_coverage_count(6, 4393, 4381, 4380, 4392, 4391, 4389);\n";
1556 cp.code() += "} // block\n";
1557 } // block
1558 cp.code() += "etiss_uint32 flags = fget_flags();\n";
1559 cp.code() += "etiss_coverage_count(2, 4397, 4396);\n";
1560 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1561 cp.code() += "etiss_coverage_count(9, 4409, 4398, 4408, 4402, 4399, 4403, 4406, 4404, 4407);\n";
1562 cp.code() += "} // block\n";
1563 } // block
1564 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1565 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1566 // -----------------------------------------------------------------------------
1567  cp.getAffectedRegisters().add("instructionPointer", 32);
1568  }
1569 
1570  return true;
1571  },
1572  0,
1573  [] (BitArray & ba, Instruction & instr)
1574  {
1575 // -----------------------------------------------------------------------------
1576 etiss_uint8 rd = 0;
1577 static BitArrayRange R_rd_0(11, 7);
1578 rd += R_rd_0.read(ba) << 0;
1579 etiss_uint8 rs1 = 0;
1580 static BitArrayRange R_rs1_0(19, 15);
1581 rs1 += R_rs1_0.read(ba) << 0;
1582 etiss_uint8 rs2 = 0;
1583 static BitArrayRange R_rs2_0(24, 20);
1584 rs2 += R_rs2_0.read(ba) << 0;
1585 
1586 // -----------------------------------------------------------------------------
1587 
1588  std::stringstream ss;
1589 // -----------------------------------------------------------------------------
1590 ss << "fmax_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1591 // -----------------------------------------------------------------------------
1592  return ss.str();
1593  }
1594 );
1595 
1596 // FCVT_W_S --------------------------------------------------------------------
1597 static InstructionDefinition fcvt_w_s_rd_rm_rs1 (
1598  ISA32_RV32IMACFD,
1599  "fcvt_w_s",
1600  (uint32_t) 0xc0000053,
1601  (uint32_t) 0xfff0007f,
1602  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1603  {
1604 
1605 // -----------------------------------------------------------------------------
1606 
1607 // -----------------------------------------------------------------------------
1608 
1609 // -----------------------------------------------------------------------------
1610 etiss_uint8 rd = 0;
1611 static BitArrayRange R_rd_0(11, 7);
1612 rd += R_rd_0.read(ba) << 0;
1613 etiss_uint8 rm = 0;
1614 static BitArrayRange R_rm_0(14, 12);
1615 rm += R_rm_0.read(ba) << 0;
1616 etiss_uint8 rs1 = 0;
1617 static BitArrayRange R_rs1_0(19, 15);
1618 rs1 += R_rs1_0.read(ba) << 0;
1619 
1620 // -----------------------------------------------------------------------------
1621 
1622  {
1623  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1624 
1625  cp.code() = std::string("//FCVT_W_S\n");
1626 
1627 // -----------------------------------------------------------------------------
1628 cp.code() += "etiss_coverage_count(1, 104);\n";
1629 { // block
1630 cp.code() += "etiss_coverage_count(1, 1169);\n";
1631 cp.code() += "{ // block\n";
1632 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1633 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1634 cp.code() += "} // block\n";
1635 } // block
1636 { // block
1637 cp.code() += "etiss_coverage_count(1, 4468);\n";
1638 cp.code() += "{ // block\n";
1639 cp.code() += "etiss_int32 res = 0LL;\n";
1640 cp.code() += "etiss_coverage_count(2, 4413, 4412);\n";
1641 { // block
1642 cp.code() += "etiss_coverage_count(1, 4438);\n";
1643 cp.code() += "{ // block\n";
1644 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
1645 cp.code() += "etiss_coverage_count(4, 4431, 4430, 4429, 4428);\n";
1646 cp.code() += "res = fcvt_s(frs1, 0LL, " + std::to_string(rm) + "ULL);\n";
1647 cp.code() += "etiss_coverage_count(6, 4437, 4432, 4436, 4433, 4434, 4435);\n";
1648 cp.code() += "} // block\n";
1649 } // block
1650 cp.code() += "etiss_coverage_count(1, 4439);\n";
1651 if ((rd % 32ULL) != 0LL) { // conditional
1652 cp.code() += "etiss_coverage_count(5, 4445, 4442, 4440, 4443, 4444);\n";
1653 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
1654 cp.code() += "etiss_coverage_count(5, 4452, 4450, 4449, 4447, 4451);\n";
1655 } // conditional
1656 cp.code() += "etiss_uint32 flags = fget_flags();\n";
1657 cp.code() += "etiss_coverage_count(2, 4455, 4454);\n";
1658 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1659 cp.code() += "etiss_coverage_count(9, 4467, 4456, 4466, 4460, 4457, 4461, 4464, 4462, 4465);\n";
1660 cp.code() += "} // block\n";
1661 } // block
1662 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1663 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1664 // -----------------------------------------------------------------------------
1665  cp.getAffectedRegisters().add("instructionPointer", 32);
1666  }
1667 
1668  return true;
1669  },
1670  0,
1671  [] (BitArray & ba, Instruction & instr)
1672  {
1673 // -----------------------------------------------------------------------------
1674 etiss_uint8 rd = 0;
1675 static BitArrayRange R_rd_0(11, 7);
1676 rd += R_rd_0.read(ba) << 0;
1677 etiss_uint8 rm = 0;
1678 static BitArrayRange R_rm_0(14, 12);
1679 rm += R_rm_0.read(ba) << 0;
1680 etiss_uint8 rs1 = 0;
1681 static BitArrayRange R_rs1_0(19, 15);
1682 rs1 += R_rs1_0.read(ba) << 0;
1683 
1684 // -----------------------------------------------------------------------------
1685 
1686  std::stringstream ss;
1687 // -----------------------------------------------------------------------------
1688 ss << "fcvt_w_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
1689 // -----------------------------------------------------------------------------
1690  return ss.str();
1691  }
1692 );
1693 
1694 // FCVT_WU_S -------------------------------------------------------------------
1695 static InstructionDefinition fcvt_wu_s_rd_rm_rs1 (
1696  ISA32_RV32IMACFD,
1697  "fcvt_wu_s",
1698  (uint32_t) 0xc0100053,
1699  (uint32_t) 0xfff0007f,
1700  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1701  {
1702 
1703 // -----------------------------------------------------------------------------
1704 
1705 // -----------------------------------------------------------------------------
1706 
1707 // -----------------------------------------------------------------------------
1708 etiss_uint8 rd = 0;
1709 static BitArrayRange R_rd_0(11, 7);
1710 rd += R_rd_0.read(ba) << 0;
1711 etiss_uint8 rm = 0;
1712 static BitArrayRange R_rm_0(14, 12);
1713 rm += R_rm_0.read(ba) << 0;
1714 etiss_uint8 rs1 = 0;
1715 static BitArrayRange R_rs1_0(19, 15);
1716 rs1 += R_rs1_0.read(ba) << 0;
1717 
1718 // -----------------------------------------------------------------------------
1719 
1720  {
1721  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1722 
1723  cp.code() = std::string("//FCVT_WU_S\n");
1724 
1725 // -----------------------------------------------------------------------------
1726 cp.code() += "etiss_coverage_count(1, 105);\n";
1727 { // block
1728 cp.code() += "etiss_coverage_count(1, 1169);\n";
1729 cp.code() += "{ // block\n";
1730 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1731 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1732 cp.code() += "} // block\n";
1733 } // block
1734 { // block
1735 cp.code() += "etiss_coverage_count(1, 4529);\n";
1736 cp.code() += "{ // block\n";
1737 cp.code() += "etiss_uint32 res = 0LL;\n";
1738 cp.code() += "etiss_coverage_count(2, 4471, 4470);\n";
1739 { // block
1740 cp.code() += "etiss_coverage_count(1, 4496);\n";
1741 cp.code() += "{ // block\n";
1742 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
1743 cp.code() += "etiss_coverage_count(4, 4489, 4488, 4487, 4486);\n";
1744 cp.code() += "res = fcvt_s(frs1, 1ULL, " + std::to_string(rm) + "ULL);\n";
1745 cp.code() += "etiss_coverage_count(6, 4495, 4490, 4494, 4491, 4492, 4493);\n";
1746 cp.code() += "} // block\n";
1747 } // block
1748 cp.code() += "etiss_coverage_count(1, 4497);\n";
1749 if ((rd % 32ULL) != 0LL) { // conditional
1750 cp.code() += "etiss_coverage_count(5, 4503, 4500, 4498, 4501, 4502);\n";
1751 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)((etiss_int32)(res));\n";
1752 cp.code() += "etiss_coverage_count(7, 4513, 4508, 4507, 4505, 4512, 4510, 4509);\n";
1753 } // conditional
1754 cp.code() += "etiss_uint32 flags = fget_flags();\n";
1755 cp.code() += "etiss_coverage_count(2, 4516, 4515);\n";
1756 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1757 cp.code() += "etiss_coverage_count(9, 4528, 4517, 4527, 4521, 4518, 4522, 4525, 4523, 4526);\n";
1758 cp.code() += "} // block\n";
1759 } // block
1760 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1761 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1762 // -----------------------------------------------------------------------------
1763  cp.getAffectedRegisters().add("instructionPointer", 32);
1764  }
1765 
1766  return true;
1767  },
1768  0,
1769  [] (BitArray & ba, Instruction & instr)
1770  {
1771 // -----------------------------------------------------------------------------
1772 etiss_uint8 rd = 0;
1773 static BitArrayRange R_rd_0(11, 7);
1774 rd += R_rd_0.read(ba) << 0;
1775 etiss_uint8 rm = 0;
1776 static BitArrayRange R_rm_0(14, 12);
1777 rm += R_rm_0.read(ba) << 0;
1778 etiss_uint8 rs1 = 0;
1779 static BitArrayRange R_rs1_0(19, 15);
1780 rs1 += R_rs1_0.read(ba) << 0;
1781 
1782 // -----------------------------------------------------------------------------
1783 
1784  std::stringstream ss;
1785 // -----------------------------------------------------------------------------
1786 ss << "fcvt_wu_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
1787 // -----------------------------------------------------------------------------
1788  return ss.str();
1789  }
1790 );
1791 
1792 // FEQ_S -----------------------------------------------------------------------
1793 static InstructionDefinition feq_s_rd_rs1_rs2 (
1794  ISA32_RV32IMACFD,
1795  "feq_s",
1796  (uint32_t) 0xa0002053,
1797  (uint32_t) 0xfe00707f,
1798  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1799  {
1800 
1801 // -----------------------------------------------------------------------------
1802 
1803 // -----------------------------------------------------------------------------
1804 
1805 // -----------------------------------------------------------------------------
1806 etiss_uint8 rd = 0;
1807 static BitArrayRange R_rd_0(11, 7);
1808 rd += R_rd_0.read(ba) << 0;
1809 etiss_uint8 rs1 = 0;
1810 static BitArrayRange R_rs1_0(19, 15);
1811 rs1 += R_rs1_0.read(ba) << 0;
1812 etiss_uint8 rs2 = 0;
1813 static BitArrayRange R_rs2_0(24, 20);
1814 rs2 += R_rs2_0.read(ba) << 0;
1815 
1816 // -----------------------------------------------------------------------------
1817 
1818  {
1819  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1820 
1821  cp.code() = std::string("//FEQ_S\n");
1822 
1823 // -----------------------------------------------------------------------------
1824 cp.code() += "etiss_coverage_count(1, 106);\n";
1825 { // block
1826 cp.code() += "etiss_coverage_count(1, 1169);\n";
1827 cp.code() += "{ // block\n";
1828 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1829 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1830 cp.code() += "} // block\n";
1831 } // block
1832 { // block
1833 cp.code() += "etiss_coverage_count(1, 4595);\n";
1834 cp.code() += "{ // block\n";
1835 cp.code() += "etiss_uint32 res = 0LL;\n";
1836 cp.code() += "etiss_coverage_count(2, 4532, 4531);\n";
1837 { // block
1838 cp.code() += "etiss_coverage_count(1, 4565);\n";
1839 cp.code() += "{ // block\n";
1840 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
1841 cp.code() += "etiss_coverage_count(4, 4552, 4551, 4550, 4549);\n";
1842 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
1843 cp.code() += "etiss_coverage_count(4, 4558, 4557, 4556, 4555);\n";
1844 cp.code() += "res = fcmp_s(frs1, frs2, 0LL);\n";
1845 cp.code() += "etiss_coverage_count(6, 4564, 4559, 4563, 4560, 4561, 4562);\n";
1846 cp.code() += "} // block\n";
1847 } // block
1848 cp.code() += "etiss_coverage_count(1, 4566);\n";
1849 if ((rd % 32ULL) != 0LL) { // conditional
1850 cp.code() += "etiss_coverage_count(5, 4572, 4569, 4567, 4570, 4571);\n";
1851 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
1852 cp.code() += "etiss_coverage_count(5, 4579, 4577, 4576, 4574, 4578);\n";
1853 } // conditional
1854 cp.code() += "etiss_uint32 flags = fget_flags();\n";
1855 cp.code() += "etiss_coverage_count(2, 4582, 4581);\n";
1856 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1857 cp.code() += "etiss_coverage_count(9, 4594, 4583, 4593, 4587, 4584, 4588, 4591, 4589, 4592);\n";
1858 cp.code() += "} // block\n";
1859 } // block
1860 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1861 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1862 // -----------------------------------------------------------------------------
1863  cp.getAffectedRegisters().add("instructionPointer", 32);
1864  }
1865 
1866  return true;
1867  },
1868  0,
1869  [] (BitArray & ba, Instruction & instr)
1870  {
1871 // -----------------------------------------------------------------------------
1872 etiss_uint8 rd = 0;
1873 static BitArrayRange R_rd_0(11, 7);
1874 rd += R_rd_0.read(ba) << 0;
1875 etiss_uint8 rs1 = 0;
1876 static BitArrayRange R_rs1_0(19, 15);
1877 rs1 += R_rs1_0.read(ba) << 0;
1878 etiss_uint8 rs2 = 0;
1879 static BitArrayRange R_rs2_0(24, 20);
1880 rs2 += R_rs2_0.read(ba) << 0;
1881 
1882 // -----------------------------------------------------------------------------
1883 
1884  std::stringstream ss;
1885 // -----------------------------------------------------------------------------
1886 ss << "feq_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1887 // -----------------------------------------------------------------------------
1888  return ss.str();
1889  }
1890 );
1891 
1892 // FLT_S -----------------------------------------------------------------------
1893 static InstructionDefinition flt_s_rd_rs1_rs2 (
1894  ISA32_RV32IMACFD,
1895  "flt_s",
1896  (uint32_t) 0xa0001053,
1897  (uint32_t) 0xfe00707f,
1898  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1899  {
1900 
1901 // -----------------------------------------------------------------------------
1902 
1903 // -----------------------------------------------------------------------------
1904 
1905 // -----------------------------------------------------------------------------
1906 etiss_uint8 rd = 0;
1907 static BitArrayRange R_rd_0(11, 7);
1908 rd += R_rd_0.read(ba) << 0;
1909 etiss_uint8 rs1 = 0;
1910 static BitArrayRange R_rs1_0(19, 15);
1911 rs1 += R_rs1_0.read(ba) << 0;
1912 etiss_uint8 rs2 = 0;
1913 static BitArrayRange R_rs2_0(24, 20);
1914 rs2 += R_rs2_0.read(ba) << 0;
1915 
1916 // -----------------------------------------------------------------------------
1917 
1918  {
1919  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1920 
1921  cp.code() = std::string("//FLT_S\n");
1922 
1923 // -----------------------------------------------------------------------------
1924 cp.code() += "etiss_coverage_count(1, 107);\n";
1925 { // block
1926 cp.code() += "etiss_coverage_count(1, 1169);\n";
1927 cp.code() += "{ // block\n";
1928 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
1929 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
1930 cp.code() += "} // block\n";
1931 } // block
1932 { // block
1933 cp.code() += "etiss_coverage_count(1, 4661);\n";
1934 cp.code() += "{ // block\n";
1935 cp.code() += "etiss_uint32 res = 0LL;\n";
1936 cp.code() += "etiss_coverage_count(2, 4598, 4597);\n";
1937 { // block
1938 cp.code() += "etiss_coverage_count(1, 4631);\n";
1939 cp.code() += "{ // block\n";
1940 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
1941 cp.code() += "etiss_coverage_count(4, 4618, 4617, 4616, 4615);\n";
1942 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
1943 cp.code() += "etiss_coverage_count(4, 4624, 4623, 4622, 4621);\n";
1944 cp.code() += "res = fcmp_s(frs1, frs2, 2ULL);\n";
1945 cp.code() += "etiss_coverage_count(6, 4630, 4625, 4629, 4626, 4627, 4628);\n";
1946 cp.code() += "} // block\n";
1947 } // block
1948 cp.code() += "etiss_coverage_count(1, 4632);\n";
1949 if ((rd % 32ULL) != 0LL) { // conditional
1950 cp.code() += "etiss_coverage_count(5, 4638, 4635, 4633, 4636, 4637);\n";
1951 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
1952 cp.code() += "etiss_coverage_count(5, 4645, 4643, 4642, 4640, 4644);\n";
1953 } // conditional
1954 cp.code() += "etiss_uint32 flags = fget_flags();\n";
1955 cp.code() += "etiss_coverage_count(2, 4648, 4647);\n";
1956 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1957 cp.code() += "etiss_coverage_count(9, 4660, 4649, 4659, 4653, 4650, 4654, 4657, 4655, 4658);\n";
1958 cp.code() += "} // block\n";
1959 } // block
1960 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1961 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1962 // -----------------------------------------------------------------------------
1963  cp.getAffectedRegisters().add("instructionPointer", 32);
1964  }
1965 
1966  return true;
1967  },
1968  0,
1969  [] (BitArray & ba, Instruction & instr)
1970  {
1971 // -----------------------------------------------------------------------------
1972 etiss_uint8 rd = 0;
1973 static BitArrayRange R_rd_0(11, 7);
1974 rd += R_rd_0.read(ba) << 0;
1975 etiss_uint8 rs1 = 0;
1976 static BitArrayRange R_rs1_0(19, 15);
1977 rs1 += R_rs1_0.read(ba) << 0;
1978 etiss_uint8 rs2 = 0;
1979 static BitArrayRange R_rs2_0(24, 20);
1980 rs2 += R_rs2_0.read(ba) << 0;
1981 
1982 // -----------------------------------------------------------------------------
1983 
1984  std::stringstream ss;
1985 // -----------------------------------------------------------------------------
1986 ss << "flt_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1987 // -----------------------------------------------------------------------------
1988  return ss.str();
1989  }
1990 );
1991 
1992 // FLE_S -----------------------------------------------------------------------
1993 static InstructionDefinition fle_s_rd_rs1_rs2 (
1994  ISA32_RV32IMACFD,
1995  "fle_s",
1996  (uint32_t) 0xa0000053,
1997  (uint32_t) 0xfe00707f,
1998  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1999  {
2000 
2001 // -----------------------------------------------------------------------------
2002 
2003 // -----------------------------------------------------------------------------
2004 
2005 // -----------------------------------------------------------------------------
2006 etiss_uint8 rd = 0;
2007 static BitArrayRange R_rd_0(11, 7);
2008 rd += R_rd_0.read(ba) << 0;
2009 etiss_uint8 rs1 = 0;
2010 static BitArrayRange R_rs1_0(19, 15);
2011 rs1 += R_rs1_0.read(ba) << 0;
2012 etiss_uint8 rs2 = 0;
2013 static BitArrayRange R_rs2_0(24, 20);
2014 rs2 += R_rs2_0.read(ba) << 0;
2015 
2016 // -----------------------------------------------------------------------------
2017 
2018  {
2019  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2020 
2021  cp.code() = std::string("//FLE_S\n");
2022 
2023 // -----------------------------------------------------------------------------
2024 cp.code() += "etiss_coverage_count(1, 108);\n";
2025 { // block
2026 cp.code() += "etiss_coverage_count(1, 1169);\n";
2027 cp.code() += "{ // block\n";
2028 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2029 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2030 cp.code() += "} // block\n";
2031 } // block
2032 { // block
2033 cp.code() += "etiss_coverage_count(1, 4727);\n";
2034 cp.code() += "{ // block\n";
2035 cp.code() += "etiss_uint32 res = 0LL;\n";
2036 cp.code() += "etiss_coverage_count(2, 4664, 4663);\n";
2037 { // block
2038 cp.code() += "etiss_coverage_count(1, 4697);\n";
2039 cp.code() += "{ // block\n";
2040 cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
2041 cp.code() += "etiss_coverage_count(4, 4684, 4683, 4682, 4681);\n";
2042 cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
2043 cp.code() += "etiss_coverage_count(4, 4690, 4689, 4688, 4687);\n";
2044 cp.code() += "res = fcmp_s(frs1, frs2, 1ULL);\n";
2045 cp.code() += "etiss_coverage_count(6, 4696, 4691, 4695, 4692, 4693, 4694);\n";
2046 cp.code() += "} // block\n";
2047 } // block
2048 cp.code() += "etiss_coverage_count(1, 4698);\n";
2049 if ((rd % 32ULL) != 0LL) { // conditional
2050 cp.code() += "etiss_coverage_count(5, 4704, 4701, 4699, 4702, 4703);\n";
2051 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
2052 cp.code() += "etiss_coverage_count(5, 4711, 4709, 4708, 4706, 4710);\n";
2053 } // conditional
2054 cp.code() += "etiss_uint32 flags = fget_flags();\n";
2055 cp.code() += "etiss_coverage_count(2, 4714, 4713);\n";
2056 cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
2057 cp.code() += "etiss_coverage_count(9, 4726, 4715, 4725, 4719, 4716, 4720, 4723, 4721, 4724);\n";
2058 cp.code() += "} // block\n";
2059 } // block
2060 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2061 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2062 // -----------------------------------------------------------------------------
2063  cp.getAffectedRegisters().add("instructionPointer", 32);
2064  }
2065 
2066  return true;
2067  },
2068  0,
2069  [] (BitArray & ba, Instruction & instr)
2070  {
2071 // -----------------------------------------------------------------------------
2072 etiss_uint8 rd = 0;
2073 static BitArrayRange R_rd_0(11, 7);
2074 rd += R_rd_0.read(ba) << 0;
2075 etiss_uint8 rs1 = 0;
2076 static BitArrayRange R_rs1_0(19, 15);
2077 rs1 += R_rs1_0.read(ba) << 0;
2078 etiss_uint8 rs2 = 0;
2079 static BitArrayRange R_rs2_0(24, 20);
2080 rs2 += R_rs2_0.read(ba) << 0;
2081 
2082 // -----------------------------------------------------------------------------
2083 
2084  std::stringstream ss;
2085 // -----------------------------------------------------------------------------
2086 ss << "fle_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
2087 // -----------------------------------------------------------------------------
2088  return ss.str();
2089  }
2090 );
2091 
2092 // FCLASS_S --------------------------------------------------------------------
2093 static InstructionDefinition fclass_s_rd_rs1 (
2094  ISA32_RV32IMACFD,
2095  "fclass_s",
2096  (uint32_t) 0xe0001053,
2097  (uint32_t) 0xfff0707f,
2098  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2099  {
2100 
2101 // -----------------------------------------------------------------------------
2102 
2103 // -----------------------------------------------------------------------------
2104 
2105 // -----------------------------------------------------------------------------
2106 etiss_uint8 rd = 0;
2107 static BitArrayRange R_rd_0(11, 7);
2108 rd += R_rd_0.read(ba) << 0;
2109 etiss_uint8 rs1 = 0;
2110 static BitArrayRange R_rs1_0(19, 15);
2111 rs1 += R_rs1_0.read(ba) << 0;
2112 
2113 // -----------------------------------------------------------------------------
2114 
2115  {
2116  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2117 
2118  cp.code() = std::string("//FCLASS_S\n");
2119 
2120 // -----------------------------------------------------------------------------
2121 cp.code() += "etiss_coverage_count(1, 109);\n";
2122 { // block
2123 cp.code() += "etiss_coverage_count(1, 1169);\n";
2124 cp.code() += "{ // block\n";
2125 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2126 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2127 cp.code() += "} // block\n";
2128 } // block
2129 { // block
2130 cp.code() += "etiss_coverage_count(1, 4762);\n";
2131 cp.code() += "{ // block\n";
2132 cp.code() += "etiss_uint32 res = 0LL;\n";
2133 cp.code() += "etiss_coverage_count(2, 4730, 4729);\n";
2134 cp.code() += "res = fclass_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]));\n";
2135 cp.code() += "etiss_coverage_count(6, 4747, 4741, 4746, 4745, 4744, 4743);\n";
2136 cp.code() += "etiss_coverage_count(1, 4748);\n";
2137 if ((rd % 32ULL) != 0LL) { // conditional
2138 cp.code() += "etiss_coverage_count(5, 4754, 4751, 4749, 4752, 4753);\n";
2139 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
2140 cp.code() += "etiss_coverage_count(5, 4761, 4759, 4758, 4756, 4760);\n";
2141 } // conditional
2142 cp.code() += "} // block\n";
2143 } // block
2144 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2145 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2146 // -----------------------------------------------------------------------------
2147  cp.getAffectedRegisters().add("instructionPointer", 32);
2148  }
2149 
2150  return true;
2151  },
2152  0,
2153  [] (BitArray & ba, Instruction & instr)
2154  {
2155 // -----------------------------------------------------------------------------
2156 etiss_uint8 rd = 0;
2157 static BitArrayRange R_rd_0(11, 7);
2158 rd += R_rd_0.read(ba) << 0;
2159 etiss_uint8 rs1 = 0;
2160 static BitArrayRange R_rs1_0(19, 15);
2161 rs1 += R_rs1_0.read(ba) << 0;
2162 
2163 // -----------------------------------------------------------------------------
2164 
2165  std::stringstream ss;
2166 // -----------------------------------------------------------------------------
2167 ss << "fclass_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + "]");
2168 // -----------------------------------------------------------------------------
2169  return ss.str();
2170  }
2171 );
2172 
2173 // FCVT_S_W --------------------------------------------------------------------
2174 static InstructionDefinition fcvt_s_w_rd_rm_rs1 (
2175  ISA32_RV32IMACFD,
2176  "fcvt_s_w",
2177  (uint32_t) 0xd0000053,
2178  (uint32_t) 0xfff0007f,
2179  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2180  {
2181 
2182 // -----------------------------------------------------------------------------
2183 
2184 // -----------------------------------------------------------------------------
2185 
2186 // -----------------------------------------------------------------------------
2187 etiss_uint8 rd = 0;
2188 static BitArrayRange R_rd_0(11, 7);
2189 rd += R_rd_0.read(ba) << 0;
2190 etiss_uint8 rm = 0;
2191 static BitArrayRange R_rm_0(14, 12);
2192 rm += R_rm_0.read(ba) << 0;
2193 etiss_uint8 rs1 = 0;
2194 static BitArrayRange R_rs1_0(19, 15);
2195 rs1 += R_rs1_0.read(ba) << 0;
2196 
2197 // -----------------------------------------------------------------------------
2198 
2199  {
2200  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2201 
2202  cp.code() = std::string("//FCVT_S_W\n");
2203 
2204 // -----------------------------------------------------------------------------
2205 cp.code() += "etiss_coverage_count(1, 110);\n";
2206 { // block
2207 cp.code() += "etiss_coverage_count(1, 1169);\n";
2208 cp.code() += "{ // block\n";
2209 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2210 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2211 cp.code() += "} // block\n";
2212 } // block
2213 { // block
2214 cp.code() += "etiss_coverage_count(1, 4807);\n";
2215 cp.code() += "{ // block\n";
2216 { // block
2217 cp.code() += "etiss_coverage_count(1, 4806);\n";
2218 cp.code() += "{ // block\n";
2219 cp.code() += "etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), 2ULL, " + std::to_string(rm) + "ULL);\n";
2220 cp.code() += "etiss_coverage_count(8, 4790, 4789, 4786, 4785, 4784, 4782, 4787, 4788);\n";
2221 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
2222 cp.code() += "etiss_coverage_count(6, 4805, 4793, 4792, 4804, 4803, 4801);\n";
2223 cp.code() += "} // block\n";
2224 } // block
2225 cp.code() += "} // block\n";
2226 } // block
2227 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2228 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2229 // -----------------------------------------------------------------------------
2230  cp.getAffectedRegisters().add("instructionPointer", 32);
2231  }
2232 
2233  return true;
2234  },
2235  0,
2236  [] (BitArray & ba, Instruction & instr)
2237  {
2238 // -----------------------------------------------------------------------------
2239 etiss_uint8 rd = 0;
2240 static BitArrayRange R_rd_0(11, 7);
2241 rd += R_rd_0.read(ba) << 0;
2242 etiss_uint8 rm = 0;
2243 static BitArrayRange R_rm_0(14, 12);
2244 rm += R_rm_0.read(ba) << 0;
2245 etiss_uint8 rs1 = 0;
2246 static BitArrayRange R_rs1_0(19, 15);
2247 rs1 += R_rs1_0.read(ba) << 0;
2248 
2249 // -----------------------------------------------------------------------------
2250 
2251  std::stringstream ss;
2252 // -----------------------------------------------------------------------------
2253 ss << "fcvt_s_w" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
2254 // -----------------------------------------------------------------------------
2255  return ss.str();
2256  }
2257 );
2258 
2259 // FCVT_S_WU -------------------------------------------------------------------
2260 static InstructionDefinition fcvt_s_wu_rd_rm_rs1 (
2261  ISA32_RV32IMACFD,
2262  "fcvt_s_wu",
2263  (uint32_t) 0xd0100053,
2264  (uint32_t) 0xfff0007f,
2265  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2266  {
2267 
2268 // -----------------------------------------------------------------------------
2269 
2270 // -----------------------------------------------------------------------------
2271 
2272 // -----------------------------------------------------------------------------
2273 etiss_uint8 rd = 0;
2274 static BitArrayRange R_rd_0(11, 7);
2275 rd += R_rd_0.read(ba) << 0;
2276 etiss_uint8 rm = 0;
2277 static BitArrayRange R_rm_0(14, 12);
2278 rm += R_rm_0.read(ba) << 0;
2279 etiss_uint8 rs1 = 0;
2280 static BitArrayRange R_rs1_0(19, 15);
2281 rs1 += R_rs1_0.read(ba) << 0;
2282 
2283 // -----------------------------------------------------------------------------
2284 
2285  {
2286  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2287 
2288  cp.code() = std::string("//FCVT_S_WU\n");
2289 
2290 // -----------------------------------------------------------------------------
2291 cp.code() += "etiss_coverage_count(1, 111);\n";
2292 { // block
2293 cp.code() += "etiss_coverage_count(1, 1169);\n";
2294 cp.code() += "{ // block\n";
2295 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2296 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2297 cp.code() += "} // block\n";
2298 } // block
2299 { // block
2300 cp.code() += "etiss_coverage_count(1, 4852);\n";
2301 cp.code() += "{ // block\n";
2302 { // block
2303 cp.code() += "etiss_coverage_count(1, 4851);\n";
2304 cp.code() += "{ // block\n";
2305 cp.code() += "etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), 3ULL, " + std::to_string(rm) + "ULL);\n";
2306 cp.code() += "etiss_coverage_count(8, 4835, 4834, 4831, 4830, 4829, 4827, 4832, 4833);\n";
2307 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
2308 cp.code() += "etiss_coverage_count(6, 4850, 4838, 4837, 4849, 4848, 4846);\n";
2309 cp.code() += "} // block\n";
2310 } // block
2311 cp.code() += "} // block\n";
2312 } // block
2313 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2314 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2315 // -----------------------------------------------------------------------------
2316  cp.getAffectedRegisters().add("instructionPointer", 32);
2317  }
2318 
2319  return true;
2320  },
2321  0,
2322  [] (BitArray & ba, Instruction & instr)
2323  {
2324 // -----------------------------------------------------------------------------
2325 etiss_uint8 rd = 0;
2326 static BitArrayRange R_rd_0(11, 7);
2327 rd += R_rd_0.read(ba) << 0;
2328 etiss_uint8 rm = 0;
2329 static BitArrayRange R_rm_0(14, 12);
2330 rm += R_rm_0.read(ba) << 0;
2331 etiss_uint8 rs1 = 0;
2332 static BitArrayRange R_rs1_0(19, 15);
2333 rs1 += R_rs1_0.read(ba) << 0;
2334 
2335 // -----------------------------------------------------------------------------
2336 
2337  std::stringstream ss;
2338 // -----------------------------------------------------------------------------
2339 ss << "fcvt_s_wu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
2340 // -----------------------------------------------------------------------------
2341  return ss.str();
2342  }
2343 );
2344 
2345 // FMV_X_W ---------------------------------------------------------------------
2346 static InstructionDefinition fmv_x_w_rd_rs1 (
2347  ISA32_RV32IMACFD,
2348  "fmv_x_w",
2349  (uint32_t) 0xe0000053,
2350  (uint32_t) 0xfff0707f,
2351  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2352  {
2353 
2354 // -----------------------------------------------------------------------------
2355 
2356 // -----------------------------------------------------------------------------
2357 
2358 // -----------------------------------------------------------------------------
2359 etiss_uint8 rd = 0;
2360 static BitArrayRange R_rd_0(11, 7);
2361 rd += R_rd_0.read(ba) << 0;
2362 etiss_uint8 rs1 = 0;
2363 static BitArrayRange R_rs1_0(19, 15);
2364 rs1 += R_rs1_0.read(ba) << 0;
2365 
2366 // -----------------------------------------------------------------------------
2367 
2368  {
2369  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2370 
2371  cp.code() = std::string("//FMV_X_W\n");
2372 
2373 // -----------------------------------------------------------------------------
2374 cp.code() += "etiss_coverage_count(1, 112);\n";
2375 { // block
2376 cp.code() += "etiss_coverage_count(1, 1169);\n";
2377 cp.code() += "{ // block\n";
2378 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2379 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2380 cp.code() += "} // block\n";
2381 } // block
2382 { // block
2383 cp.code() += "etiss_coverage_count(1, 4873);\n";
2384 cp.code() += "{ // block\n";
2385 cp.code() += "etiss_coverage_count(1, 4853);\n";
2386 if ((rd % 32ULL) != 0LL) { // conditional
2387 cp.code() += "etiss_coverage_count(5, 4859, 4856, 4854, 4857, 4858);\n";
2388 cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)((etiss_int32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]));\n";
2389 cp.code() += "etiss_coverage_count(8, 4872, 4864, 4863, 4861, 4871, 4869, 4867, 4866);\n";
2390 } // conditional
2391 cp.code() += "} // block\n";
2392 } // block
2393 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2394 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2395 // -----------------------------------------------------------------------------
2396  cp.getAffectedRegisters().add("instructionPointer", 32);
2397  }
2398 
2399  return true;
2400  },
2401  0,
2402  [] (BitArray & ba, Instruction & instr)
2403  {
2404 // -----------------------------------------------------------------------------
2405 etiss_uint8 rd = 0;
2406 static BitArrayRange R_rd_0(11, 7);
2407 rd += R_rd_0.read(ba) << 0;
2408 etiss_uint8 rs1 = 0;
2409 static BitArrayRange R_rs1_0(19, 15);
2410 rs1 += R_rs1_0.read(ba) << 0;
2411 
2412 // -----------------------------------------------------------------------------
2413 
2414  std::stringstream ss;
2415 // -----------------------------------------------------------------------------
2416 ss << "fmv_x_w" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + "]");
2417 // -----------------------------------------------------------------------------
2418  return ss.str();
2419  }
2420 );
2421 
2422 // FMV_W_X ---------------------------------------------------------------------
2423 static InstructionDefinition fmv_w_x_rd_rs1 (
2424  ISA32_RV32IMACFD,
2425  "fmv_w_x",
2426  (uint32_t) 0xf0000053,
2427  (uint32_t) 0xfff0707f,
2428  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2429  {
2430 
2431 // -----------------------------------------------------------------------------
2432 
2433 // -----------------------------------------------------------------------------
2434 
2435 // -----------------------------------------------------------------------------
2436 etiss_uint8 rd = 0;
2437 static BitArrayRange R_rd_0(11, 7);
2438 rd += R_rd_0.read(ba) << 0;
2439 etiss_uint8 rs1 = 0;
2440 static BitArrayRange R_rs1_0(19, 15);
2441 rs1 += R_rs1_0.read(ba) << 0;
2442 
2443 // -----------------------------------------------------------------------------
2444 
2445  {
2446  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2447 
2448  cp.code() = std::string("//FMV_W_X\n");
2449 
2450 // -----------------------------------------------------------------------------
2451 cp.code() += "etiss_coverage_count(1, 113);\n";
2452 { // block
2453 cp.code() += "etiss_coverage_count(1, 1169);\n";
2454 cp.code() += "{ // block\n";
2455 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 4) + "ULL;\n";
2456 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
2457 cp.code() += "} // block\n";
2458 } // block
2459 { // block
2460 cp.code() += "etiss_coverage_count(1, 4907);\n";
2461 cp.code() += "{ // block\n";
2462 { // block
2463 cp.code() += "etiss_coverage_count(1, 4906);\n";
2464 cp.code() += "{ // block\n";
2465 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]);\n";
2466 cp.code() += "etiss_coverage_count(8, 4905, 4889, 4888, 4904, 4903, 4901, 4900, 4898);\n";
2467 cp.code() += "} // block\n";
2468 } // block
2469 cp.code() += "} // block\n";
2470 } // block
2471 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2472 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2473 // -----------------------------------------------------------------------------
2474  cp.getAffectedRegisters().add("instructionPointer", 32);
2475  }
2476 
2477  return true;
2478  },
2479  0,
2480  [] (BitArray & ba, Instruction & instr)
2481  {
2482 // -----------------------------------------------------------------------------
2483 etiss_uint8 rd = 0;
2484 static BitArrayRange R_rd_0(11, 7);
2485 rd += R_rd_0.read(ba) << 0;
2486 etiss_uint8 rs1 = 0;
2487 static BitArrayRange R_rs1_0(19, 15);
2488 rs1 += R_rs1_0.read(ba) << 0;
2489 
2490 // -----------------------------------------------------------------------------
2491 
2492  std::stringstream ss;
2493 // -----------------------------------------------------------------------------
2494 ss << "fmv_w_x" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + "]");
2495 // -----------------------------------------------------------------------------
2496  return ss.str();
2497  }
2498 );
ISA32_RV32IMACFD
etiss::instr::InstructionGroup ISA32_RV32IMACFD("ISA32_RV32IMACFD", 32)
fsub_s_rd_rm_rs1_rs2
static InstructionDefinition fsub_s_rd_rm_rs1_rs2(ISA32_RV32IMACFD, "fsub_s",(uint32_t) 0x8000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSUB_S\n");cp.code()+="etiss_coverage_count(1, 95);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3909);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 3893);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 3864, 3863, 3862, 3861);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 3870, 3869, 3868, 3867);\n";cp.code()+="etiss_uint32 res = fsub_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(6, 3877, 3876, 3872, 3873, 3875, 3874);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 3892, 3880, 3879, 3891, 3890, 3888);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 3896, 3895);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 3908, 3897, 3907, 3901, 3898, 3902, 3905, 3903, 3906);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fsub_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
flw_rd_rs1_imm
static InstructionDefinition flw_rd_rs1_imm(ISA32_RV32IMACFD, "flw",(uint32_t) 0x002007,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FLW\n");cp.code()+="etiss_coverage_count(1, 88);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3450);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 offs = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 3417, 3416, 3412, 3411, 3409, 3415, 3413);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 3424, 3423, 3421, 3420);\n";{ cp.code()+="etiss_coverage_count(1, 3449);\n";cp.code()+="{ // block\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 3448, 3436, 3435, 3447, 3446, 3444);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//FLW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "flw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
fdiv_s_rd_rm_rs1_rs2
static InstructionDefinition fdiv_s_rd_rm_rs1_rs2(ISA32_RV32IMACFD, "fdiv_s",(uint32_t) 0x18000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FDIV_S\n");cp.code()+="etiss_coverage_count(1, 97);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4045);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 4029);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4000, 3999, 3998, 3997);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4006, 4005, 4004, 4003);\n";cp.code()+="etiss_uint32 res = fdiv_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(6, 4013, 4012, 4008, 4009, 4011, 4010);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 4028, 4016, 4015, 4027, 4026, 4024);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 4032, 4031);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 4044, 4033, 4043, 4037, 4034, 4038, 4041, 4039, 4042);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fdiv_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fmadd_s_rd_rm_rs1_rs2_rs3
static InstructionDefinition fmadd_s_rd_rm_rs1_rs2_rs3(ISA32_RV32IMACFD, "fmadd_s",(uint32_t) 0x000043,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMADD_S\n");cp.code()+="etiss_coverage_count(1, 90);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3542);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 3526);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs3)+"ULL]), 0LL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(14, 3510, 3509, 3497, 3496, 3495, 3501, 3500, 3499, 3505, 3504, 3503, 3506, 3508, 3507);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 3525, 3513, 3512, 3524, 3523, 3521);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 3529, 3528);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 3541, 3530, 3540, 3534, 3531, 3535, 3538, 3536, 3539);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;std::stringstream ss;ss<< "fmadd_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rs3="+std::to_string(rs3)+"]");return ss.str();})
fmv_w_x_rd_rs1
static InstructionDefinition fmv_w_x_rd_rs1(ISA32_RV32IMACFD, "fmv_w_x",(uint32_t) 0xf0000053,(uint32_t) 0xfff0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMV_W_X\n");cp.code()+="etiss_coverage_count(1, 113);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4907);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 4906);\n";cp.code()+="{ // block\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(8, 4905, 4889, 4888, 4904, 4903, 4901, 4900, 4898);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fmv_w_x"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fsgnj_s_rd_rs1_rs2
static InstructionDefinition fsgnj_s_rd_rs1_rs2(ISA32_RV32IMACFD, "fsgnj_s",(uint32_t) 0x20000053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSGNJ_S\n");cp.code()+="etiss_coverage_count(1, 99);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4162);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 4161);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4130, 4129, 4128, 4127);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4136, 4135, 4134, 4133);\n";cp.code()+="etiss_uint32 res = ((((((frs2) >> (31ULL)) & 1ULL)) << 31) | ((((frs1) >> (0LL)) & 2147483647ULL)));\n";cp.code()+="etiss_coverage_count(10, 4147, 4146, 4141, 4138, 4139, 4140, 4145, 4142, 4143, 4144);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 4160, 4150, 4149, 4159, 4158, 4156);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fsgnj_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fsw_imm_rs1_rs2
static InstructionDefinition fsw_imm_rs1_rs2(ISA32_RV32IMACFD, "fsw",(uint32_t) 0x002027,(uint32_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSW\n");cp.code()+="etiss_coverage_count(1, 89);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3471);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 offs = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) >>(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 3461, 3460, 3456, 3455, 3453, 3459, 3457);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(6, 3470, 3464, 3463, 3469, 3467, 3466);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//FSW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "fsw"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fnmadd_s_rd_rm_rs1_rs2_rs3
static InstructionDefinition fnmadd_s_rd_rm_rs1_rs2_rs3(ISA32_RV32IMACFD, "fnmadd_s",(uint32_t) 0x00004f,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FNMADD_S\n");cp.code()+="etiss_coverage_count(1, 92);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3693);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 3677);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 3640, 3639, 3638, 3637);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 3646, 3645, 3644, 3643);\n";cp.code()+="etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs3)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 3652, 3651, 3650, 3649);\n";cp.code()+="etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(8, 3661, 3660, 3654, 3655, 3656, 3657, 3659, 3658);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 3676, 3664, 3663, 3675, 3674, 3672);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 3680, 3679);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 3692, 3681, 3691, 3685, 3682, 3686, 3689, 3687, 3690);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;std::stringstream ss;ss<< "fnmadd_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rs3="+std::to_string(rs3)+"]");return ss.str();})
fmul_s_rd_rm_rs1_rs2
static InstructionDefinition fmul_s_rd_rm_rs1_rs2(ISA32_RV32IMACFD, "fmul_s",(uint32_t) 0x10000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMUL_S\n");cp.code()+="etiss_coverage_count(1, 96);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3977);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 3961);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 3932, 3931, 3930, 3929);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 3938, 3937, 3936, 3935);\n";cp.code()+="etiss_uint32 res = fmul_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(6, 3945, 3944, 3940, 3941, 3943, 3942);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 3960, 3948, 3947, 3959, 3958, 3956);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 3964, 3963);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 3976, 3965, 3975, 3969, 3966, 3970, 3973, 3971, 3974);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fmul_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fmv_x_w_rd_rs1
static InstructionDefinition fmv_x_w_rd_rs1(ISA32_RV32IMACFD, "fmv_x_w",(uint32_t) 0xe0000053,(uint32_t) 0xfff0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMV_X_W\n");cp.code()+="etiss_coverage_count(1, 112);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4873);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 4853);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 4859, 4856, 4854, 4857, 4858);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint32)((etiss_int32)(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]));\n";cp.code()+="etiss_coverage_count(8, 4872, 4864, 4863, 4861, 4871, 4869, 4867, 4866);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fmv_x_w"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fle_s_rd_rs1_rs2
static InstructionDefinition fle_s_rd_rs1_rs2(ISA32_RV32IMACFD, "fle_s",(uint32_t) 0xa0000053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FLE_S\n");cp.code()+="etiss_coverage_count(1, 108);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4727);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = 0LL;\n";cp.code()+="etiss_coverage_count(2, 4664, 4663);\n";{ cp.code()+="etiss_coverage_count(1, 4697);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4684, 4683, 4682, 4681);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4690, 4689, 4688, 4687);\n";cp.code()+="res = fcmp_s(frs1, frs2, 1ULL);\n";cp.code()+="etiss_coverage_count(6, 4696, 4691, 4695, 4692, 4693, 4694);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 4698);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 4704, 4701, 4699, 4702, 4703);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 4711, 4709, 4708, 4706, 4710);\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 4714, 4713);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 4726, 4715, 4725, 4719, 4716, 4720, 4723, 4721, 4724);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fle_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fmsub_s_rd_rm_rs1_rs2_rs3
static InstructionDefinition fmsub_s_rd_rm_rs1_rs2_rs3(ISA32_RV32IMACFD, "fmsub_s",(uint32_t) 0x000047,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMSUB_S\n");cp.code()+="etiss_coverage_count(1, 91);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3613);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 3597);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs3)+"ULL]), 1ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(14, 3581, 3580, 3568, 3567, 3566, 3572, 3571, 3570, 3576, 3575, 3574, 3577, 3579, 3578);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 3596, 3584, 3583, 3595, 3594, 3592);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 3600, 3599);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 3612, 3601, 3611, 3605, 3602, 3606, 3609, 3607, 3610);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;std::stringstream ss;ss<< "fmsub_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rs3="+std::to_string(rs3)+"]");return ss.str();})
fadd_s_rd_rm_rs1_rs2
static InstructionDefinition fadd_s_rd_rm_rs1_rs2(ISA32_RV32IMACFD, "fadd_s",(uint32_t) 0x000053,(uint32_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FADD_S\n");cp.code()+="etiss_coverage_count(1, 94);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3841);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 3825);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 3796, 3795, 3794, 3793);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 3802, 3801, 3800, 3799);\n";cp.code()+="etiss_uint32 res = fadd_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(6, 3809, 3808, 3804, 3805, 3807, 3806);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 3824, 3812, 3811, 3823, 3822, 3820);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 3828, 3827);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 3840, 3829, 3839, 3833, 3830, 3834, 3837, 3835, 3838);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fadd_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fnmsub_s_rd_rm_rs1_rs2_rs3
static InstructionDefinition fnmsub_s_rd_rm_rs1_rs2_rs3(ISA32_RV32IMACFD, "fnmsub_s",(uint32_t) 0x00004b,(uint32_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FNMSUB_S\n");cp.code()+="etiss_coverage_count(1, 93);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3773);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 3757);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 3720, 3719, 3718, 3717);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 3726, 3725, 3724, 3723);\n";cp.code()+="etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs3)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 3732, 3731, 3730, 3729);\n";cp.code()+="etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(8, 3741, 3740, 3734, 3735, 3736, 3737, 3739, 3738);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 3756, 3744, 3743, 3755, 3754, 3752);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 3760, 3759);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 3772, 3761, 3771, 3765, 3762, 3766, 3769, 3767, 3770);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;std::stringstream ss;ss<< "fnmsub_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rs3="+std::to_string(rs3)+"]");return ss.str();})
flt_s_rd_rs1_rs2
static InstructionDefinition flt_s_rd_rs1_rs2(ISA32_RV32IMACFD, "flt_s",(uint32_t) 0xa0001053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FLT_S\n");cp.code()+="etiss_coverage_count(1, 107);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4661);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = 0LL;\n";cp.code()+="etiss_coverage_count(2, 4598, 4597);\n";{ cp.code()+="etiss_coverage_count(1, 4631);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4618, 4617, 4616, 4615);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4624, 4623, 4622, 4621);\n";cp.code()+="res = fcmp_s(frs1, frs2, 2ULL);\n";cp.code()+="etiss_coverage_count(6, 4630, 4625, 4629, 4626, 4627, 4628);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 4632);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 4638, 4635, 4633, 4636, 4637);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 4645, 4643, 4642, 4640, 4644);\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 4648, 4647);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 4660, 4649, 4659, 4653, 4650, 4654, 4657, 4655, 4658);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "flt_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fcvt_w_s_rd_rm_rs1
static InstructionDefinition fcvt_w_s_rd_rm_rs1(ISA32_RV32IMACFD, "fcvt_w_s",(uint32_t) 0xc0000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_W_S\n");cp.code()+="etiss_coverage_count(1, 104);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4468);\n";cp.code()+="{ // block\n";cp.code()+="etiss_int32 res = 0LL;\n";cp.code()+="etiss_coverage_count(2, 4413, 4412);\n";{ cp.code()+="etiss_coverage_count(1, 4438);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4431, 4430, 4429, 4428);\n";cp.code()+="res = fcvt_s(frs1, 0LL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(6, 4437, 4432, 4436, 4433, 4434, 4435);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 4439);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 4445, 4442, 4440, 4443, 4444);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 4452, 4450, 4449, 4447, 4451);\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 4455, 4454);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 4467, 4456, 4466, 4460, 4457, 4461, 4464, 4462, 4465);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_w_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fmin_s_rd_rs1_rs2
static InstructionDefinition fmin_s_rd_rs1_rs2(ISA32_RV32IMACFD, "fmin_s",(uint32_t) 0x28000053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMIN_S\n");cp.code()+="etiss_coverage_count(1, 102);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4344);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 4328);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4300, 4299, 4298, 4297);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4306, 4305, 4304, 4303);\n";cp.code()+="etiss_uint32 res = fsel_s(frs1, frs2, 0LL);\n";cp.code()+="etiss_coverage_count(5, 4312, 4311, 4308, 4309, 4310);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 4327, 4315, 4314, 4326, 4325, 4323);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 4331, 4330);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 4343, 4332, 4342, 4336, 4333, 4337, 4340, 4338, 4341);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fmin_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fcvt_wu_s_rd_rm_rs1
static InstructionDefinition fcvt_wu_s_rd_rm_rs1(ISA32_RV32IMACFD, "fcvt_wu_s",(uint32_t) 0xc0100053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_WU_S\n");cp.code()+="etiss_coverage_count(1, 105);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4529);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = 0LL;\n";cp.code()+="etiss_coverage_count(2, 4471, 4470);\n";{ cp.code()+="etiss_coverage_count(1, 4496);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4489, 4488, 4487, 4486);\n";cp.code()+="res = fcvt_s(frs1, 1ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(6, 4495, 4490, 4494, 4491, 4492, 4493);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 4497);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 4503, 4500, 4498, 4501, 4502);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint32)((etiss_int32)(res));\n";cp.code()+="etiss_coverage_count(7, 4513, 4508, 4507, 4505, 4512, 4510, 4509);\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 4516, 4515);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 4528, 4517, 4527, 4521, 4518, 4522, 4525, 4523, 4526);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_wu_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fcvt_s_w_rd_rm_rs1
static InstructionDefinition fcvt_s_w_rd_rm_rs1(ISA32_RV32IMACFD, "fcvt_s_w",(uint32_t) 0xd0000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_S_W\n");cp.code()+="etiss_coverage_count(1, 110);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4807);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 4806);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]), 2ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(8, 4790, 4789, 4786, 4785, 4784, 4782, 4787, 4788);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 4805, 4793, 4792, 4804, 4803, 4801);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_s_w"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fsgnjn_s_rd_rs1_rs2
static InstructionDefinition fsgnjn_s_rd_rs1_rs2(ISA32_RV32IMACFD, "fsgnjn_s",(uint32_t) 0x20001053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSGNJN_S\n");cp.code()+="etiss_coverage_count(1, 100);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4223);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 4222);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4190, 4189, 4188, 4187);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4196, 4195, 4194, 4193);\n";cp.code()+="etiss_uint32 res = (((~((((frs2) >> (31ULL)) & 1ULL))) << 31) | ((((frs1) >> (0LL)) & 2147483647ULL)));\n";cp.code()+="etiss_coverage_count(11, 4208, 4207, 4202, 4201, 4198, 4199, 4200, 4206, 4203, 4204, 4205);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 4221, 4211, 4210, 4220, 4219, 4217);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fsgnjn_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fclass_s_rd_rs1
static InstructionDefinition fclass_s_rd_rs1(ISA32_RV32IMACFD, "fclass_s",(uint32_t) 0xe0001053,(uint32_t) 0xfff0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCLASS_S\n");cp.code()+="etiss_coverage_count(1, 109);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4762);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = 0LL;\n";cp.code()+="etiss_coverage_count(2, 4730, 4729);\n";cp.code()+="res = fclass_s(unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]));\n";cp.code()+="etiss_coverage_count(6, 4747, 4741, 4746, 4745, 4744, 4743);\n";cp.code()+="etiss_coverage_count(1, 4748);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 4754, 4751, 4749, 4752, 4753);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 4761, 4759, 4758, 4756, 4760);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fclass_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fsgnjx_s_rd_rs1_rs2
static InstructionDefinition fsgnjx_s_rd_rs1_rs2(ISA32_RV32IMACFD, "fsgnjx_s",(uint32_t) 0x20002053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSGNJX_S\n");cp.code()+="etiss_coverage_count(1, 101);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4278);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 4277);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4247, 4246, 4245, 4244);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4253, 4252, 4251, 4250);\n";cp.code()+="etiss_uint32 res = frs1 ^ (frs2 & 2147483648ULL);\n";cp.code()+="etiss_coverage_count(7, 4261, 4260, 4255, 4258, 4256, 4257, 4259);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 4276, 4264, 4263, 4275, 4274, 4272);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fsgnjx_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fsqrt_s_rd_rm_rs1
static InstructionDefinition fsqrt_s_rd_rm_rs1(ISA32_RV32IMACFD, "fsqrt_s",(uint32_t) 0x58000053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSQRT_S\n");cp.code()+="etiss_coverage_count(1, 98);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4103);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 4087);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4065, 4064, 4063, 4062);\n";cp.code()+="etiss_uint32 res = fsqrt_s(frs1, RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(5, 4071, 4070, 4067, 4069, 4068);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 4086, 4074, 4073, 4085, 4084, 4082);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 4090, 4089);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 4102, 4091, 4101, 4095, 4092, 4096, 4099, 4097, 4100);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fsqrt_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fmax_s_rd_rs1_rs2
static InstructionDefinition fmax_s_rd_rs1_rs2(ISA32_RV32IMACFD, "fmax_s",(uint32_t) 0x28001053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMAX_S\n");cp.code()+="etiss_coverage_count(1, 103);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4410);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 4394);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4366, 4365, 4364, 4363);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4372, 4371, 4370, 4369);\n";cp.code()+="etiss_uint32 res = fsel_s(frs1, frs2, 1ULL);\n";cp.code()+="etiss_coverage_count(5, 4378, 4377, 4374, 4375, 4376);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 4393, 4381, 4380, 4392, 4391, 4389);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 4397, 4396);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 4409, 4398, 4408, 4402, 4399, 4403, 4406, 4404, 4407);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fmax_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
feq_s_rd_rs1_rs2
static InstructionDefinition feq_s_rd_rs1_rs2(ISA32_RV32IMACFD, "feq_s",(uint32_t) 0xa0002053,(uint32_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FEQ_S\n");cp.code()+="etiss_coverage_count(1, 106);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4595);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = 0LL;\n";cp.code()+="etiss_coverage_count(2, 4532, 4531);\n";{ cp.code()+="etiss_coverage_count(1, 4565);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4552, 4551, 4550, 4549);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4558, 4557, 4556, 4555);\n";cp.code()+="res = fcmp_s(frs1, frs2, 0LL);\n";cp.code()+="etiss_coverage_count(6, 4564, 4559, 4563, 4560, 4561, 4562);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 4566);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 4572, 4569, 4567, 4570, 4571);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 4579, 4577, 4576, 4574, 4578);\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 4582, 4581);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 4594, 4583, 4593, 4587, 4584, 4588, 4591, 4589, 4592);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "feq_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fcvt_s_wu_rd_rm_rs1
static InstructionDefinition fcvt_s_wu_rd_rm_rs1(ISA32_RV32IMACFD, "fcvt_s_wu",(uint32_t) 0xd0100053,(uint32_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_S_WU\n");cp.code()+="etiss_coverage_count(1, 111);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+4)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4852);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 4851);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]), 3ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(8, 4835, 4834, 4831, 4830, 4829, 4827, 4832, 4833);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 4850, 4838, 4837, 4849, 4848, 4846);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_s_wu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
uint32_t
static __inline__ uint32_t
Definition: arm_cde.h:25
etiss_int16
int16_t etiss_int16
Definition: types.h:89
etiss_uint8
uint8_t etiss_uint8
Definition: types.h:87
etiss_uint16
uint16_t etiss_uint16
Definition: types.h:90
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:386
etiss::CodePart::APPENDEDRETURNINGREQUIRED
@ APPENDEDRETURNINGREQUIRED
Definition: CodePart.h:402
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition: Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition: Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
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