ETISS 0.11.2
ExtendableTranslatingInstructionSetSimulator(version0.11.2)
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RV32IMACFD_RV32FInstr.cpp
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1// clang-format off
9#include "RV32IMACFDArch.h"
10#include "RV32IMACFDFuncs.h"
11
12using namespace etiss;
13using namespace etiss::instr;
14
15// FLW -------------------------------------------------------------------------
16static InstructionDefinition flw_rd_rs1_imm (
17 ISA32_RV32IMACFD,
18 "flw",
19 (uint64_t) 0x002007,
20 (uint64_t) 0x00707f,
21 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22 {
23
24// -----------------------------------------------------------------------------
25
26// -----------------------------------------------------------------------------
27
28// -----------------------------------------------------------------------------
29// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
30etiss_uint8 rd = 0;
31static BitArrayRange R_rd_0(11, 7);
32rd += R_rd_0.read(ba) << 0;
33etiss_uint8 rs1 = 0;
34static BitArrayRange R_rs1_0(19, 15);
35rs1 += R_rs1_0.read(ba) << 0;
36etiss_uint16 imm = 0;
37static BitArrayRange R_imm_0(31, 20);
38imm += R_imm_0.read(ba) << 0;
39
40// NOLINTEND(clang-diagnostic-unused-but-set-variable)
41// -----------------------------------------------------------------------------
42
43 {
44 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
45
46 cp.code() = std::string("//FLW\n");
47
48// -----------------------------------------------------------------------------
49cp.code() += "etiss_coverage_count(1, 88);\n";
50{ // block
51cp.code() += "etiss_coverage_count(1, 1189);\n";
52cp.code() += "{ // block\n";
53cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
54cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
55cp.code() += "} // block\n";
56} // block
57{ // block
58cp.code() += "etiss_coverage_count(1, 3413);\n";
59cp.code() += "{ // block\n";
60cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
61cp.code() += "etiss_coverage_count(7, 3377, 3376, 3372, 3371, 3369, 3375, 3373);\n";
62cp.code() += "etiss_uint32 mem_val_0;\n";
63cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
64cp.code() += "if (cpu->exception) { // conditional\n";
65{ // procedure
66cp.code() += "{ // procedure\n";
67cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
68cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
69cp.code() += "} // procedure\n";
70} // procedure
71cp.code() += "} // conditional\n";
72cp.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
73cp.code() += "etiss_coverage_count(6, 3387, 3386, 3384, 3382, 3380, 3381);\n";
74{ // block
75cp.code() += "etiss_coverage_count(1, 3412);\n";
76cp.code() += "{ // block\n";
77cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
78cp.code() += "etiss_coverage_count(6, 3411, 3399, 3398, 3410, 3409, 3407);\n";
79cp.code() += "} // block\n";
80} // block
81cp.code() += "} // block\n";
82} // block
83cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
84cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
85// -----------------------------------------------------------------------------
86 cp.getAffectedRegisters().add("instructionPointer", 32);
87 }
88 {
89 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
90
91 cp.code() = std::string("//FLW\n");
92
93// -----------------------------------------------------------------------------
94cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
95// -----------------------------------------------------------------------------
96 }
97
98 return true;
99 },
100 0,
101 [] (BitArray & ba, Instruction & instr)
102 {
103// -----------------------------------------------------------------------------
104etiss_uint8 rd = 0;
105static BitArrayRange R_rd_0(11, 7);
106rd += R_rd_0.read(ba) << 0;
107etiss_uint8 rs1 = 0;
108static BitArrayRange R_rs1_0(19, 15);
109rs1 += R_rs1_0.read(ba) << 0;
110etiss_uint16 imm = 0;
111static BitArrayRange R_imm_0(31, 20);
112imm += R_imm_0.read(ba) << 0;
113
114// -----------------------------------------------------------------------------
115
116 std::stringstream ss;
117// -----------------------------------------------------------------------------
118ss << "flw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | imm=" + std::to_string(imm) + "]");
119// -----------------------------------------------------------------------------
120 return ss.str();
121 }
122);
123
124// FSW -------------------------------------------------------------------------
125static InstructionDefinition fsw_imm_rs1_rs2 (
126 ISA32_RV32IMACFD,
127 "fsw",
128 (uint64_t) 0x002027,
129 (uint64_t) 0x00707f,
130 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
131 {
132
133// -----------------------------------------------------------------------------
134
135// -----------------------------------------------------------------------------
136
137// -----------------------------------------------------------------------------
138// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
139etiss_uint16 imm = 0;
140static BitArrayRange R_imm_0(11, 7);
141imm += R_imm_0.read(ba) << 0;
142etiss_uint8 rs1 = 0;
143static BitArrayRange R_rs1_0(19, 15);
144rs1 += R_rs1_0.read(ba) << 0;
145etiss_uint8 rs2 = 0;
146static BitArrayRange R_rs2_0(24, 20);
147rs2 += R_rs2_0.read(ba) << 0;
148static BitArrayRange R_imm_5(31, 25);
149imm += R_imm_5.read(ba) << 5;
150
151// NOLINTEND(clang-diagnostic-unused-but-set-variable)
152// -----------------------------------------------------------------------------
153
154 {
155 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
156
157 cp.code() = std::string("//FSW\n");
158
159// -----------------------------------------------------------------------------
160cp.code() += "etiss_coverage_count(1, 89);\n";
161{ // block
162cp.code() += "etiss_coverage_count(1, 1189);\n";
163cp.code() += "{ // block\n";
164cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
165cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
166cp.code() += "} // block\n";
167} // block
168{ // block
169cp.code() += "etiss_coverage_count(1, 3437);\n";
170cp.code() += "{ // block\n";
171cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL] + " + std::to_string(((etiss_int16)(((etiss_int16)imm) << (4)) >> (4))) + "LL;\n";
172cp.code() += "etiss_coverage_count(7, 3424, 3423, 3419, 3418, 3416, 3422, 3420);\n";
173cp.code() += "etiss_uint32 mem_val_0;\n";
174cp.code() += "mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
175cp.code() += "etiss_coverage_count(8, 3436, 3430, 3428, 3426, 3427, 3435, 3433, 3432);\n";
176cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
177cp.code() += "if (cpu->exception) { // conditional\n";
178{ // procedure
179cp.code() += "{ // procedure\n";
180cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
181cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
182cp.code() += "} // procedure\n";
183} // procedure
184cp.code() += "} // conditional\n";
185cp.code() += "} // block\n";
186} // block
187cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
188cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
189// -----------------------------------------------------------------------------
190 cp.getAffectedRegisters().add("instructionPointer", 32);
191 }
192 {
193 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
194
195 cp.code() = std::string("//FSW\n");
196
197// -----------------------------------------------------------------------------
198cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
199// -----------------------------------------------------------------------------
200 }
201
202 return true;
203 },
204 0,
205 [] (BitArray & ba, Instruction & instr)
206 {
207// -----------------------------------------------------------------------------
208etiss_uint16 imm = 0;
209static BitArrayRange R_imm_0(11, 7);
210imm += R_imm_0.read(ba) << 0;
211etiss_uint8 rs1 = 0;
212static BitArrayRange R_rs1_0(19, 15);
213rs1 += R_rs1_0.read(ba) << 0;
214etiss_uint8 rs2 = 0;
215static BitArrayRange R_rs2_0(24, 20);
216rs2 += R_rs2_0.read(ba) << 0;
217static BitArrayRange R_imm_5(31, 25);
218imm += R_imm_5.read(ba) << 5;
219
220// -----------------------------------------------------------------------------
221
222 std::stringstream ss;
223// -----------------------------------------------------------------------------
224ss << "fsw" << " # " << ba << (" [imm=" + std::to_string(imm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
225// -----------------------------------------------------------------------------
226 return ss.str();
227 }
228);
229
230// FMADD_S ---------------------------------------------------------------------
231static InstructionDefinition fmadd_s_rd_rm_rs1_rs2_rs3 (
232 ISA32_RV32IMACFD,
233 "fmadd_s",
234 (uint64_t) 0x000043,
235 (uint64_t) 0x600007f,
236 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
237 {
238
239// -----------------------------------------------------------------------------
240
241// -----------------------------------------------------------------------------
242
243// -----------------------------------------------------------------------------
244// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
245etiss_uint8 rd = 0;
246static BitArrayRange R_rd_0(11, 7);
247rd += R_rd_0.read(ba) << 0;
248etiss_uint8 rm = 0;
249static BitArrayRange R_rm_0(14, 12);
250rm += R_rm_0.read(ba) << 0;
251etiss_uint8 rs1 = 0;
252static BitArrayRange R_rs1_0(19, 15);
253rs1 += R_rs1_0.read(ba) << 0;
254etiss_uint8 rs2 = 0;
255static BitArrayRange R_rs2_0(24, 20);
256rs2 += R_rs2_0.read(ba) << 0;
257etiss_uint8 rs3 = 0;
258static BitArrayRange R_rs3_0(31, 27);
259rs3 += R_rs3_0.read(ba) << 0;
260
261// NOLINTEND(clang-diagnostic-unused-but-set-variable)
262// -----------------------------------------------------------------------------
263
264 {
265 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
266
267 cp.code() = std::string("//FMADD_S\n");
268
269// -----------------------------------------------------------------------------
270cp.code() += "etiss_coverage_count(1, 90);\n";
271{ // block
272cp.code() += "etiss_coverage_count(1, 1189);\n";
273cp.code() += "{ // block\n";
274cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
275cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
276cp.code() += "} // block\n";
277} // block
278{ // block
279cp.code() += "etiss_coverage_count(1, 3508);\n";
280cp.code() += "{ // block\n";
281{ // block
282cp.code() += "etiss_coverage_count(1, 3492);\n";
283cp.code() += "{ // block\n";
284cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 0LL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
285cp.code() += "etiss_coverage_count(14, 3476, 3475, 3463, 3462, 3461, 3467, 3466, 3465, 3471, 3470, 3469, 3472, 3474, 3473);\n";
286cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
287cp.code() += "etiss_coverage_count(6, 3491, 3479, 3478, 3490, 3489, 3487);\n";
288cp.code() += "} // block\n";
289} // block
290cp.code() += "etiss_uint32 flags = fget_flags();\n";
291cp.code() += "etiss_coverage_count(2, 3495, 3494);\n";
292cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
293cp.code() += "etiss_coverage_count(9, 3507, 3496, 3506, 3500, 3497, 3501, 3504, 3502, 3505);\n";
294cp.code() += "} // block\n";
295} // block
296cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
297cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
298// -----------------------------------------------------------------------------
299 cp.getAffectedRegisters().add("instructionPointer", 32);
300 }
301
302 return true;
303 },
304 0,
305 [] (BitArray & ba, Instruction & instr)
306 {
307// -----------------------------------------------------------------------------
308etiss_uint8 rd = 0;
309static BitArrayRange R_rd_0(11, 7);
310rd += R_rd_0.read(ba) << 0;
311etiss_uint8 rm = 0;
312static BitArrayRange R_rm_0(14, 12);
313rm += R_rm_0.read(ba) << 0;
314etiss_uint8 rs1 = 0;
315static BitArrayRange R_rs1_0(19, 15);
316rs1 += R_rs1_0.read(ba) << 0;
317etiss_uint8 rs2 = 0;
318static BitArrayRange R_rs2_0(24, 20);
319rs2 += R_rs2_0.read(ba) << 0;
320etiss_uint8 rs3 = 0;
321static BitArrayRange R_rs3_0(31, 27);
322rs3 += R_rs3_0.read(ba) << 0;
323
324// -----------------------------------------------------------------------------
325
326 std::stringstream ss;
327// -----------------------------------------------------------------------------
328ss << "fmadd_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]");
329// -----------------------------------------------------------------------------
330 return ss.str();
331 }
332);
333
334// FMSUB_S ---------------------------------------------------------------------
335static InstructionDefinition fmsub_s_rd_rm_rs1_rs2_rs3 (
336 ISA32_RV32IMACFD,
337 "fmsub_s",
338 (uint64_t) 0x000047,
339 (uint64_t) 0x600007f,
340 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
341 {
342
343// -----------------------------------------------------------------------------
344
345// -----------------------------------------------------------------------------
346
347// -----------------------------------------------------------------------------
348// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
349etiss_uint8 rd = 0;
350static BitArrayRange R_rd_0(11, 7);
351rd += R_rd_0.read(ba) << 0;
352etiss_uint8 rm = 0;
353static BitArrayRange R_rm_0(14, 12);
354rm += R_rm_0.read(ba) << 0;
355etiss_uint8 rs1 = 0;
356static BitArrayRange R_rs1_0(19, 15);
357rs1 += R_rs1_0.read(ba) << 0;
358etiss_uint8 rs2 = 0;
359static BitArrayRange R_rs2_0(24, 20);
360rs2 += R_rs2_0.read(ba) << 0;
361etiss_uint8 rs3 = 0;
362static BitArrayRange R_rs3_0(31, 27);
363rs3 += R_rs3_0.read(ba) << 0;
364
365// NOLINTEND(clang-diagnostic-unused-but-set-variable)
366// -----------------------------------------------------------------------------
367
368 {
369 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
370
371 cp.code() = std::string("//FMSUB_S\n");
372
373// -----------------------------------------------------------------------------
374cp.code() += "etiss_coverage_count(1, 91);\n";
375{ // block
376cp.code() += "etiss_coverage_count(1, 1189);\n";
377cp.code() += "{ // block\n";
378cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
379cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
380cp.code() += "} // block\n";
381} // block
382{ // block
383cp.code() += "etiss_coverage_count(1, 3579);\n";
384cp.code() += "{ // block\n";
385{ // block
386cp.code() += "etiss_coverage_count(1, 3563);\n";
387cp.code() += "{ // block\n";
388cp.code() += "etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]), unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]), 1ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
389cp.code() += "etiss_coverage_count(14, 3547, 3546, 3534, 3533, 3532, 3538, 3537, 3536, 3542, 3541, 3540, 3543, 3545, 3544);\n";
390cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
391cp.code() += "etiss_coverage_count(6, 3562, 3550, 3549, 3561, 3560, 3558);\n";
392cp.code() += "} // block\n";
393} // block
394cp.code() += "etiss_uint32 flags = fget_flags();\n";
395cp.code() += "etiss_coverage_count(2, 3566, 3565);\n";
396cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
397cp.code() += "etiss_coverage_count(9, 3578, 3567, 3577, 3571, 3568, 3572, 3575, 3573, 3576);\n";
398cp.code() += "} // block\n";
399} // block
400cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
401cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
402// -----------------------------------------------------------------------------
403 cp.getAffectedRegisters().add("instructionPointer", 32);
404 }
405
406 return true;
407 },
408 0,
409 [] (BitArray & ba, Instruction & instr)
410 {
411// -----------------------------------------------------------------------------
412etiss_uint8 rd = 0;
413static BitArrayRange R_rd_0(11, 7);
414rd += R_rd_0.read(ba) << 0;
415etiss_uint8 rm = 0;
416static BitArrayRange R_rm_0(14, 12);
417rm += R_rm_0.read(ba) << 0;
418etiss_uint8 rs1 = 0;
419static BitArrayRange R_rs1_0(19, 15);
420rs1 += R_rs1_0.read(ba) << 0;
421etiss_uint8 rs2 = 0;
422static BitArrayRange R_rs2_0(24, 20);
423rs2 += R_rs2_0.read(ba) << 0;
424etiss_uint8 rs3 = 0;
425static BitArrayRange R_rs3_0(31, 27);
426rs3 += R_rs3_0.read(ba) << 0;
427
428// -----------------------------------------------------------------------------
429
430 std::stringstream ss;
431// -----------------------------------------------------------------------------
432ss << "fmsub_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]");
433// -----------------------------------------------------------------------------
434 return ss.str();
435 }
436);
437
438// FNMADD_S --------------------------------------------------------------------
439static InstructionDefinition fnmadd_s_rd_rm_rs1_rs2_rs3 (
440 ISA32_RV32IMACFD,
441 "fnmadd_s",
442 (uint64_t) 0x00004f,
443 (uint64_t) 0x600007f,
444 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
445 {
446
447// -----------------------------------------------------------------------------
448
449// -----------------------------------------------------------------------------
450
451// -----------------------------------------------------------------------------
452// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
453etiss_uint8 rd = 0;
454static BitArrayRange R_rd_0(11, 7);
455rd += R_rd_0.read(ba) << 0;
456etiss_uint8 rm = 0;
457static BitArrayRange R_rm_0(14, 12);
458rm += R_rm_0.read(ba) << 0;
459etiss_uint8 rs1 = 0;
460static BitArrayRange R_rs1_0(19, 15);
461rs1 += R_rs1_0.read(ba) << 0;
462etiss_uint8 rs2 = 0;
463static BitArrayRange R_rs2_0(24, 20);
464rs2 += R_rs2_0.read(ba) << 0;
465etiss_uint8 rs3 = 0;
466static BitArrayRange R_rs3_0(31, 27);
467rs3 += R_rs3_0.read(ba) << 0;
468
469// NOLINTEND(clang-diagnostic-unused-but-set-variable)
470// -----------------------------------------------------------------------------
471
472 {
473 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
474
475 cp.code() = std::string("//FNMADD_S\n");
476
477// -----------------------------------------------------------------------------
478cp.code() += "etiss_coverage_count(1, 92);\n";
479{ // block
480cp.code() += "etiss_coverage_count(1, 1189);\n";
481cp.code() += "{ // block\n";
482cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
483cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
484cp.code() += "} // block\n";
485} // block
486{ // block
487cp.code() += "etiss_coverage_count(1, 3659);\n";
488cp.code() += "{ // block\n";
489{ // block
490cp.code() += "etiss_coverage_count(1, 3643);\n";
491cp.code() += "{ // block\n";
492cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
493cp.code() += "etiss_coverage_count(4, 3606, 3605, 3604, 3603);\n";
494cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
495cp.code() += "etiss_coverage_count(4, 3612, 3611, 3610, 3609);\n";
496cp.code() += "etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]);\n";
497cp.code() += "etiss_coverage_count(4, 3618, 3617, 3616, 3615);\n";
498cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
499cp.code() += "etiss_coverage_count(8, 3627, 3626, 3620, 3621, 3622, 3623, 3625, 3624);\n";
500cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
501cp.code() += "etiss_coverage_count(6, 3642, 3630, 3629, 3641, 3640, 3638);\n";
502cp.code() += "} // block\n";
503} // block
504cp.code() += "etiss_uint32 flags = fget_flags();\n";
505cp.code() += "etiss_coverage_count(2, 3646, 3645);\n";
506cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
507cp.code() += "etiss_coverage_count(9, 3658, 3647, 3657, 3651, 3648, 3652, 3655, 3653, 3656);\n";
508cp.code() += "} // block\n";
509} // block
510cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
511cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
512// -----------------------------------------------------------------------------
513 cp.getAffectedRegisters().add("instructionPointer", 32);
514 }
515
516 return true;
517 },
518 0,
519 [] (BitArray & ba, Instruction & instr)
520 {
521// -----------------------------------------------------------------------------
522etiss_uint8 rd = 0;
523static BitArrayRange R_rd_0(11, 7);
524rd += R_rd_0.read(ba) << 0;
525etiss_uint8 rm = 0;
526static BitArrayRange R_rm_0(14, 12);
527rm += R_rm_0.read(ba) << 0;
528etiss_uint8 rs1 = 0;
529static BitArrayRange R_rs1_0(19, 15);
530rs1 += R_rs1_0.read(ba) << 0;
531etiss_uint8 rs2 = 0;
532static BitArrayRange R_rs2_0(24, 20);
533rs2 += R_rs2_0.read(ba) << 0;
534etiss_uint8 rs3 = 0;
535static BitArrayRange R_rs3_0(31, 27);
536rs3 += R_rs3_0.read(ba) << 0;
537
538// -----------------------------------------------------------------------------
539
540 std::stringstream ss;
541// -----------------------------------------------------------------------------
542ss << "fnmadd_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]");
543// -----------------------------------------------------------------------------
544 return ss.str();
545 }
546);
547
548// FNMSUB_S --------------------------------------------------------------------
549static InstructionDefinition fnmsub_s_rd_rm_rs1_rs2_rs3 (
550 ISA32_RV32IMACFD,
551 "fnmsub_s",
552 (uint64_t) 0x00004b,
553 (uint64_t) 0x600007f,
554 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
555 {
556
557// -----------------------------------------------------------------------------
558
559// -----------------------------------------------------------------------------
560
561// -----------------------------------------------------------------------------
562// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
563etiss_uint8 rd = 0;
564static BitArrayRange R_rd_0(11, 7);
565rd += R_rd_0.read(ba) << 0;
566etiss_uint8 rm = 0;
567static BitArrayRange R_rm_0(14, 12);
568rm += R_rm_0.read(ba) << 0;
569etiss_uint8 rs1 = 0;
570static BitArrayRange R_rs1_0(19, 15);
571rs1 += R_rs1_0.read(ba) << 0;
572etiss_uint8 rs2 = 0;
573static BitArrayRange R_rs2_0(24, 20);
574rs2 += R_rs2_0.read(ba) << 0;
575etiss_uint8 rs3 = 0;
576static BitArrayRange R_rs3_0(31, 27);
577rs3 += R_rs3_0.read(ba) << 0;
578
579// NOLINTEND(clang-diagnostic-unused-but-set-variable)
580// -----------------------------------------------------------------------------
581
582 {
583 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
584
585 cp.code() = std::string("//FNMSUB_S\n");
586
587// -----------------------------------------------------------------------------
588cp.code() += "etiss_coverage_count(1, 93);\n";
589{ // block
590cp.code() += "etiss_coverage_count(1, 1189);\n";
591cp.code() += "{ // block\n";
592cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
593cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
594cp.code() += "} // block\n";
595} // block
596{ // block
597cp.code() += "etiss_coverage_count(1, 3739);\n";
598cp.code() += "{ // block\n";
599{ // block
600cp.code() += "etiss_coverage_count(1, 3723);\n";
601cp.code() += "{ // block\n";
602cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
603cp.code() += "etiss_coverage_count(4, 3686, 3685, 3684, 3683);\n";
604cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
605cp.code() += "etiss_coverage_count(4, 3692, 3691, 3690, 3689);\n";
606cp.code() += "etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs3) + "ULL]);\n";
607cp.code() += "etiss_coverage_count(4, 3698, 3697, 3696, 3695);\n";
608cp.code() += "etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
609cp.code() += "etiss_coverage_count(8, 3707, 3706, 3700, 3701, 3702, 3703, 3705, 3704);\n";
610cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
611cp.code() += "etiss_coverage_count(6, 3722, 3710, 3709, 3721, 3720, 3718);\n";
612cp.code() += "} // block\n";
613} // block
614cp.code() += "etiss_uint32 flags = fget_flags();\n";
615cp.code() += "etiss_coverage_count(2, 3726, 3725);\n";
616cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
617cp.code() += "etiss_coverage_count(9, 3738, 3727, 3737, 3731, 3728, 3732, 3735, 3733, 3736);\n";
618cp.code() += "} // block\n";
619} // block
620cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
621cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
622// -----------------------------------------------------------------------------
623 cp.getAffectedRegisters().add("instructionPointer", 32);
624 }
625
626 return true;
627 },
628 0,
629 [] (BitArray & ba, Instruction & instr)
630 {
631// -----------------------------------------------------------------------------
632etiss_uint8 rd = 0;
633static BitArrayRange R_rd_0(11, 7);
634rd += R_rd_0.read(ba) << 0;
635etiss_uint8 rm = 0;
636static BitArrayRange R_rm_0(14, 12);
637rm += R_rm_0.read(ba) << 0;
638etiss_uint8 rs1 = 0;
639static BitArrayRange R_rs1_0(19, 15);
640rs1 += R_rs1_0.read(ba) << 0;
641etiss_uint8 rs2 = 0;
642static BitArrayRange R_rs2_0(24, 20);
643rs2 += R_rs2_0.read(ba) << 0;
644etiss_uint8 rs3 = 0;
645static BitArrayRange R_rs3_0(31, 27);
646rs3 += R_rs3_0.read(ba) << 0;
647
648// -----------------------------------------------------------------------------
649
650 std::stringstream ss;
651// -----------------------------------------------------------------------------
652ss << "fnmsub_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + " | rs3=" + std::to_string(rs3) + "]");
653// -----------------------------------------------------------------------------
654 return ss.str();
655 }
656);
657
658// FADD_S ----------------------------------------------------------------------
659static InstructionDefinition fadd_s_rd_rm_rs1_rs2 (
660 ISA32_RV32IMACFD,
661 "fadd_s",
662 (uint64_t) 0x000053,
663 (uint64_t) 0xfe00007f,
664 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
665 {
666
667// -----------------------------------------------------------------------------
668
669// -----------------------------------------------------------------------------
670
671// -----------------------------------------------------------------------------
672// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
673etiss_uint8 rd = 0;
674static BitArrayRange R_rd_0(11, 7);
675rd += R_rd_0.read(ba) << 0;
676etiss_uint8 rm = 0;
677static BitArrayRange R_rm_0(14, 12);
678rm += R_rm_0.read(ba) << 0;
679etiss_uint8 rs1 = 0;
680static BitArrayRange R_rs1_0(19, 15);
681rs1 += R_rs1_0.read(ba) << 0;
682etiss_uint8 rs2 = 0;
683static BitArrayRange R_rs2_0(24, 20);
684rs2 += R_rs2_0.read(ba) << 0;
685
686// NOLINTEND(clang-diagnostic-unused-but-set-variable)
687// -----------------------------------------------------------------------------
688
689 {
690 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
691
692 cp.code() = std::string("//FADD_S\n");
693
694// -----------------------------------------------------------------------------
695cp.code() += "etiss_coverage_count(1, 94);\n";
696{ // block
697cp.code() += "etiss_coverage_count(1, 1189);\n";
698cp.code() += "{ // block\n";
699cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
700cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
701cp.code() += "} // block\n";
702} // block
703{ // block
704cp.code() += "etiss_coverage_count(1, 3807);\n";
705cp.code() += "{ // block\n";
706{ // block
707cp.code() += "etiss_coverage_count(1, 3791);\n";
708cp.code() += "{ // block\n";
709cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
710cp.code() += "etiss_coverage_count(4, 3762, 3761, 3760, 3759);\n";
711cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
712cp.code() += "etiss_coverage_count(4, 3768, 3767, 3766, 3765);\n";
713cp.code() += "etiss_uint32 res = fadd_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
714cp.code() += "etiss_coverage_count(6, 3775, 3774, 3770, 3771, 3773, 3772);\n";
715cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
716cp.code() += "etiss_coverage_count(6, 3790, 3778, 3777, 3789, 3788, 3786);\n";
717cp.code() += "} // block\n";
718} // block
719cp.code() += "etiss_uint32 flags = fget_flags();\n";
720cp.code() += "etiss_coverage_count(2, 3794, 3793);\n";
721cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
722cp.code() += "etiss_coverage_count(9, 3806, 3795, 3805, 3799, 3796, 3800, 3803, 3801, 3804);\n";
723cp.code() += "} // block\n";
724} // block
725cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
726cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
727// -----------------------------------------------------------------------------
728 cp.getAffectedRegisters().add("instructionPointer", 32);
729 }
730
731 return true;
732 },
733 0,
734 [] (BitArray & ba, Instruction & instr)
735 {
736// -----------------------------------------------------------------------------
737etiss_uint8 rd = 0;
738static BitArrayRange R_rd_0(11, 7);
739rd += R_rd_0.read(ba) << 0;
740etiss_uint8 rm = 0;
741static BitArrayRange R_rm_0(14, 12);
742rm += R_rm_0.read(ba) << 0;
743etiss_uint8 rs1 = 0;
744static BitArrayRange R_rs1_0(19, 15);
745rs1 += R_rs1_0.read(ba) << 0;
746etiss_uint8 rs2 = 0;
747static BitArrayRange R_rs2_0(24, 20);
748rs2 += R_rs2_0.read(ba) << 0;
749
750// -----------------------------------------------------------------------------
751
752 std::stringstream ss;
753// -----------------------------------------------------------------------------
754ss << "fadd_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
755// -----------------------------------------------------------------------------
756 return ss.str();
757 }
758);
759
760// FSUB_S ----------------------------------------------------------------------
761static InstructionDefinition fsub_s_rd_rm_rs1_rs2 (
762 ISA32_RV32IMACFD,
763 "fsub_s",
764 (uint64_t) 0x8000053,
765 (uint64_t) 0xfe00007f,
766 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
767 {
768
769// -----------------------------------------------------------------------------
770
771// -----------------------------------------------------------------------------
772
773// -----------------------------------------------------------------------------
774// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
775etiss_uint8 rd = 0;
776static BitArrayRange R_rd_0(11, 7);
777rd += R_rd_0.read(ba) << 0;
778etiss_uint8 rm = 0;
779static BitArrayRange R_rm_0(14, 12);
780rm += R_rm_0.read(ba) << 0;
781etiss_uint8 rs1 = 0;
782static BitArrayRange R_rs1_0(19, 15);
783rs1 += R_rs1_0.read(ba) << 0;
784etiss_uint8 rs2 = 0;
785static BitArrayRange R_rs2_0(24, 20);
786rs2 += R_rs2_0.read(ba) << 0;
787
788// NOLINTEND(clang-diagnostic-unused-but-set-variable)
789// -----------------------------------------------------------------------------
790
791 {
792 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
793
794 cp.code() = std::string("//FSUB_S\n");
795
796// -----------------------------------------------------------------------------
797cp.code() += "etiss_coverage_count(1, 95);\n";
798{ // block
799cp.code() += "etiss_coverage_count(1, 1189);\n";
800cp.code() += "{ // block\n";
801cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
802cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
803cp.code() += "} // block\n";
804} // block
805{ // block
806cp.code() += "etiss_coverage_count(1, 3875);\n";
807cp.code() += "{ // block\n";
808{ // block
809cp.code() += "etiss_coverage_count(1, 3859);\n";
810cp.code() += "{ // block\n";
811cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
812cp.code() += "etiss_coverage_count(4, 3830, 3829, 3828, 3827);\n";
813cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
814cp.code() += "etiss_coverage_count(4, 3836, 3835, 3834, 3833);\n";
815cp.code() += "etiss_uint32 res = fsub_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
816cp.code() += "etiss_coverage_count(6, 3843, 3842, 3838, 3839, 3841, 3840);\n";
817cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
818cp.code() += "etiss_coverage_count(6, 3858, 3846, 3845, 3857, 3856, 3854);\n";
819cp.code() += "} // block\n";
820} // block
821cp.code() += "etiss_uint32 flags = fget_flags();\n";
822cp.code() += "etiss_coverage_count(2, 3862, 3861);\n";
823cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
824cp.code() += "etiss_coverage_count(9, 3874, 3863, 3873, 3867, 3864, 3868, 3871, 3869, 3872);\n";
825cp.code() += "} // block\n";
826} // block
827cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
828cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
829// -----------------------------------------------------------------------------
830 cp.getAffectedRegisters().add("instructionPointer", 32);
831 }
832
833 return true;
834 },
835 0,
836 [] (BitArray & ba, Instruction & instr)
837 {
838// -----------------------------------------------------------------------------
839etiss_uint8 rd = 0;
840static BitArrayRange R_rd_0(11, 7);
841rd += R_rd_0.read(ba) << 0;
842etiss_uint8 rm = 0;
843static BitArrayRange R_rm_0(14, 12);
844rm += R_rm_0.read(ba) << 0;
845etiss_uint8 rs1 = 0;
846static BitArrayRange R_rs1_0(19, 15);
847rs1 += R_rs1_0.read(ba) << 0;
848etiss_uint8 rs2 = 0;
849static BitArrayRange R_rs2_0(24, 20);
850rs2 += R_rs2_0.read(ba) << 0;
851
852// -----------------------------------------------------------------------------
853
854 std::stringstream ss;
855// -----------------------------------------------------------------------------
856ss << "fsub_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
857// -----------------------------------------------------------------------------
858 return ss.str();
859 }
860);
861
862// FMUL_S ----------------------------------------------------------------------
863static InstructionDefinition fmul_s_rd_rm_rs1_rs2 (
864 ISA32_RV32IMACFD,
865 "fmul_s",
866 (uint64_t) 0x10000053,
867 (uint64_t) 0xfe00007f,
868 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
869 {
870
871// -----------------------------------------------------------------------------
872
873// -----------------------------------------------------------------------------
874
875// -----------------------------------------------------------------------------
876// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
877etiss_uint8 rd = 0;
878static BitArrayRange R_rd_0(11, 7);
879rd += R_rd_0.read(ba) << 0;
880etiss_uint8 rm = 0;
881static BitArrayRange R_rm_0(14, 12);
882rm += R_rm_0.read(ba) << 0;
883etiss_uint8 rs1 = 0;
884static BitArrayRange R_rs1_0(19, 15);
885rs1 += R_rs1_0.read(ba) << 0;
886etiss_uint8 rs2 = 0;
887static BitArrayRange R_rs2_0(24, 20);
888rs2 += R_rs2_0.read(ba) << 0;
889
890// NOLINTEND(clang-diagnostic-unused-but-set-variable)
891// -----------------------------------------------------------------------------
892
893 {
894 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
895
896 cp.code() = std::string("//FMUL_S\n");
897
898// -----------------------------------------------------------------------------
899cp.code() += "etiss_coverage_count(1, 96);\n";
900{ // block
901cp.code() += "etiss_coverage_count(1, 1189);\n";
902cp.code() += "{ // block\n";
903cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
904cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
905cp.code() += "} // block\n";
906} // block
907{ // block
908cp.code() += "etiss_coverage_count(1, 3943);\n";
909cp.code() += "{ // block\n";
910{ // block
911cp.code() += "etiss_coverage_count(1, 3927);\n";
912cp.code() += "{ // block\n";
913cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
914cp.code() += "etiss_coverage_count(4, 3898, 3897, 3896, 3895);\n";
915cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
916cp.code() += "etiss_coverage_count(4, 3904, 3903, 3902, 3901);\n";
917cp.code() += "etiss_uint32 res = fmul_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
918cp.code() += "etiss_coverage_count(6, 3911, 3910, 3906, 3907, 3909, 3908);\n";
919cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
920cp.code() += "etiss_coverage_count(6, 3926, 3914, 3913, 3925, 3924, 3922);\n";
921cp.code() += "} // block\n";
922} // block
923cp.code() += "etiss_uint32 flags = fget_flags();\n";
924cp.code() += "etiss_coverage_count(2, 3930, 3929);\n";
925cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
926cp.code() += "etiss_coverage_count(9, 3942, 3931, 3941, 3935, 3932, 3936, 3939, 3937, 3940);\n";
927cp.code() += "} // block\n";
928} // block
929cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
930cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
931// -----------------------------------------------------------------------------
932 cp.getAffectedRegisters().add("instructionPointer", 32);
933 }
934
935 return true;
936 },
937 0,
938 [] (BitArray & ba, Instruction & instr)
939 {
940// -----------------------------------------------------------------------------
941etiss_uint8 rd = 0;
942static BitArrayRange R_rd_0(11, 7);
943rd += R_rd_0.read(ba) << 0;
944etiss_uint8 rm = 0;
945static BitArrayRange R_rm_0(14, 12);
946rm += R_rm_0.read(ba) << 0;
947etiss_uint8 rs1 = 0;
948static BitArrayRange R_rs1_0(19, 15);
949rs1 += R_rs1_0.read(ba) << 0;
950etiss_uint8 rs2 = 0;
951static BitArrayRange R_rs2_0(24, 20);
952rs2 += R_rs2_0.read(ba) << 0;
953
954// -----------------------------------------------------------------------------
955
956 std::stringstream ss;
957// -----------------------------------------------------------------------------
958ss << "fmul_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
959// -----------------------------------------------------------------------------
960 return ss.str();
961 }
962);
963
964// FDIV_S ----------------------------------------------------------------------
965static InstructionDefinition fdiv_s_rd_rm_rs1_rs2 (
966 ISA32_RV32IMACFD,
967 "fdiv_s",
968 (uint64_t) 0x18000053,
969 (uint64_t) 0xfe00007f,
970 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
971 {
972
973// -----------------------------------------------------------------------------
974
975// -----------------------------------------------------------------------------
976
977// -----------------------------------------------------------------------------
978// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
979etiss_uint8 rd = 0;
980static BitArrayRange R_rd_0(11, 7);
981rd += R_rd_0.read(ba) << 0;
982etiss_uint8 rm = 0;
983static BitArrayRange R_rm_0(14, 12);
984rm += R_rm_0.read(ba) << 0;
985etiss_uint8 rs1 = 0;
986static BitArrayRange R_rs1_0(19, 15);
987rs1 += R_rs1_0.read(ba) << 0;
988etiss_uint8 rs2 = 0;
989static BitArrayRange R_rs2_0(24, 20);
990rs2 += R_rs2_0.read(ba) << 0;
991
992// NOLINTEND(clang-diagnostic-unused-but-set-variable)
993// -----------------------------------------------------------------------------
994
995 {
996 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
997
998 cp.code() = std::string("//FDIV_S\n");
999
1000// -----------------------------------------------------------------------------
1001cp.code() += "etiss_coverage_count(1, 97);\n";
1002{ // block
1003cp.code() += "etiss_coverage_count(1, 1189);\n";
1004cp.code() += "{ // block\n";
1005cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
1006cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
1007cp.code() += "} // block\n";
1008} // block
1009{ // block
1010cp.code() += "etiss_coverage_count(1, 4011);\n";
1011cp.code() += "{ // block\n";
1012{ // block
1013cp.code() += "etiss_coverage_count(1, 3995);\n";
1014cp.code() += "{ // block\n";
1015cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
1016cp.code() += "etiss_coverage_count(4, 3966, 3965, 3964, 3963);\n";
1017cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
1018cp.code() += "etiss_coverage_count(4, 3972, 3971, 3970, 3969);\n";
1019cp.code() += "etiss_uint32 res = fdiv_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
1020cp.code() += "etiss_coverage_count(6, 3979, 3978, 3974, 3975, 3977, 3976);\n";
1021cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
1022cp.code() += "etiss_coverage_count(6, 3994, 3982, 3981, 3993, 3992, 3990);\n";
1023cp.code() += "} // block\n";
1024} // block
1025cp.code() += "etiss_uint32 flags = fget_flags();\n";
1026cp.code() += "etiss_coverage_count(2, 3998, 3997);\n";
1027cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1028cp.code() += "etiss_coverage_count(9, 4010, 3999, 4009, 4003, 4000, 4004, 4007, 4005, 4008);\n";
1029cp.code() += "} // block\n";
1030} // block
1031cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1032cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1033// -----------------------------------------------------------------------------
1034 cp.getAffectedRegisters().add("instructionPointer", 32);
1035 }
1036
1037 return true;
1038 },
1039 0,
1040 [] (BitArray & ba, Instruction & instr)
1041 {
1042// -----------------------------------------------------------------------------
1043etiss_uint8 rd = 0;
1044static BitArrayRange R_rd_0(11, 7);
1045rd += R_rd_0.read(ba) << 0;
1046etiss_uint8 rm = 0;
1047static BitArrayRange R_rm_0(14, 12);
1048rm += R_rm_0.read(ba) << 0;
1049etiss_uint8 rs1 = 0;
1050static BitArrayRange R_rs1_0(19, 15);
1051rs1 += R_rs1_0.read(ba) << 0;
1052etiss_uint8 rs2 = 0;
1053static BitArrayRange R_rs2_0(24, 20);
1054rs2 += R_rs2_0.read(ba) << 0;
1055
1056// -----------------------------------------------------------------------------
1057
1058 std::stringstream ss;
1059// -----------------------------------------------------------------------------
1060ss << "fdiv_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1061// -----------------------------------------------------------------------------
1062 return ss.str();
1063 }
1064);
1065
1066// FSQRT_S ---------------------------------------------------------------------
1067static InstructionDefinition fsqrt_s_rd_rm_rs1 (
1068 ISA32_RV32IMACFD,
1069 "fsqrt_s",
1070 (uint64_t) 0x58000053,
1071 (uint64_t) 0xfff0007f,
1072 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1073 {
1074
1075// -----------------------------------------------------------------------------
1076
1077// -----------------------------------------------------------------------------
1078
1079// -----------------------------------------------------------------------------
1080// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
1081etiss_uint8 rd = 0;
1082static BitArrayRange R_rd_0(11, 7);
1083rd += R_rd_0.read(ba) << 0;
1084etiss_uint8 rm = 0;
1085static BitArrayRange R_rm_0(14, 12);
1086rm += R_rm_0.read(ba) << 0;
1087etiss_uint8 rs1 = 0;
1088static BitArrayRange R_rs1_0(19, 15);
1089rs1 += R_rs1_0.read(ba) << 0;
1090
1091// NOLINTEND(clang-diagnostic-unused-but-set-variable)
1092// -----------------------------------------------------------------------------
1093
1094 {
1095 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1096
1097 cp.code() = std::string("//FSQRT_S\n");
1098
1099// -----------------------------------------------------------------------------
1100cp.code() += "etiss_coverage_count(1, 98);\n";
1101{ // block
1102cp.code() += "etiss_coverage_count(1, 1189);\n";
1103cp.code() += "{ // block\n";
1104cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
1105cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
1106cp.code() += "} // block\n";
1107} // block
1108{ // block
1109cp.code() += "etiss_coverage_count(1, 4069);\n";
1110cp.code() += "{ // block\n";
1111{ // block
1112cp.code() += "etiss_coverage_count(1, 4053);\n";
1113cp.code() += "{ // block\n";
1114cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
1115cp.code() += "etiss_coverage_count(4, 4031, 4030, 4029, 4028);\n";
1116cp.code() += "etiss_uint32 res = fsqrt_s(frs1, RV32IMACFD_get_rm(cpu, system, plugin_pointers, " + std::to_string(rm) + "ULL));\n";
1117cp.code() += "etiss_coverage_count(5, 4037, 4036, 4033, 4035, 4034);\n";
1118cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
1119cp.code() += "etiss_coverage_count(6, 4052, 4040, 4039, 4051, 4050, 4048);\n";
1120cp.code() += "} // block\n";
1121} // block
1122cp.code() += "etiss_uint32 flags = fget_flags();\n";
1123cp.code() += "etiss_coverage_count(2, 4056, 4055);\n";
1124cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1125cp.code() += "etiss_coverage_count(9, 4068, 4057, 4067, 4061, 4058, 4062, 4065, 4063, 4066);\n";
1126cp.code() += "} // block\n";
1127} // block
1128cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1129cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1130// -----------------------------------------------------------------------------
1131 cp.getAffectedRegisters().add("instructionPointer", 32);
1132 }
1133
1134 return true;
1135 },
1136 0,
1137 [] (BitArray & ba, Instruction & instr)
1138 {
1139// -----------------------------------------------------------------------------
1140etiss_uint8 rd = 0;
1141static BitArrayRange R_rd_0(11, 7);
1142rd += R_rd_0.read(ba) << 0;
1143etiss_uint8 rm = 0;
1144static BitArrayRange R_rm_0(14, 12);
1145rm += R_rm_0.read(ba) << 0;
1146etiss_uint8 rs1 = 0;
1147static BitArrayRange R_rs1_0(19, 15);
1148rs1 += R_rs1_0.read(ba) << 0;
1149
1150// -----------------------------------------------------------------------------
1151
1152 std::stringstream ss;
1153// -----------------------------------------------------------------------------
1154ss << "fsqrt_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
1155// -----------------------------------------------------------------------------
1156 return ss.str();
1157 }
1158);
1159
1160// FSGNJ_S ---------------------------------------------------------------------
1161static InstructionDefinition fsgnj_s_rd_rs1_rs2 (
1162 ISA32_RV32IMACFD,
1163 "fsgnj_s",
1164 (uint64_t) 0x20000053,
1165 (uint64_t) 0xfe00707f,
1166 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1167 {
1168
1169// -----------------------------------------------------------------------------
1170
1171// -----------------------------------------------------------------------------
1172
1173// -----------------------------------------------------------------------------
1174// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
1175etiss_uint8 rd = 0;
1176static BitArrayRange R_rd_0(11, 7);
1177rd += R_rd_0.read(ba) << 0;
1178etiss_uint8 rs1 = 0;
1179static BitArrayRange R_rs1_0(19, 15);
1180rs1 += R_rs1_0.read(ba) << 0;
1181etiss_uint8 rs2 = 0;
1182static BitArrayRange R_rs2_0(24, 20);
1183rs2 += R_rs2_0.read(ba) << 0;
1184
1185// NOLINTEND(clang-diagnostic-unused-but-set-variable)
1186// -----------------------------------------------------------------------------
1187
1188 {
1189 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1190
1191 cp.code() = std::string("//FSGNJ_S\n");
1192
1193// -----------------------------------------------------------------------------
1194cp.code() += "etiss_coverage_count(1, 99);\n";
1195{ // block
1196cp.code() += "etiss_coverage_count(1, 1189);\n";
1197cp.code() += "{ // block\n";
1198cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
1199cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
1200cp.code() += "} // block\n";
1201} // block
1202{ // block
1203cp.code() += "etiss_coverage_count(1, 4128);\n";
1204cp.code() += "{ // block\n";
1205{ // block
1206cp.code() += "etiss_coverage_count(1, 4127);\n";
1207cp.code() += "{ // block\n";
1208cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
1209cp.code() += "etiss_coverage_count(4, 4096, 4095, 4094, 4093);\n";
1210cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
1211cp.code() += "etiss_coverage_count(4, 4102, 4101, 4100, 4099);\n";
1212cp.code() += "etiss_uint32 res = ((((((frs2) >> (31ULL)) & 0x1ULL)) << 31) | (((frs1) & 0x7fffffffULL)));\n";
1213cp.code() += "etiss_coverage_count(10, 4113, 4112, 4107, 4104, 4105, 4106, 4111, 4108, 4109, 4110);\n";
1214cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
1215cp.code() += "etiss_coverage_count(6, 4126, 4116, 4115, 4125, 4124, 4122);\n";
1216cp.code() += "} // block\n";
1217} // block
1218cp.code() += "} // block\n";
1219} // block
1220cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1221cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1222// -----------------------------------------------------------------------------
1223 cp.getAffectedRegisters().add("instructionPointer", 32);
1224 }
1225
1226 return true;
1227 },
1228 0,
1229 [] (BitArray & ba, Instruction & instr)
1230 {
1231// -----------------------------------------------------------------------------
1232etiss_uint8 rd = 0;
1233static BitArrayRange R_rd_0(11, 7);
1234rd += R_rd_0.read(ba) << 0;
1235etiss_uint8 rs1 = 0;
1236static BitArrayRange R_rs1_0(19, 15);
1237rs1 += R_rs1_0.read(ba) << 0;
1238etiss_uint8 rs2 = 0;
1239static BitArrayRange R_rs2_0(24, 20);
1240rs2 += R_rs2_0.read(ba) << 0;
1241
1242// -----------------------------------------------------------------------------
1243
1244 std::stringstream ss;
1245// -----------------------------------------------------------------------------
1246ss << "fsgnj_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1247// -----------------------------------------------------------------------------
1248 return ss.str();
1249 }
1250);
1251
1252// FSGNJN_S --------------------------------------------------------------------
1253static InstructionDefinition fsgnjn_s_rd_rs1_rs2 (
1254 ISA32_RV32IMACFD,
1255 "fsgnjn_s",
1256 (uint64_t) 0x20001053,
1257 (uint64_t) 0xfe00707f,
1258 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1259 {
1260
1261// -----------------------------------------------------------------------------
1262
1263// -----------------------------------------------------------------------------
1264
1265// -----------------------------------------------------------------------------
1266// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
1267etiss_uint8 rd = 0;
1268static BitArrayRange R_rd_0(11, 7);
1269rd += R_rd_0.read(ba) << 0;
1270etiss_uint8 rs1 = 0;
1271static BitArrayRange R_rs1_0(19, 15);
1272rs1 += R_rs1_0.read(ba) << 0;
1273etiss_uint8 rs2 = 0;
1274static BitArrayRange R_rs2_0(24, 20);
1275rs2 += R_rs2_0.read(ba) << 0;
1276
1277// NOLINTEND(clang-diagnostic-unused-but-set-variable)
1278// -----------------------------------------------------------------------------
1279
1280 {
1281 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1282
1283 cp.code() = std::string("//FSGNJN_S\n");
1284
1285// -----------------------------------------------------------------------------
1286cp.code() += "etiss_coverage_count(1, 100);\n";
1287{ // block
1288cp.code() += "etiss_coverage_count(1, 1189);\n";
1289cp.code() += "{ // block\n";
1290cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
1291cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
1292cp.code() += "} // block\n";
1293} // block
1294{ // block
1295cp.code() += "etiss_coverage_count(1, 4189);\n";
1296cp.code() += "{ // block\n";
1297{ // block
1298cp.code() += "etiss_coverage_count(1, 4188);\n";
1299cp.code() += "{ // block\n";
1300cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
1301cp.code() += "etiss_coverage_count(4, 4156, 4155, 4154, 4153);\n";
1302cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
1303cp.code() += "etiss_coverage_count(4, 4162, 4161, 4160, 4159);\n";
1304cp.code() += "etiss_uint32 res = (((~((((frs2) >> (31ULL)) & 0x1ULL))) << 31) | (((frs1) & 0x7fffffffULL)));\n";
1305cp.code() += "etiss_coverage_count(11, 4174, 4173, 4168, 4167, 4164, 4165, 4166, 4172, 4169, 4170, 4171);\n";
1306cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
1307cp.code() += "etiss_coverage_count(6, 4187, 4177, 4176, 4186, 4185, 4183);\n";
1308cp.code() += "} // block\n";
1309} // block
1310cp.code() += "} // block\n";
1311} // block
1312cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1313cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1314// -----------------------------------------------------------------------------
1315 cp.getAffectedRegisters().add("instructionPointer", 32);
1316 }
1317
1318 return true;
1319 },
1320 0,
1321 [] (BitArray & ba, Instruction & instr)
1322 {
1323// -----------------------------------------------------------------------------
1324etiss_uint8 rd = 0;
1325static BitArrayRange R_rd_0(11, 7);
1326rd += R_rd_0.read(ba) << 0;
1327etiss_uint8 rs1 = 0;
1328static BitArrayRange R_rs1_0(19, 15);
1329rs1 += R_rs1_0.read(ba) << 0;
1330etiss_uint8 rs2 = 0;
1331static BitArrayRange R_rs2_0(24, 20);
1332rs2 += R_rs2_0.read(ba) << 0;
1333
1334// -----------------------------------------------------------------------------
1335
1336 std::stringstream ss;
1337// -----------------------------------------------------------------------------
1338ss << "fsgnjn_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1339// -----------------------------------------------------------------------------
1340 return ss.str();
1341 }
1342);
1343
1344// FSGNJX_S --------------------------------------------------------------------
1345static InstructionDefinition fsgnjx_s_rd_rs1_rs2 (
1346 ISA32_RV32IMACFD,
1347 "fsgnjx_s",
1348 (uint64_t) 0x20002053,
1349 (uint64_t) 0xfe00707f,
1350 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1351 {
1352
1353// -----------------------------------------------------------------------------
1354
1355// -----------------------------------------------------------------------------
1356
1357// -----------------------------------------------------------------------------
1358// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
1359etiss_uint8 rd = 0;
1360static BitArrayRange R_rd_0(11, 7);
1361rd += R_rd_0.read(ba) << 0;
1362etiss_uint8 rs1 = 0;
1363static BitArrayRange R_rs1_0(19, 15);
1364rs1 += R_rs1_0.read(ba) << 0;
1365etiss_uint8 rs2 = 0;
1366static BitArrayRange R_rs2_0(24, 20);
1367rs2 += R_rs2_0.read(ba) << 0;
1368
1369// NOLINTEND(clang-diagnostic-unused-but-set-variable)
1370// -----------------------------------------------------------------------------
1371
1372 {
1373 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1374
1375 cp.code() = std::string("//FSGNJX_S\n");
1376
1377// -----------------------------------------------------------------------------
1378cp.code() += "etiss_coverage_count(1, 101);\n";
1379{ // block
1380cp.code() += "etiss_coverage_count(1, 1189);\n";
1381cp.code() += "{ // block\n";
1382cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
1383cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
1384cp.code() += "} // block\n";
1385} // block
1386{ // block
1387cp.code() += "etiss_coverage_count(1, 4244);\n";
1388cp.code() += "{ // block\n";
1389{ // block
1390cp.code() += "etiss_coverage_count(1, 4243);\n";
1391cp.code() += "{ // block\n";
1392cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
1393cp.code() += "etiss_coverage_count(4, 4213, 4212, 4211, 4210);\n";
1394cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
1395cp.code() += "etiss_coverage_count(4, 4219, 4218, 4217, 4216);\n";
1396cp.code() += "etiss_uint32 res = frs1 ^ (frs2 & 2147483648ULL);\n";
1397cp.code() += "etiss_coverage_count(7, 4227, 4226, 4221, 4224, 4222, 4223, 4225);\n";
1398cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
1399cp.code() += "etiss_coverage_count(6, 4242, 4230, 4229, 4241, 4240, 4238);\n";
1400cp.code() += "} // block\n";
1401} // block
1402cp.code() += "} // block\n";
1403} // block
1404cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1405cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1406// -----------------------------------------------------------------------------
1407 cp.getAffectedRegisters().add("instructionPointer", 32);
1408 }
1409
1410 return true;
1411 },
1412 0,
1413 [] (BitArray & ba, Instruction & instr)
1414 {
1415// -----------------------------------------------------------------------------
1416etiss_uint8 rd = 0;
1417static BitArrayRange R_rd_0(11, 7);
1418rd += R_rd_0.read(ba) << 0;
1419etiss_uint8 rs1 = 0;
1420static BitArrayRange R_rs1_0(19, 15);
1421rs1 += R_rs1_0.read(ba) << 0;
1422etiss_uint8 rs2 = 0;
1423static BitArrayRange R_rs2_0(24, 20);
1424rs2 += R_rs2_0.read(ba) << 0;
1425
1426// -----------------------------------------------------------------------------
1427
1428 std::stringstream ss;
1429// -----------------------------------------------------------------------------
1430ss << "fsgnjx_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1431// -----------------------------------------------------------------------------
1432 return ss.str();
1433 }
1434);
1435
1436// FMIN_S ----------------------------------------------------------------------
1437static InstructionDefinition fmin_s_rd_rs1_rs2 (
1438 ISA32_RV32IMACFD,
1439 "fmin_s",
1440 (uint64_t) 0x28000053,
1441 (uint64_t) 0xfe00707f,
1442 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1443 {
1444
1445// -----------------------------------------------------------------------------
1446
1447// -----------------------------------------------------------------------------
1448
1449// -----------------------------------------------------------------------------
1450// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
1451etiss_uint8 rd = 0;
1452static BitArrayRange R_rd_0(11, 7);
1453rd += R_rd_0.read(ba) << 0;
1454etiss_uint8 rs1 = 0;
1455static BitArrayRange R_rs1_0(19, 15);
1456rs1 += R_rs1_0.read(ba) << 0;
1457etiss_uint8 rs2 = 0;
1458static BitArrayRange R_rs2_0(24, 20);
1459rs2 += R_rs2_0.read(ba) << 0;
1460
1461// NOLINTEND(clang-diagnostic-unused-but-set-variable)
1462// -----------------------------------------------------------------------------
1463
1464 {
1465 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1466
1467 cp.code() = std::string("//FMIN_S\n");
1468
1469// -----------------------------------------------------------------------------
1470cp.code() += "etiss_coverage_count(1, 102);\n";
1471{ // block
1472cp.code() += "etiss_coverage_count(1, 1189);\n";
1473cp.code() += "{ // block\n";
1474cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
1475cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
1476cp.code() += "} // block\n";
1477} // block
1478{ // block
1479cp.code() += "etiss_coverage_count(1, 4310);\n";
1480cp.code() += "{ // block\n";
1481{ // block
1482cp.code() += "etiss_coverage_count(1, 4294);\n";
1483cp.code() += "{ // block\n";
1484cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
1485cp.code() += "etiss_coverage_count(4, 4266, 4265, 4264, 4263);\n";
1486cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
1487cp.code() += "etiss_coverage_count(4, 4272, 4271, 4270, 4269);\n";
1488cp.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 0LL);\n";
1489cp.code() += "etiss_coverage_count(5, 4278, 4277, 4274, 4275, 4276);\n";
1490cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
1491cp.code() += "etiss_coverage_count(6, 4293, 4281, 4280, 4292, 4291, 4289);\n";
1492cp.code() += "} // block\n";
1493} // block
1494cp.code() += "etiss_uint32 flags = fget_flags();\n";
1495cp.code() += "etiss_coverage_count(2, 4297, 4296);\n";
1496cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1497cp.code() += "etiss_coverage_count(9, 4309, 4298, 4308, 4302, 4299, 4303, 4306, 4304, 4307);\n";
1498cp.code() += "} // block\n";
1499} // block
1500cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1501cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1502// -----------------------------------------------------------------------------
1503 cp.getAffectedRegisters().add("instructionPointer", 32);
1504 }
1505
1506 return true;
1507 },
1508 0,
1509 [] (BitArray & ba, Instruction & instr)
1510 {
1511// -----------------------------------------------------------------------------
1512etiss_uint8 rd = 0;
1513static BitArrayRange R_rd_0(11, 7);
1514rd += R_rd_0.read(ba) << 0;
1515etiss_uint8 rs1 = 0;
1516static BitArrayRange R_rs1_0(19, 15);
1517rs1 += R_rs1_0.read(ba) << 0;
1518etiss_uint8 rs2 = 0;
1519static BitArrayRange R_rs2_0(24, 20);
1520rs2 += R_rs2_0.read(ba) << 0;
1521
1522// -----------------------------------------------------------------------------
1523
1524 std::stringstream ss;
1525// -----------------------------------------------------------------------------
1526ss << "fmin_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1527// -----------------------------------------------------------------------------
1528 return ss.str();
1529 }
1530);
1531
1532// FMAX_S ----------------------------------------------------------------------
1533static InstructionDefinition fmax_s_rd_rs1_rs2 (
1534 ISA32_RV32IMACFD,
1535 "fmax_s",
1536 (uint64_t) 0x28001053,
1537 (uint64_t) 0xfe00707f,
1538 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1539 {
1540
1541// -----------------------------------------------------------------------------
1542
1543// -----------------------------------------------------------------------------
1544
1545// -----------------------------------------------------------------------------
1546// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
1547etiss_uint8 rd = 0;
1548static BitArrayRange R_rd_0(11, 7);
1549rd += R_rd_0.read(ba) << 0;
1550etiss_uint8 rs1 = 0;
1551static BitArrayRange R_rs1_0(19, 15);
1552rs1 += R_rs1_0.read(ba) << 0;
1553etiss_uint8 rs2 = 0;
1554static BitArrayRange R_rs2_0(24, 20);
1555rs2 += R_rs2_0.read(ba) << 0;
1556
1557// NOLINTEND(clang-diagnostic-unused-but-set-variable)
1558// -----------------------------------------------------------------------------
1559
1560 {
1561 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1562
1563 cp.code() = std::string("//FMAX_S\n");
1564
1565// -----------------------------------------------------------------------------
1566cp.code() += "etiss_coverage_count(1, 103);\n";
1567{ // block
1568cp.code() += "etiss_coverage_count(1, 1189);\n";
1569cp.code() += "{ // block\n";
1570cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
1571cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
1572cp.code() += "} // block\n";
1573} // block
1574{ // block
1575cp.code() += "etiss_coverage_count(1, 4376);\n";
1576cp.code() += "{ // block\n";
1577{ // block
1578cp.code() += "etiss_coverage_count(1, 4360);\n";
1579cp.code() += "{ // block\n";
1580cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
1581cp.code() += "etiss_coverage_count(4, 4332, 4331, 4330, 4329);\n";
1582cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
1583cp.code() += "etiss_coverage_count(4, 4338, 4337, 4336, 4335);\n";
1584cp.code() += "etiss_uint32 res = fsel_s(frs1, frs2, 1ULL);\n";
1585cp.code() += "etiss_coverage_count(5, 4344, 4343, 4340, 4341, 4342);\n";
1586cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
1587cp.code() += "etiss_coverage_count(6, 4359, 4347, 4346, 4358, 4357, 4355);\n";
1588cp.code() += "} // block\n";
1589} // block
1590cp.code() += "etiss_uint32 flags = fget_flags();\n";
1591cp.code() += "etiss_coverage_count(2, 4363, 4362);\n";
1592cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1593cp.code() += "etiss_coverage_count(9, 4375, 4364, 4374, 4368, 4365, 4369, 4372, 4370, 4373);\n";
1594cp.code() += "} // block\n";
1595} // block
1596cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1597cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1598// -----------------------------------------------------------------------------
1599 cp.getAffectedRegisters().add("instructionPointer", 32);
1600 }
1601
1602 return true;
1603 },
1604 0,
1605 [] (BitArray & ba, Instruction & instr)
1606 {
1607// -----------------------------------------------------------------------------
1608etiss_uint8 rd = 0;
1609static BitArrayRange R_rd_0(11, 7);
1610rd += R_rd_0.read(ba) << 0;
1611etiss_uint8 rs1 = 0;
1612static BitArrayRange R_rs1_0(19, 15);
1613rs1 += R_rs1_0.read(ba) << 0;
1614etiss_uint8 rs2 = 0;
1615static BitArrayRange R_rs2_0(24, 20);
1616rs2 += R_rs2_0.read(ba) << 0;
1617
1618// -----------------------------------------------------------------------------
1619
1620 std::stringstream ss;
1621// -----------------------------------------------------------------------------
1622ss << "fmax_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1623// -----------------------------------------------------------------------------
1624 return ss.str();
1625 }
1626);
1627
1628// FCVT_W_S --------------------------------------------------------------------
1629static InstructionDefinition fcvt_w_s_rd_rm_rs1 (
1630 ISA32_RV32IMACFD,
1631 "fcvt_w_s",
1632 (uint64_t) 0xc0000053,
1633 (uint64_t) 0xfff0007f,
1634 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1635 {
1636
1637// -----------------------------------------------------------------------------
1638
1639// -----------------------------------------------------------------------------
1640
1641// -----------------------------------------------------------------------------
1642// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
1643etiss_uint8 rd = 0;
1644static BitArrayRange R_rd_0(11, 7);
1645rd += R_rd_0.read(ba) << 0;
1646etiss_uint8 rm = 0;
1647static BitArrayRange R_rm_0(14, 12);
1648rm += R_rm_0.read(ba) << 0;
1649etiss_uint8 rs1 = 0;
1650static BitArrayRange R_rs1_0(19, 15);
1651rs1 += R_rs1_0.read(ba) << 0;
1652
1653// NOLINTEND(clang-diagnostic-unused-but-set-variable)
1654// -----------------------------------------------------------------------------
1655
1656 {
1657 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1658
1659 cp.code() = std::string("//FCVT_W_S\n");
1660
1661// -----------------------------------------------------------------------------
1662cp.code() += "etiss_coverage_count(1, 104);\n";
1663{ // block
1664cp.code() += "etiss_coverage_count(1, 1189);\n";
1665cp.code() += "{ // block\n";
1666cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
1667cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
1668cp.code() += "} // block\n";
1669} // block
1670{ // block
1671cp.code() += "etiss_coverage_count(1, 4434);\n";
1672cp.code() += "{ // block\n";
1673cp.code() += "etiss_int32 res = 0LL;\n";
1674cp.code() += "etiss_coverage_count(2, 4379, 4378);\n";
1675{ // block
1676cp.code() += "etiss_coverage_count(1, 4404);\n";
1677cp.code() += "{ // block\n";
1678cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
1679cp.code() += "etiss_coverage_count(4, 4397, 4396, 4395, 4394);\n";
1680cp.code() += "res = fcvt_s(frs1, 0LL, " + std::to_string(rm) + "ULL);\n";
1681cp.code() += "etiss_coverage_count(6, 4403, 4398, 4402, 4399, 4400, 4401);\n";
1682cp.code() += "} // block\n";
1683} // block
1684cp.code() += "etiss_coverage_count(1, 4405);\n";
1685if ((rd % 32ULL) != 0LL) { // conditional
1686cp.code() += "etiss_coverage_count(5, 4411, 4408, 4406, 4409, 4410);\n";
1687cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
1688cp.code() += "etiss_coverage_count(5, 4418, 4416, 4415, 4413, 4417);\n";
1689} // conditional
1690cp.code() += "etiss_uint32 flags = fget_flags();\n";
1691cp.code() += "etiss_coverage_count(2, 4421, 4420);\n";
1692cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1693cp.code() += "etiss_coverage_count(9, 4433, 4422, 4432, 4426, 4423, 4427, 4430, 4428, 4431);\n";
1694cp.code() += "} // block\n";
1695} // block
1696cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1697cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1698// -----------------------------------------------------------------------------
1699 cp.getAffectedRegisters().add("instructionPointer", 32);
1700 }
1701
1702 return true;
1703 },
1704 0,
1705 [] (BitArray & ba, Instruction & instr)
1706 {
1707// -----------------------------------------------------------------------------
1708etiss_uint8 rd = 0;
1709static BitArrayRange R_rd_0(11, 7);
1710rd += R_rd_0.read(ba) << 0;
1711etiss_uint8 rm = 0;
1712static BitArrayRange R_rm_0(14, 12);
1713rm += R_rm_0.read(ba) << 0;
1714etiss_uint8 rs1 = 0;
1715static BitArrayRange R_rs1_0(19, 15);
1716rs1 += R_rs1_0.read(ba) << 0;
1717
1718// -----------------------------------------------------------------------------
1719
1720 std::stringstream ss;
1721// -----------------------------------------------------------------------------
1722ss << "fcvt_w_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
1723// -----------------------------------------------------------------------------
1724 return ss.str();
1725 }
1726);
1727
1728// FCVT_WU_S -------------------------------------------------------------------
1729static InstructionDefinition fcvt_wu_s_rd_rm_rs1 (
1730 ISA32_RV32IMACFD,
1731 "fcvt_wu_s",
1732 (uint64_t) 0xc0100053,
1733 (uint64_t) 0xfff0007f,
1734 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1735 {
1736
1737// -----------------------------------------------------------------------------
1738
1739// -----------------------------------------------------------------------------
1740
1741// -----------------------------------------------------------------------------
1742// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
1743etiss_uint8 rd = 0;
1744static BitArrayRange R_rd_0(11, 7);
1745rd += R_rd_0.read(ba) << 0;
1746etiss_uint8 rm = 0;
1747static BitArrayRange R_rm_0(14, 12);
1748rm += R_rm_0.read(ba) << 0;
1749etiss_uint8 rs1 = 0;
1750static BitArrayRange R_rs1_0(19, 15);
1751rs1 += R_rs1_0.read(ba) << 0;
1752
1753// NOLINTEND(clang-diagnostic-unused-but-set-variable)
1754// -----------------------------------------------------------------------------
1755
1756 {
1757 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1758
1759 cp.code() = std::string("//FCVT_WU_S\n");
1760
1761// -----------------------------------------------------------------------------
1762cp.code() += "etiss_coverage_count(1, 105);\n";
1763{ // block
1764cp.code() += "etiss_coverage_count(1, 1189);\n";
1765cp.code() += "{ // block\n";
1766cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
1767cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
1768cp.code() += "} // block\n";
1769} // block
1770{ // block
1771cp.code() += "etiss_coverage_count(1, 4495);\n";
1772cp.code() += "{ // block\n";
1773cp.code() += "etiss_uint32 res = 0LL;\n";
1774cp.code() += "etiss_coverage_count(2, 4437, 4436);\n";
1775{ // block
1776cp.code() += "etiss_coverage_count(1, 4462);\n";
1777cp.code() += "{ // block\n";
1778cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
1779cp.code() += "etiss_coverage_count(4, 4455, 4454, 4453, 4452);\n";
1780cp.code() += "res = fcvt_s(frs1, 1ULL, " + std::to_string(rm) + "ULL);\n";
1781cp.code() += "etiss_coverage_count(6, 4461, 4456, 4460, 4457, 4458, 4459);\n";
1782cp.code() += "} // block\n";
1783} // block
1784cp.code() += "etiss_coverage_count(1, 4463);\n";
1785if ((rd % 32ULL) != 0LL) { // conditional
1786cp.code() += "etiss_coverage_count(5, 4469, 4466, 4464, 4467, 4468);\n";
1787cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)((etiss_int32)(res));\n";
1788cp.code() += "etiss_coverage_count(7, 4479, 4474, 4473, 4471, 4478, 4476, 4475);\n";
1789} // conditional
1790cp.code() += "etiss_uint32 flags = fget_flags();\n";
1791cp.code() += "etiss_coverage_count(2, 4482, 4481);\n";
1792cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1793cp.code() += "etiss_coverage_count(9, 4494, 4483, 4493, 4487, 4484, 4488, 4491, 4489, 4492);\n";
1794cp.code() += "} // block\n";
1795} // block
1796cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1797cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1798// -----------------------------------------------------------------------------
1799 cp.getAffectedRegisters().add("instructionPointer", 32);
1800 }
1801
1802 return true;
1803 },
1804 0,
1805 [] (BitArray & ba, Instruction & instr)
1806 {
1807// -----------------------------------------------------------------------------
1808etiss_uint8 rd = 0;
1809static BitArrayRange R_rd_0(11, 7);
1810rd += R_rd_0.read(ba) << 0;
1811etiss_uint8 rm = 0;
1812static BitArrayRange R_rm_0(14, 12);
1813rm += R_rm_0.read(ba) << 0;
1814etiss_uint8 rs1 = 0;
1815static BitArrayRange R_rs1_0(19, 15);
1816rs1 += R_rs1_0.read(ba) << 0;
1817
1818// -----------------------------------------------------------------------------
1819
1820 std::stringstream ss;
1821// -----------------------------------------------------------------------------
1822ss << "fcvt_wu_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
1823// -----------------------------------------------------------------------------
1824 return ss.str();
1825 }
1826);
1827
1828// FEQ_S -----------------------------------------------------------------------
1829static InstructionDefinition feq_s_rd_rs1_rs2 (
1830 ISA32_RV32IMACFD,
1831 "feq_s",
1832 (uint64_t) 0xa0002053,
1833 (uint64_t) 0xfe00707f,
1834 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1835 {
1836
1837// -----------------------------------------------------------------------------
1838
1839// -----------------------------------------------------------------------------
1840
1841// -----------------------------------------------------------------------------
1842// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
1843etiss_uint8 rd = 0;
1844static BitArrayRange R_rd_0(11, 7);
1845rd += R_rd_0.read(ba) << 0;
1846etiss_uint8 rs1 = 0;
1847static BitArrayRange R_rs1_0(19, 15);
1848rs1 += R_rs1_0.read(ba) << 0;
1849etiss_uint8 rs2 = 0;
1850static BitArrayRange R_rs2_0(24, 20);
1851rs2 += R_rs2_0.read(ba) << 0;
1852
1853// NOLINTEND(clang-diagnostic-unused-but-set-variable)
1854// -----------------------------------------------------------------------------
1855
1856 {
1857 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1858
1859 cp.code() = std::string("//FEQ_S\n");
1860
1861// -----------------------------------------------------------------------------
1862cp.code() += "etiss_coverage_count(1, 106);\n";
1863{ // block
1864cp.code() += "etiss_coverage_count(1, 1189);\n";
1865cp.code() += "{ // block\n";
1866cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
1867cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
1868cp.code() += "} // block\n";
1869} // block
1870{ // block
1871cp.code() += "etiss_coverage_count(1, 4561);\n";
1872cp.code() += "{ // block\n";
1873cp.code() += "etiss_uint32 res = 0LL;\n";
1874cp.code() += "etiss_coverage_count(2, 4498, 4497);\n";
1875{ // block
1876cp.code() += "etiss_coverage_count(1, 4531);\n";
1877cp.code() += "{ // block\n";
1878cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
1879cp.code() += "etiss_coverage_count(4, 4518, 4517, 4516, 4515);\n";
1880cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
1881cp.code() += "etiss_coverage_count(4, 4524, 4523, 4522, 4521);\n";
1882cp.code() += "res = fcmp_s(frs1, frs2, 0LL);\n";
1883cp.code() += "etiss_coverage_count(6, 4530, 4525, 4529, 4526, 4527, 4528);\n";
1884cp.code() += "} // block\n";
1885} // block
1886cp.code() += "etiss_coverage_count(1, 4532);\n";
1887if ((rd % 32ULL) != 0LL) { // conditional
1888cp.code() += "etiss_coverage_count(5, 4538, 4535, 4533, 4536, 4537);\n";
1889cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
1890cp.code() += "etiss_coverage_count(5, 4545, 4543, 4542, 4540, 4544);\n";
1891} // conditional
1892cp.code() += "etiss_uint32 flags = fget_flags();\n";
1893cp.code() += "etiss_coverage_count(2, 4548, 4547);\n";
1894cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1895cp.code() += "etiss_coverage_count(9, 4560, 4549, 4559, 4553, 4550, 4554, 4557, 4555, 4558);\n";
1896cp.code() += "} // block\n";
1897} // block
1898cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
1899cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
1900// -----------------------------------------------------------------------------
1901 cp.getAffectedRegisters().add("instructionPointer", 32);
1902 }
1903
1904 return true;
1905 },
1906 0,
1907 [] (BitArray & ba, Instruction & instr)
1908 {
1909// -----------------------------------------------------------------------------
1910etiss_uint8 rd = 0;
1911static BitArrayRange R_rd_0(11, 7);
1912rd += R_rd_0.read(ba) << 0;
1913etiss_uint8 rs1 = 0;
1914static BitArrayRange R_rs1_0(19, 15);
1915rs1 += R_rs1_0.read(ba) << 0;
1916etiss_uint8 rs2 = 0;
1917static BitArrayRange R_rs2_0(24, 20);
1918rs2 += R_rs2_0.read(ba) << 0;
1919
1920// -----------------------------------------------------------------------------
1921
1922 std::stringstream ss;
1923// -----------------------------------------------------------------------------
1924ss << "feq_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
1925// -----------------------------------------------------------------------------
1926 return ss.str();
1927 }
1928);
1929
1930// FLT_S -----------------------------------------------------------------------
1931static InstructionDefinition flt_s_rd_rs1_rs2 (
1932 ISA32_RV32IMACFD,
1933 "flt_s",
1934 (uint64_t) 0xa0001053,
1935 (uint64_t) 0xfe00707f,
1936 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
1937 {
1938
1939// -----------------------------------------------------------------------------
1940
1941// -----------------------------------------------------------------------------
1942
1943// -----------------------------------------------------------------------------
1944// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
1945etiss_uint8 rd = 0;
1946static BitArrayRange R_rd_0(11, 7);
1947rd += R_rd_0.read(ba) << 0;
1948etiss_uint8 rs1 = 0;
1949static BitArrayRange R_rs1_0(19, 15);
1950rs1 += R_rs1_0.read(ba) << 0;
1951etiss_uint8 rs2 = 0;
1952static BitArrayRange R_rs2_0(24, 20);
1953rs2 += R_rs2_0.read(ba) << 0;
1954
1955// NOLINTEND(clang-diagnostic-unused-but-set-variable)
1956// -----------------------------------------------------------------------------
1957
1958 {
1959 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
1960
1961 cp.code() = std::string("//FLT_S\n");
1962
1963// -----------------------------------------------------------------------------
1964cp.code() += "etiss_coverage_count(1, 107);\n";
1965{ // block
1966cp.code() += "etiss_coverage_count(1, 1189);\n";
1967cp.code() += "{ // block\n";
1968cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
1969cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
1970cp.code() += "} // block\n";
1971} // block
1972{ // block
1973cp.code() += "etiss_coverage_count(1, 4627);\n";
1974cp.code() += "{ // block\n";
1975cp.code() += "etiss_uint32 res = 0LL;\n";
1976cp.code() += "etiss_coverage_count(2, 4564, 4563);\n";
1977{ // block
1978cp.code() += "etiss_coverage_count(1, 4597);\n";
1979cp.code() += "{ // block\n";
1980cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
1981cp.code() += "etiss_coverage_count(4, 4584, 4583, 4582, 4581);\n";
1982cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
1983cp.code() += "etiss_coverage_count(4, 4590, 4589, 4588, 4587);\n";
1984cp.code() += "res = fcmp_s(frs1, frs2, 2ULL);\n";
1985cp.code() += "etiss_coverage_count(6, 4596, 4591, 4595, 4592, 4593, 4594);\n";
1986cp.code() += "} // block\n";
1987} // block
1988cp.code() += "etiss_coverage_count(1, 4598);\n";
1989if ((rd % 32ULL) != 0LL) { // conditional
1990cp.code() += "etiss_coverage_count(5, 4604, 4601, 4599, 4602, 4603);\n";
1991cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
1992cp.code() += "etiss_coverage_count(5, 4611, 4609, 4608, 4606, 4610);\n";
1993} // conditional
1994cp.code() += "etiss_uint32 flags = fget_flags();\n";
1995cp.code() += "etiss_coverage_count(2, 4614, 4613);\n";
1996cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
1997cp.code() += "etiss_coverage_count(9, 4626, 4615, 4625, 4619, 4616, 4620, 4623, 4621, 4624);\n";
1998cp.code() += "} // block\n";
1999} // block
2000cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2001cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2002// -----------------------------------------------------------------------------
2003 cp.getAffectedRegisters().add("instructionPointer", 32);
2004 }
2005
2006 return true;
2007 },
2008 0,
2009 [] (BitArray & ba, Instruction & instr)
2010 {
2011// -----------------------------------------------------------------------------
2012etiss_uint8 rd = 0;
2013static BitArrayRange R_rd_0(11, 7);
2014rd += R_rd_0.read(ba) << 0;
2015etiss_uint8 rs1 = 0;
2016static BitArrayRange R_rs1_0(19, 15);
2017rs1 += R_rs1_0.read(ba) << 0;
2018etiss_uint8 rs2 = 0;
2019static BitArrayRange R_rs2_0(24, 20);
2020rs2 += R_rs2_0.read(ba) << 0;
2021
2022// -----------------------------------------------------------------------------
2023
2024 std::stringstream ss;
2025// -----------------------------------------------------------------------------
2026ss << "flt_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
2027// -----------------------------------------------------------------------------
2028 return ss.str();
2029 }
2030);
2031
2032// FLE_S -----------------------------------------------------------------------
2033static InstructionDefinition fle_s_rd_rs1_rs2 (
2034 ISA32_RV32IMACFD,
2035 "fle_s",
2036 (uint64_t) 0xa0000053,
2037 (uint64_t) 0xfe00707f,
2038 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2039 {
2040
2041// -----------------------------------------------------------------------------
2042
2043// -----------------------------------------------------------------------------
2044
2045// -----------------------------------------------------------------------------
2046// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
2047etiss_uint8 rd = 0;
2048static BitArrayRange R_rd_0(11, 7);
2049rd += R_rd_0.read(ba) << 0;
2050etiss_uint8 rs1 = 0;
2051static BitArrayRange R_rs1_0(19, 15);
2052rs1 += R_rs1_0.read(ba) << 0;
2053etiss_uint8 rs2 = 0;
2054static BitArrayRange R_rs2_0(24, 20);
2055rs2 += R_rs2_0.read(ba) << 0;
2056
2057// NOLINTEND(clang-diagnostic-unused-but-set-variable)
2058// -----------------------------------------------------------------------------
2059
2060 {
2061 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2062
2063 cp.code() = std::string("//FLE_S\n");
2064
2065// -----------------------------------------------------------------------------
2066cp.code() += "etiss_coverage_count(1, 108);\n";
2067{ // block
2068cp.code() += "etiss_coverage_count(1, 1189);\n";
2069cp.code() += "{ // block\n";
2070cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
2071cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
2072cp.code() += "} // block\n";
2073} // block
2074{ // block
2075cp.code() += "etiss_coverage_count(1, 4693);\n";
2076cp.code() += "{ // block\n";
2077cp.code() += "etiss_uint32 res = 0LL;\n";
2078cp.code() += "etiss_coverage_count(2, 4630, 4629);\n";
2079{ // block
2080cp.code() += "etiss_coverage_count(1, 4663);\n";
2081cp.code() += "{ // block\n";
2082cp.code() += "etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]);\n";
2083cp.code() += "etiss_coverage_count(4, 4650, 4649, 4648, 4647);\n";
2084cp.code() += "etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
2085cp.code() += "etiss_coverage_count(4, 4656, 4655, 4654, 4653);\n";
2086cp.code() += "res = fcmp_s(frs1, frs2, 1ULL);\n";
2087cp.code() += "etiss_coverage_count(6, 4662, 4657, 4661, 4658, 4659, 4660);\n";
2088cp.code() += "} // block\n";
2089} // block
2090cp.code() += "etiss_coverage_count(1, 4664);\n";
2091if ((rd % 32ULL) != 0LL) { // conditional
2092cp.code() += "etiss_coverage_count(5, 4670, 4667, 4665, 4668, 4669);\n";
2093cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
2094cp.code() += "etiss_coverage_count(5, 4677, 4675, 4674, 4672, 4676);\n";
2095} // conditional
2096cp.code() += "etiss_uint32 flags = fget_flags();\n";
2097cp.code() += "etiss_coverage_count(2, 4680, 4679);\n";
2098cp.code() += "((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";
2099cp.code() += "etiss_coverage_count(9, 4692, 4681, 4691, 4685, 4682, 4686, 4689, 4687, 4690);\n";
2100cp.code() += "} // block\n";
2101} // block
2102cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2103cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2104// -----------------------------------------------------------------------------
2105 cp.getAffectedRegisters().add("instructionPointer", 32);
2106 }
2107
2108 return true;
2109 },
2110 0,
2111 [] (BitArray & ba, Instruction & instr)
2112 {
2113// -----------------------------------------------------------------------------
2114etiss_uint8 rd = 0;
2115static BitArrayRange R_rd_0(11, 7);
2116rd += R_rd_0.read(ba) << 0;
2117etiss_uint8 rs1 = 0;
2118static BitArrayRange R_rs1_0(19, 15);
2119rs1 += R_rs1_0.read(ba) << 0;
2120etiss_uint8 rs2 = 0;
2121static BitArrayRange R_rs2_0(24, 20);
2122rs2 += R_rs2_0.read(ba) << 0;
2123
2124// -----------------------------------------------------------------------------
2125
2126 std::stringstream ss;
2127// -----------------------------------------------------------------------------
2128ss << "fle_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + " | rs2=" + std::to_string(rs2) + "]");
2129// -----------------------------------------------------------------------------
2130 return ss.str();
2131 }
2132);
2133
2134// FCLASS_S --------------------------------------------------------------------
2135static InstructionDefinition fclass_s_rd_rs1 (
2136 ISA32_RV32IMACFD,
2137 "fclass_s",
2138 (uint64_t) 0xe0001053,
2139 (uint64_t) 0xfff0707f,
2140 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2141 {
2142
2143// -----------------------------------------------------------------------------
2144
2145// -----------------------------------------------------------------------------
2146
2147// -----------------------------------------------------------------------------
2148// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
2149etiss_uint8 rd = 0;
2150static BitArrayRange R_rd_0(11, 7);
2151rd += R_rd_0.read(ba) << 0;
2152etiss_uint8 rs1 = 0;
2153static BitArrayRange R_rs1_0(19, 15);
2154rs1 += R_rs1_0.read(ba) << 0;
2155
2156// NOLINTEND(clang-diagnostic-unused-but-set-variable)
2157// -----------------------------------------------------------------------------
2158
2159 {
2160 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2161
2162 cp.code() = std::string("//FCLASS_S\n");
2163
2164// -----------------------------------------------------------------------------
2165cp.code() += "etiss_coverage_count(1, 109);\n";
2166{ // block
2167cp.code() += "etiss_coverage_count(1, 1189);\n";
2168cp.code() += "{ // block\n";
2169cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
2170cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
2171cp.code() += "} // block\n";
2172} // block
2173{ // block
2174cp.code() += "etiss_coverage_count(1, 4728);\n";
2175cp.code() += "{ // block\n";
2176cp.code() += "etiss_uint32 res = 0LL;\n";
2177cp.code() += "etiss_coverage_count(2, 4696, 4695);\n";
2178cp.code() += "res = fclass_s(unbox_s(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]));\n";
2179cp.code() += "etiss_coverage_count(6, 4713, 4707, 4712, 4711, 4710, 4709);\n";
2180cp.code() += "etiss_coverage_count(1, 4714);\n";
2181if ((rd % 32ULL) != 0LL) { // conditional
2182cp.code() += "etiss_coverage_count(5, 4720, 4717, 4715, 4718, 4719);\n";
2183cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = res;\n";
2184cp.code() += "etiss_coverage_count(5, 4727, 4725, 4724, 4722, 4726);\n";
2185} // conditional
2186cp.code() += "} // block\n";
2187} // block
2188cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2189cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2190// -----------------------------------------------------------------------------
2191 cp.getAffectedRegisters().add("instructionPointer", 32);
2192 }
2193
2194 return true;
2195 },
2196 0,
2197 [] (BitArray & ba, Instruction & instr)
2198 {
2199// -----------------------------------------------------------------------------
2200etiss_uint8 rd = 0;
2201static BitArrayRange R_rd_0(11, 7);
2202rd += R_rd_0.read(ba) << 0;
2203etiss_uint8 rs1 = 0;
2204static BitArrayRange R_rs1_0(19, 15);
2205rs1 += R_rs1_0.read(ba) << 0;
2206
2207// -----------------------------------------------------------------------------
2208
2209 std::stringstream ss;
2210// -----------------------------------------------------------------------------
2211ss << "fclass_s" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + "]");
2212// -----------------------------------------------------------------------------
2213 return ss.str();
2214 }
2215);
2216
2217// FCVT_S_W --------------------------------------------------------------------
2218static InstructionDefinition fcvt_s_w_rd_rm_rs1 (
2219 ISA32_RV32IMACFD,
2220 "fcvt_s_w",
2221 (uint64_t) 0xd0000053,
2222 (uint64_t) 0xfff0007f,
2223 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2224 {
2225
2226// -----------------------------------------------------------------------------
2227
2228// -----------------------------------------------------------------------------
2229
2230// -----------------------------------------------------------------------------
2231// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
2232etiss_uint8 rd = 0;
2233static BitArrayRange R_rd_0(11, 7);
2234rd += R_rd_0.read(ba) << 0;
2235etiss_uint8 rm = 0;
2236static BitArrayRange R_rm_0(14, 12);
2237rm += R_rm_0.read(ba) << 0;
2238etiss_uint8 rs1 = 0;
2239static BitArrayRange R_rs1_0(19, 15);
2240rs1 += R_rs1_0.read(ba) << 0;
2241
2242// NOLINTEND(clang-diagnostic-unused-but-set-variable)
2243// -----------------------------------------------------------------------------
2244
2245 {
2246 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2247
2248 cp.code() = std::string("//FCVT_S_W\n");
2249
2250// -----------------------------------------------------------------------------
2251cp.code() += "etiss_coverage_count(1, 110);\n";
2252{ // block
2253cp.code() += "etiss_coverage_count(1, 1189);\n";
2254cp.code() += "{ // block\n";
2255cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
2256cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
2257cp.code() += "} // block\n";
2258} // block
2259{ // block
2260cp.code() += "etiss_coverage_count(1, 4773);\n";
2261cp.code() += "{ // block\n";
2262{ // block
2263cp.code() += "etiss_coverage_count(1, 4772);\n";
2264cp.code() += "{ // block\n";
2265cp.code() += "etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), 2ULL, " + std::to_string(rm) + "ULL);\n";
2266cp.code() += "etiss_coverage_count(8, 4756, 4755, 4752, 4751, 4750, 4748, 4753, 4754);\n";
2267cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
2268cp.code() += "etiss_coverage_count(6, 4771, 4759, 4758, 4770, 4769, 4767);\n";
2269cp.code() += "} // block\n";
2270} // block
2271cp.code() += "} // block\n";
2272} // block
2273cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2274cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2275// -----------------------------------------------------------------------------
2276 cp.getAffectedRegisters().add("instructionPointer", 32);
2277 }
2278
2279 return true;
2280 },
2281 0,
2282 [] (BitArray & ba, Instruction & instr)
2283 {
2284// -----------------------------------------------------------------------------
2285etiss_uint8 rd = 0;
2286static BitArrayRange R_rd_0(11, 7);
2287rd += R_rd_0.read(ba) << 0;
2288etiss_uint8 rm = 0;
2289static BitArrayRange R_rm_0(14, 12);
2290rm += R_rm_0.read(ba) << 0;
2291etiss_uint8 rs1 = 0;
2292static BitArrayRange R_rs1_0(19, 15);
2293rs1 += R_rs1_0.read(ba) << 0;
2294
2295// -----------------------------------------------------------------------------
2296
2297 std::stringstream ss;
2298// -----------------------------------------------------------------------------
2299ss << "fcvt_s_w" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
2300// -----------------------------------------------------------------------------
2301 return ss.str();
2302 }
2303);
2304
2305// FCVT_S_WU -------------------------------------------------------------------
2306static InstructionDefinition fcvt_s_wu_rd_rm_rs1 (
2307 ISA32_RV32IMACFD,
2308 "fcvt_s_wu",
2309 (uint64_t) 0xd0100053,
2310 (uint64_t) 0xfff0007f,
2311 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2312 {
2313
2314// -----------------------------------------------------------------------------
2315
2316// -----------------------------------------------------------------------------
2317
2318// -----------------------------------------------------------------------------
2319// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
2320etiss_uint8 rd = 0;
2321static BitArrayRange R_rd_0(11, 7);
2322rd += R_rd_0.read(ba) << 0;
2323etiss_uint8 rm = 0;
2324static BitArrayRange R_rm_0(14, 12);
2325rm += R_rm_0.read(ba) << 0;
2326etiss_uint8 rs1 = 0;
2327static BitArrayRange R_rs1_0(19, 15);
2328rs1 += R_rs1_0.read(ba) << 0;
2329
2330// NOLINTEND(clang-diagnostic-unused-but-set-variable)
2331// -----------------------------------------------------------------------------
2332
2333 {
2334 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2335
2336 cp.code() = std::string("//FCVT_S_WU\n");
2337
2338// -----------------------------------------------------------------------------
2339cp.code() += "etiss_coverage_count(1, 111);\n";
2340{ // block
2341cp.code() += "etiss_coverage_count(1, 1189);\n";
2342cp.code() += "{ // block\n";
2343cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
2344cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
2345cp.code() += "} // block\n";
2346} // block
2347{ // block
2348cp.code() += "etiss_coverage_count(1, 4818);\n";
2349cp.code() += "{ // block\n";
2350{ // block
2351cp.code() += "etiss_coverage_count(1, 4817);\n";
2352cp.code() += "{ // block\n";
2353cp.code() += "etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]), 3ULL, " + std::to_string(rm) + "ULL);\n";
2354cp.code() += "etiss_coverage_count(8, 4801, 4800, 4797, 4796, 4795, 4793, 4798, 4799);\n";
2355cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(res);\n";
2356cp.code() += "etiss_coverage_count(6, 4816, 4804, 4803, 4815, 4814, 4812);\n";
2357cp.code() += "} // block\n";
2358} // block
2359cp.code() += "} // block\n";
2360} // block
2361cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2362cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2363// -----------------------------------------------------------------------------
2364 cp.getAffectedRegisters().add("instructionPointer", 32);
2365 }
2366
2367 return true;
2368 },
2369 0,
2370 [] (BitArray & ba, Instruction & instr)
2371 {
2372// -----------------------------------------------------------------------------
2373etiss_uint8 rd = 0;
2374static BitArrayRange R_rd_0(11, 7);
2375rd += R_rd_0.read(ba) << 0;
2376etiss_uint8 rm = 0;
2377static BitArrayRange R_rm_0(14, 12);
2378rm += R_rm_0.read(ba) << 0;
2379etiss_uint8 rs1 = 0;
2380static BitArrayRange R_rs1_0(19, 15);
2381rs1 += R_rs1_0.read(ba) << 0;
2382
2383// -----------------------------------------------------------------------------
2384
2385 std::stringstream ss;
2386// -----------------------------------------------------------------------------
2387ss << "fcvt_s_wu" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rm=" + std::to_string(rm) + " | rs1=" + std::to_string(rs1) + "]");
2388// -----------------------------------------------------------------------------
2389 return ss.str();
2390 }
2391);
2392
2393// FMV_X_W ---------------------------------------------------------------------
2394static InstructionDefinition fmv_x_w_rd_rs1 (
2395 ISA32_RV32IMACFD,
2396 "fmv_x_w",
2397 (uint64_t) 0xe0000053,
2398 (uint64_t) 0xfff0707f,
2399 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2400 {
2401
2402// -----------------------------------------------------------------------------
2403
2404// -----------------------------------------------------------------------------
2405
2406// -----------------------------------------------------------------------------
2407// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
2408etiss_uint8 rd = 0;
2409static BitArrayRange R_rd_0(11, 7);
2410rd += R_rd_0.read(ba) << 0;
2411etiss_uint8 rs1 = 0;
2412static BitArrayRange R_rs1_0(19, 15);
2413rs1 += R_rs1_0.read(ba) << 0;
2414
2415// NOLINTEND(clang-diagnostic-unused-but-set-variable)
2416// -----------------------------------------------------------------------------
2417
2418 {
2419 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2420
2421 cp.code() = std::string("//FMV_X_W\n");
2422
2423// -----------------------------------------------------------------------------
2424cp.code() += "etiss_coverage_count(1, 112);\n";
2425{ // block
2426cp.code() += "etiss_coverage_count(1, 1189);\n";
2427cp.code() += "{ // block\n";
2428cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
2429cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
2430cp.code() += "} // block\n";
2431} // block
2432{ // block
2433cp.code() += "etiss_coverage_count(1, 4839);\n";
2434cp.code() += "{ // block\n";
2435cp.code() += "etiss_coverage_count(1, 4819);\n";
2436if ((rd % 32ULL) != 0LL) { // conditional
2437cp.code() += "etiss_coverage_count(5, 4825, 4822, 4820, 4823, 4824);\n";
2438cp.code() += "*((RV32IMACFD*)cpu)->X[" + std::to_string(rd % 32ULL) + "ULL] = (etiss_uint32)((etiss_int32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs1) + "ULL]));\n";
2439cp.code() += "etiss_coverage_count(8, 4838, 4830, 4829, 4827, 4837, 4835, 4833, 4832);\n";
2440} // conditional
2441cp.code() += "} // block\n";
2442} // block
2443cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2444cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2445// -----------------------------------------------------------------------------
2446 cp.getAffectedRegisters().add("instructionPointer", 32);
2447 }
2448
2449 return true;
2450 },
2451 0,
2452 [] (BitArray & ba, Instruction & instr)
2453 {
2454// -----------------------------------------------------------------------------
2455etiss_uint8 rd = 0;
2456static BitArrayRange R_rd_0(11, 7);
2457rd += R_rd_0.read(ba) << 0;
2458etiss_uint8 rs1 = 0;
2459static BitArrayRange R_rs1_0(19, 15);
2460rs1 += R_rs1_0.read(ba) << 0;
2461
2462// -----------------------------------------------------------------------------
2463
2464 std::stringstream ss;
2465// -----------------------------------------------------------------------------
2466ss << "fmv_x_w" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + "]");
2467// -----------------------------------------------------------------------------
2468 return ss.str();
2469 }
2470);
2471
2472// FMV_W_X ---------------------------------------------------------------------
2473static InstructionDefinition fmv_w_x_rd_rs1 (
2474 ISA32_RV32IMACFD,
2475 "fmv_w_x",
2476 (uint64_t) 0xf0000053,
2477 (uint64_t) 0xfff0707f,
2478 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
2479 {
2480
2481// -----------------------------------------------------------------------------
2482
2483// -----------------------------------------------------------------------------
2484
2485// -----------------------------------------------------------------------------
2486// NOLINTBEGIN(clang-diagnostic-unused-but-set-variable)
2487etiss_uint8 rd = 0;
2488static BitArrayRange R_rd_0(11, 7);
2489rd += R_rd_0.read(ba) << 0;
2490etiss_uint8 rs1 = 0;
2491static BitArrayRange R_rs1_0(19, 15);
2492rs1 += R_rs1_0.read(ba) << 0;
2493
2494// NOLINTEND(clang-diagnostic-unused-but-set-variable)
2495// -----------------------------------------------------------------------------
2496
2497 {
2498 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
2499
2500 cp.code() = std::string("//FMV_W_X\n");
2501
2502// -----------------------------------------------------------------------------
2503cp.code() += "etiss_coverage_count(1, 113);\n";
2504{ // block
2505cp.code() += "etiss_coverage_count(1, 1189);\n";
2506cp.code() += "{ // block\n";
2507cp.code() += "cpu->nextPc = " + std::to_string((etiss_uint32)((ic.current_address_ + 4))) + "ULL;\n";
2508cp.code() += "etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";
2509cp.code() += "} // block\n";
2510} // block
2511{ // block
2512cp.code() += "etiss_coverage_count(1, 4873);\n";
2513cp.code() += "{ // block\n";
2514{ // block
2515cp.code() += "etiss_coverage_count(1, 4872);\n";
2516cp.code() += "{ // block\n";
2517cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | (etiss_uint64)(*((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 % 32ULL) + "ULL]);\n";
2518cp.code() += "etiss_coverage_count(8, 4871, 4855, 4854, 4870, 4869, 4867, 4866, 4864);\n";
2519cp.code() += "} // block\n";
2520} // block
2521cp.code() += "} // block\n";
2522} // block
2523cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
2524cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
2525// -----------------------------------------------------------------------------
2526 cp.getAffectedRegisters().add("instructionPointer", 32);
2527 }
2528
2529 return true;
2530 },
2531 0,
2532 [] (BitArray & ba, Instruction & instr)
2533 {
2534// -----------------------------------------------------------------------------
2535etiss_uint8 rd = 0;
2536static BitArrayRange R_rd_0(11, 7);
2537rd += R_rd_0.read(ba) << 0;
2538etiss_uint8 rs1 = 0;
2539static BitArrayRange R_rs1_0(19, 15);
2540rs1 += R_rs1_0.read(ba) << 0;
2541
2542// -----------------------------------------------------------------------------
2543
2544 std::stringstream ss;
2545// -----------------------------------------------------------------------------
2546ss << "fmv_w_x" << " # " << ba << (" [rd=" + std::to_string(rd) + " | rs1=" + std::to_string(rs1) + "]");
2547// -----------------------------------------------------------------------------
2548 return ss.str();
2549 }
2550);
2551// clang-format on
ISA32_RV32IMACFD
etiss::instr::InstructionGroup ISA32_RV32IMACFD("ISA32_RV32IMACFD", 32)
fle_s_rd_rs1_rs2
static InstructionDefinition fle_s_rd_rs1_rs2(ISA32_RV32IMACFD, "fle_s",(uint64_t) 0xa0000053,(uint64_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FLE_S\n");cp.code()+="etiss_coverage_count(1, 108);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4693);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = 0LL;\n";cp.code()+="etiss_coverage_count(2, 4630, 4629);\n";{ cp.code()+="etiss_coverage_count(1, 4663);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4650, 4649, 4648, 4647);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4656, 4655, 4654, 4653);\n";cp.code()+="res = fcmp_s(frs1, frs2, 1ULL);\n";cp.code()+="etiss_coverage_count(6, 4662, 4657, 4661, 4658, 4659, 4660);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 4664);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 4670, 4667, 4665, 4668, 4669);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 4677, 4675, 4674, 4672, 4676);\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 4680, 4679);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 4692, 4681, 4691, 4685, 4682, 4686, 4689, 4687, 4690);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fle_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fdiv_s_rd_rm_rs1_rs2
static InstructionDefinition fdiv_s_rd_rm_rs1_rs2(ISA32_RV32IMACFD, "fdiv_s",(uint64_t) 0x18000053,(uint64_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FDIV_S\n");cp.code()+="etiss_coverage_count(1, 97);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4011);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 3995);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 3966, 3965, 3964, 3963);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 3972, 3971, 3970, 3969);\n";cp.code()+="etiss_uint32 res = fdiv_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(6, 3979, 3978, 3974, 3975, 3977, 3976);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 3994, 3982, 3981, 3993, 3992, 3990);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 3998, 3997);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 4010, 3999, 4009, 4003, 4000, 4004, 4007, 4005, 4008);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fdiv_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fcvt_w_s_rd_rm_rs1
static InstructionDefinition fcvt_w_s_rd_rm_rs1(ISA32_RV32IMACFD, "fcvt_w_s",(uint64_t) 0xc0000053,(uint64_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_W_S\n");cp.code()+="etiss_coverage_count(1, 104);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4434);\n";cp.code()+="{ // block\n";cp.code()+="etiss_int32 res = 0LL;\n";cp.code()+="etiss_coverage_count(2, 4379, 4378);\n";{ cp.code()+="etiss_coverage_count(1, 4404);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4397, 4396, 4395, 4394);\n";cp.code()+="res = fcvt_s(frs1, 0LL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(6, 4403, 4398, 4402, 4399, 4400, 4401);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 4405);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 4411, 4408, 4406, 4409, 4410);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 4418, 4416, 4415, 4413, 4417);\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 4421, 4420);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 4433, 4422, 4432, 4426, 4423, 4427, 4430, 4428, 4431);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_w_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fmadd_s_rd_rm_rs1_rs2_rs3
static InstructionDefinition fmadd_s_rd_rm_rs1_rs2_rs3(ISA32_RV32IMACFD, "fmadd_s",(uint64_t) 0x000043,(uint64_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMADD_S\n");cp.code()+="etiss_coverage_count(1, 90);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3508);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 3492);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs3)+"ULL]), 0LL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(14, 3476, 3475, 3463, 3462, 3461, 3467, 3466, 3465, 3471, 3470, 3469, 3472, 3474, 3473);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 3491, 3479, 3478, 3490, 3489, 3487);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 3495, 3494);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 3507, 3496, 3506, 3500, 3497, 3501, 3504, 3502, 3505);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;std::stringstream ss;ss<< "fmadd_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rs3="+std::to_string(rs3)+"]");return ss.str();})
fnmsub_s_rd_rm_rs1_rs2_rs3
static InstructionDefinition fnmsub_s_rd_rm_rs1_rs2_rs3(ISA32_RV32IMACFD, "fnmsub_s",(uint64_t) 0x00004b,(uint64_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FNMSUB_S\n");cp.code()+="etiss_coverage_count(1, 93);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3739);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 3723);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 3686, 3685, 3684, 3683);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 3692, 3691, 3690, 3689);\n";cp.code()+="etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs3)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 3698, 3697, 3696, 3695);\n";cp.code()+="etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 3ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(8, 3707, 3706, 3700, 3701, 3702, 3703, 3705, 3704);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 3722, 3710, 3709, 3721, 3720, 3718);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 3726, 3725);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 3738, 3727, 3737, 3731, 3728, 3732, 3735, 3733, 3736);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;std::stringstream ss;ss<< "fnmsub_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rs3="+std::to_string(rs3)+"]");return ss.str();})
fmv_x_w_rd_rs1
static InstructionDefinition fmv_x_w_rd_rs1(ISA32_RV32IMACFD, "fmv_x_w",(uint64_t) 0xe0000053,(uint64_t) 0xfff0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMV_X_W\n");cp.code()+="etiss_coverage_count(1, 112);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4839);\n";cp.code()+="{ // block\n";cp.code()+="etiss_coverage_count(1, 4819);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 4825, 4822, 4820, 4823, 4824);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint32)((etiss_int32)(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]));\n";cp.code()+="etiss_coverage_count(8, 4838, 4830, 4829, 4827, 4837, 4835, 4833, 4832);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fmv_x_w"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fcvt_s_wu_rd_rm_rs1
static InstructionDefinition fcvt_s_wu_rd_rm_rs1(ISA32_RV32IMACFD, "fcvt_s_wu",(uint64_t) 0xd0100053,(uint64_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_S_WU\n");cp.code()+="etiss_coverage_count(1, 111);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4818);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 4817);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]), 3ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(8, 4801, 4800, 4797, 4796, 4795, 4793, 4798, 4799);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 4816, 4804, 4803, 4815, 4814, 4812);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_s_wu"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fmsub_s_rd_rm_rs1_rs2_rs3
static InstructionDefinition fmsub_s_rd_rm_rs1_rs2_rs3(ISA32_RV32IMACFD, "fmsub_s",(uint64_t) 0x000047,(uint64_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMSUB_S\n");cp.code()+="etiss_coverage_count(1, 91);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3579);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 3563);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = fmadd_s(unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]), unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]), unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs3)+"ULL]), 1ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(14, 3547, 3546, 3534, 3533, 3532, 3538, 3537, 3536, 3542, 3541, 3540, 3543, 3545, 3544);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 3562, 3550, 3549, 3561, 3560, 3558);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 3566, 3565);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 3578, 3567, 3577, 3571, 3568, 3572, 3575, 3573, 3576);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;std::stringstream ss;ss<< "fmsub_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rs3="+std::to_string(rs3)+"]");return ss.str();})
fmv_w_x_rd_rs1
static InstructionDefinition fmv_w_x_rd_rs1(ISA32_RV32IMACFD, "fmv_w_x",(uint64_t) 0xf0000053,(uint64_t) 0xfff0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMV_W_X\n");cp.code()+="etiss_coverage_count(1, 113);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4873);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 4872);\n";cp.code()+="{ // block\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(8, 4871, 4855, 4854, 4870, 4869, 4867, 4866, 4864);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fmv_w_x"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fsqrt_s_rd_rm_rs1
static InstructionDefinition fsqrt_s_rd_rm_rs1(ISA32_RV32IMACFD, "fsqrt_s",(uint64_t) 0x58000053,(uint64_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSQRT_S\n");cp.code()+="etiss_coverage_count(1, 98);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4069);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 4053);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4031, 4030, 4029, 4028);\n";cp.code()+="etiss_uint32 res = fsqrt_s(frs1, RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(5, 4037, 4036, 4033, 4035, 4034);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 4052, 4040, 4039, 4051, 4050, 4048);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 4056, 4055);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 4068, 4057, 4067, 4061, 4058, 4062, 4065, 4063, 4066);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fsqrt_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fmin_s_rd_rs1_rs2
static InstructionDefinition fmin_s_rd_rs1_rs2(ISA32_RV32IMACFD, "fmin_s",(uint64_t) 0x28000053,(uint64_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMIN_S\n");cp.code()+="etiss_coverage_count(1, 102);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4310);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 4294);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4266, 4265, 4264, 4263);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4272, 4271, 4270, 4269);\n";cp.code()+="etiss_uint32 res = fsel_s(frs1, frs2, 0LL);\n";cp.code()+="etiss_coverage_count(5, 4278, 4277, 4274, 4275, 4276);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 4293, 4281, 4280, 4292, 4291, 4289);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 4297, 4296);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 4309, 4298, 4308, 4302, 4299, 4303, 4306, 4304, 4307);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fmin_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fsgnjx_s_rd_rs1_rs2
static InstructionDefinition fsgnjx_s_rd_rs1_rs2(ISA32_RV32IMACFD, "fsgnjx_s",(uint64_t) 0x20002053,(uint64_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSGNJX_S\n");cp.code()+="etiss_coverage_count(1, 101);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4244);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 4243);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4213, 4212, 4211, 4210);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4219, 4218, 4217, 4216);\n";cp.code()+="etiss_uint32 res = frs1 ^ (frs2 & 2147483648ULL);\n";cp.code()+="etiss_coverage_count(7, 4227, 4226, 4221, 4224, 4222, 4223, 4225);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 4242, 4230, 4229, 4241, 4240, 4238);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fsgnjx_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
feq_s_rd_rs1_rs2
static InstructionDefinition feq_s_rd_rs1_rs2(ISA32_RV32IMACFD, "feq_s",(uint64_t) 0xa0002053,(uint64_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FEQ_S\n");cp.code()+="etiss_coverage_count(1, 106);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4561);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = 0LL;\n";cp.code()+="etiss_coverage_count(2, 4498, 4497);\n";{ cp.code()+="etiss_coverage_count(1, 4531);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4518, 4517, 4516, 4515);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4524, 4523, 4522, 4521);\n";cp.code()+="res = fcmp_s(frs1, frs2, 0LL);\n";cp.code()+="etiss_coverage_count(6, 4530, 4525, 4529, 4526, 4527, 4528);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 4532);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 4538, 4535, 4533, 4536, 4537);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 4545, 4543, 4542, 4540, 4544);\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 4548, 4547);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 4560, 4549, 4559, 4553, 4550, 4554, 4557, 4555, 4558);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "feq_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fsub_s_rd_rm_rs1_rs2
static InstructionDefinition fsub_s_rd_rm_rs1_rs2(ISA32_RV32IMACFD, "fsub_s",(uint64_t) 0x8000053,(uint64_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSUB_S\n");cp.code()+="etiss_coverage_count(1, 95);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3875);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 3859);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 3830, 3829, 3828, 3827);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 3836, 3835, 3834, 3833);\n";cp.code()+="etiss_uint32 res = fsub_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(6, 3843, 3842, 3838, 3839, 3841, 3840);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 3858, 3846, 3845, 3857, 3856, 3854);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 3862, 3861);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 3874, 3863, 3873, 3867, 3864, 3868, 3871, 3869, 3872);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fsub_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fsgnj_s_rd_rs1_rs2
static InstructionDefinition fsgnj_s_rd_rs1_rs2(ISA32_RV32IMACFD, "fsgnj_s",(uint64_t) 0x20000053,(uint64_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSGNJ_S\n");cp.code()+="etiss_coverage_count(1, 99);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4128);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 4127);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4096, 4095, 4094, 4093);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4102, 4101, 4100, 4099);\n";cp.code()+="etiss_uint32 res = ((((((frs2) >> (31ULL)) & 0x1ULL)) << 31) | (((frs1) & 0x7fffffffULL)));\n";cp.code()+="etiss_coverage_count(10, 4113, 4112, 4107, 4104, 4105, 4106, 4111, 4108, 4109, 4110);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 4126, 4116, 4115, 4125, 4124, 4122);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fsgnj_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fcvt_s_w_rd_rm_rs1
static InstructionDefinition fcvt_s_w_rd_rm_rs1(ISA32_RV32IMACFD, "fcvt_s_w",(uint64_t) 0xd0000053,(uint64_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_S_W\n");cp.code()+="etiss_coverage_count(1, 110);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4773);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 4772);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = fcvt_s((etiss_uint32)(*((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL]), 2ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(8, 4756, 4755, 4752, 4751, 4750, 4748, 4753, 4754);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 4771, 4759, 4758, 4770, 4769, 4767);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_s_w"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fnmadd_s_rd_rm_rs1_rs2_rs3
static InstructionDefinition fnmadd_s_rd_rm_rs1_rs2_rs3(ISA32_RV32IMACFD, "fnmadd_s",(uint64_t) 0x00004f,(uint64_t) 0x600007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FNMADD_S\n");cp.code()+="etiss_coverage_count(1, 92);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3659);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 3643);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 3606, 3605, 3604, 3603);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 3612, 3611, 3610, 3609);\n";cp.code()+="etiss_uint32 frs3 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs3)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 3618, 3617, 3616, 3615);\n";cp.code()+="etiss_uint32 res = fmadd_s(frs1, frs2, frs3, 2ULL, RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(8, 3627, 3626, 3620, 3621, 3622, 3623, 3625, 3624);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 3642, 3630, 3629, 3641, 3640, 3638);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 3646, 3645);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 3658, 3647, 3657, 3651, 3648, 3652, 3655, 3653, 3656);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 rs3=0;static BitArrayRange R_rs3_0(31, 27);rs3+=R_rs3_0.read(ba)<< 0;std::stringstream ss;ss<< "fnmadd_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+" | rs3="+std::to_string(rs3)+"]");return ss.str();})
fmul_s_rd_rm_rs1_rs2
static InstructionDefinition fmul_s_rd_rm_rs1_rs2(ISA32_RV32IMACFD, "fmul_s",(uint64_t) 0x10000053,(uint64_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMUL_S\n");cp.code()+="etiss_coverage_count(1, 96);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3943);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 3927);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 3898, 3897, 3896, 3895);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 3904, 3903, 3902, 3901);\n";cp.code()+="etiss_uint32 res = fmul_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(6, 3911, 3910, 3906, 3907, 3909, 3908);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 3926, 3914, 3913, 3925, 3924, 3922);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 3930, 3929);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 3942, 3931, 3941, 3935, 3932, 3936, 3939, 3937, 3940);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fmul_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fadd_s_rd_rm_rs1_rs2
static InstructionDefinition fadd_s_rd_rm_rs1_rs2(ISA32_RV32IMACFD, "fadd_s",(uint64_t) 0x000053,(uint64_t) 0xfe00007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FADD_S\n");cp.code()+="etiss_coverage_count(1, 94);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3807);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 3791);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 3762, 3761, 3760, 3759);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 3768, 3767, 3766, 3765);\n";cp.code()+="etiss_uint32 res = fadd_s(frs1, frs2, RV32IMACFD_get_rm(cpu, system, plugin_pointers, "+std::to_string(rm)+"ULL));\n";cp.code()+="etiss_coverage_count(6, 3775, 3774, 3770, 3771, 3773, 3772);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 3790, 3778, 3777, 3789, 3788, 3786);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 3794, 3793);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 3806, 3795, 3805, 3799, 3796, 3800, 3803, 3801, 3804);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fadd_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fmax_s_rd_rs1_rs2
static InstructionDefinition fmax_s_rd_rs1_rs2(ISA32_RV32IMACFD, "fmax_s",(uint64_t) 0x28001053,(uint64_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FMAX_S\n");cp.code()+="etiss_coverage_count(1, 103);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4376);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 4360);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4332, 4331, 4330, 4329);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4338, 4337, 4336, 4335);\n";cp.code()+="etiss_uint32 res = fsel_s(frs1, frs2, 1ULL);\n";cp.code()+="etiss_coverage_count(5, 4344, 4343, 4340, 4341, 4342);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 4359, 4347, 4346, 4358, 4357, 4355);\n";cp.code()+="} // block\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 4363, 4362);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 4375, 4364, 4374, 4368, 4365, 4369, 4372, 4370, 4373);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fmax_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fsgnjn_s_rd_rs1_rs2
static InstructionDefinition fsgnjn_s_rd_rs1_rs2(ISA32_RV32IMACFD, "fsgnjn_s",(uint64_t) 0x20001053,(uint64_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSGNJN_S\n");cp.code()+="etiss_coverage_count(1, 100);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4189);\n";cp.code()+="{ // block\n";{ cp.code()+="etiss_coverage_count(1, 4188);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4156, 4155, 4154, 4153);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4162, 4161, 4160, 4159);\n";cp.code()+="etiss_uint32 res = (((~((((frs2) >> (31ULL)) & 0x1ULL))) << 31) | (((frs1) & 0x7fffffffULL)));\n";cp.code()+="etiss_coverage_count(11, 4174, 4173, 4168, 4167, 4164, 4165, 4166, 4172, 4169, 4170, 4171);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 4187, 4177, 4176, 4186, 4185, 4183);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "fsgnjn_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fcvt_wu_s_rd_rm_rs1
static InstructionDefinition fcvt_wu_s_rd_rm_rs1(ISA32_RV32IMACFD, "fcvt_wu_s",(uint64_t) 0xc0100053,(uint64_t) 0xfff0007f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCVT_WU_S\n");cp.code()+="etiss_coverage_count(1, 105);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4495);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = 0LL;\n";cp.code()+="etiss_coverage_count(2, 4437, 4436);\n";{ cp.code()+="etiss_coverage_count(1, 4462);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4455, 4454, 4453, 4452);\n";cp.code()+="res = fcvt_s(frs1, 1ULL, "+std::to_string(rm)+"ULL);\n";cp.code()+="etiss_coverage_count(6, 4461, 4456, 4460, 4457, 4458, 4459);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 4463);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 4469, 4466, 4464, 4467, 4468);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = (etiss_uint32)((etiss_int32)(res));\n";cp.code()+="etiss_coverage_count(7, 4479, 4474, 4473, 4471, 4478, 4476, 4475);\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 4482, 4481);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 4494, 4483, 4493, 4487, 4484, 4488, 4491, 4489, 4492);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rm=0;static BitArrayRange R_rm_0(14, 12);rm+=R_rm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fcvt_wu_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rm="+std::to_string(rm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
fsw_imm_rs1_rs2
static InstructionDefinition fsw_imm_rs1_rs2(ISA32_RV32IMACFD, "fsw",(uint64_t) 0x002027,(uint64_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FSW\n");cp.code()+="etiss_coverage_count(1, 89);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3437);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 offs = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 3424, 3423, 3419, 3418, 3416, 3422, 3420);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(8, 3436, 3430, 3428, 3426, 3427, 3435, 3433, 3432);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//FSW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 imm=0;static BitArrayRange R_imm_0(11, 7);imm+=R_imm_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;static BitArrayRange R_imm_5(31, 25);imm+=R_imm_5.read(ba)<< 5;std::stringstream ss;ss<< "fsw"<< " # "<< ba<<(" [imm="+std::to_string(imm)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
flt_s_rd_rs1_rs2
static InstructionDefinition flt_s_rd_rs1_rs2(ISA32_RV32IMACFD, "flt_s",(uint64_t) 0xa0001053,(uint64_t) 0xfe00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FLT_S\n");cp.code()+="etiss_coverage_count(1, 107);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4627);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = 0LL;\n";cp.code()+="etiss_coverage_count(2, 4564, 4563);\n";{ cp.code()+="etiss_coverage_count(1, 4597);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 frs1 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4584, 4583, 4582, 4581);\n";cp.code()+="etiss_uint32 frs2 = unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(4, 4590, 4589, 4588, 4587);\n";cp.code()+="res = fcmp_s(frs1, frs2, 2ULL);\n";cp.code()+="etiss_coverage_count(6, 4596, 4591, 4595, 4592, 4593, 4594);\n";cp.code()+="} // block\n";} cp.code()+="etiss_coverage_count(1, 4598);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 4604, 4601, 4599, 4602, 4603);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 4611, 4609, 4608, 4606, 4610);\n";} cp.code()+="etiss_uint32 flags = fget_flags();\n";cp.code()+="etiss_coverage_count(2, 4614, 4613);\n";cp.code()+="((RV32IMACFD*)cpu)->FCSR = (((RV32IMACFD*)cpu)->FCSR & -32LL) | (flags & 31ULL);\n";cp.code()+="etiss_coverage_count(9, 4626, 4615, 4625, 4619, 4616, 4620, 4623, 4621, 4624);\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(24, 20);rs2+=R_rs2_0.read(ba)<< 0;std::stringstream ss;ss<< "flt_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | rs2="+std::to_string(rs2)+"]");return ss.str();})
fclass_s_rd_rs1
static InstructionDefinition fclass_s_rd_rs1(ISA32_RV32IMACFD, "fclass_s",(uint64_t) 0xe0001053,(uint64_t) 0xfff0707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FCLASS_S\n");cp.code()+="etiss_coverage_count(1, 109);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4728);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 res = 0LL;\n";cp.code()+="etiss_coverage_count(2, 4696, 4695);\n";cp.code()+="res = fclass_s(unbox_s(((RV32IMACFD*)cpu)->F["+std::to_string(rs1)+"ULL]));\n";cp.code()+="etiss_coverage_count(6, 4713, 4707, 4712, 4711, 4710, 4709);\n";cp.code()+="etiss_coverage_count(1, 4714);\n";if((rd % 32ULL) !=0LL) { cp.code()+="etiss_coverage_count(5, 4720, 4717, 4715, 4718, 4719);\n";cp.code()+="*((RV32IMACFD*)cpu)->X["+std::to_string(rd % 32ULL)+"ULL] = res;\n";cp.code()+="etiss_coverage_count(5, 4727, 4725, 4724, 4722, 4726);\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;std::stringstream ss;ss<< "fclass_s"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
flw_rd_rs1_imm
static InstructionDefinition flw_rd_rs1_imm(ISA32_RV32IMACFD, "flw",(uint64_t) 0x002007,(uint64_t) 0x00707f, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//FLW\n");cp.code()+="etiss_coverage_count(1, 88);\n";{ cp.code()+="etiss_coverage_count(1, 1189);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string((etiss_uint32)((ic.current_address_+4)))+"ULL;\n";cp.code()+="etiss_coverage_count(7, 1188, 1181, 1187, 1184, 1182, 1183, 1185);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 3413);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 offs = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1 % 32ULL)+"ULL] + "+std::to_string(((etiss_int16)(((etiss_int16) imm)<<(4)) > >(4)))+"LL;\n";cp.code()+="etiss_coverage_count(7, 3377, 3376, 3372, 3371, 3369, 3375, 3373);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";cp.code()+="etiss_coverage_count(6, 3387, 3386, 3384, 3382, 3380, 3381);\n";{ cp.code()+="etiss_coverage_count(1, 3412);\n";cp.code()+="{ // block\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | (etiss_uint64)(res);\n";cp.code()+="etiss_coverage_count(6, 3411, 3399, 3398, 3410, 3409, 3407);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//FLW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(19, 15);rs1+=R_rs1_0.read(ba)<< 0;etiss_uint16 imm=0;static BitArrayRange R_imm_0(31, 20);imm+=R_imm_0.read(ba)<< 0;std::stringstream ss;ss<< "flw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | rs1="+std::to_string(rs1)+" | imm="+std::to_string(imm)+"]");return ss.str();})
etiss_int16
int16_t etiss_int16
Definition types.h:51
etiss_uint32
uint32_t etiss_uint32
Definition types.h:55
etiss_uint8
uint8_t etiss_uint8
Definition types.h:49
etiss_uint16
uint16_t etiss_uint16
Definition types.h:52
etiss::CodePart
Contains a small code snipped.
Definition CodePart.h:348
etiss::CodePart::APPENDEDRETURNINGREQUIRED
@ APPENDEDRETURNINGREQUIRED
Definition CodePart.h:364
etiss::CodePart::code
std::string & code()
Definition CodePart.h:378
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition CodePart.h:376
etiss::CodeSet
A set of CodeParts.
Definition CodePart.h:399
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition CodePart.h:412
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition CodePart.h:184
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition Instruction.h:162
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition Instruction.cpp:171
etiss::instr::BitArray
stores a bit vector
Definition Instruction.h:114
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition Instruction.h:290
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition Instruction.h:319
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition Instruction.h:346
etiss
forwards: include/jit/*
Definition Benchmark.h:17
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