ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
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RV32IMACFD_RV32FCInstr.cpp
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1
8#include "RV32IMACFDArch.h"
9#include "RV32IMACFDFuncs.h"
10
11using namespace etiss;
12using namespace etiss::instr;
13
14
15// CFLW ------------------------------------------------------------------------
16static InstructionDefinition cflw_rd_uimm_rs1 (
17 ISA16_RV32IMACFD,
18 "cflw",
19 (uint16_t) 0x6000,
20 (uint16_t) 0xe003,
21 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22 {
23
24// -----------------------------------------------------------------------------
25
26// -----------------------------------------------------------------------------
27
28// -----------------------------------------------------------------------------
29etiss_uint8 rd = 0;
30static BitArrayRange R_rd_0(4, 2);
31rd += R_rd_0.read(ba) << 0;
32etiss_uint8 uimm = 0;
33static BitArrayRange R_uimm_6(5, 5);
34uimm += R_uimm_6.read(ba) << 6;
35static BitArrayRange R_uimm_2(6, 6);
36uimm += R_uimm_2.read(ba) << 2;
37etiss_uint8 rs1 = 0;
38static BitArrayRange R_rs1_0(9, 7);
39rs1 += R_rs1_0.read(ba) << 0;
40static BitArrayRange R_uimm_3(12, 10);
41uimm += R_uimm_3.read(ba) << 3;
42
43// -----------------------------------------------------------------------------
44
45 {
46 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
47
48 cp.code() = std::string("//CFLW\n");
49
50// -----------------------------------------------------------------------------
51cp.code() += "etiss_coverage_count(1, 114);\n";
52{ // block
53cp.code() += "etiss_coverage_count(1, 1169);\n";
54cp.code() += "{ // block\n";
55cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
56cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
57cp.code() += "} // block\n";
58} // block
59{ // block
60cp.code() += "etiss_coverage_count(1, 4951);\n";
61cp.code() += "{ // block\n";
62cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
63cp.code() += "etiss_coverage_count(7, 4916, 4915, 4913, 4912, 4910, 4911, 4914);\n";
64cp.code() += "etiss_uint32 mem_val_0;\n";
65cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
66cp.code() += "if (cpu->exception) { // conditional\n";
67{ // procedure
68cp.code() += "{ // procedure\n";
69cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
70cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
71cp.code() += "} // procedure\n";
72} // procedure
73cp.code() += "} // conditional\n";
74cp.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
75cp.code() += "etiss_coverage_count(4, 4923, 4922, 4920, 4919);\n";
76{ // block
77cp.code() += "etiss_coverage_count(1, 4950);\n";
78cp.code() += "{ // block\n";
79cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd + 8ULL) + "ULL] = -4294967296LL | res;\n";
80cp.code() += "etiss_coverage_count(7, 4949, 4939, 4938, 4936, 4937, 4948, 4947);\n";
81cp.code() += "} // block\n";
82} // block
83cp.code() += "} // block\n";
84} // block
85cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
86cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
87// -----------------------------------------------------------------------------
88 cp.getAffectedRegisters().add("instructionPointer", 32);
89 }
90 {
91 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
92
93 cp.code() = std::string("//CFLW\n");
94
95// -----------------------------------------------------------------------------
96cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
97// -----------------------------------------------------------------------------
98 }
99
100 return true;
101 },
102 0,
103 [] (BitArray & ba, Instruction & instr)
104 {
105// -----------------------------------------------------------------------------
106etiss_uint8 rd = 0;
107static BitArrayRange R_rd_0(4, 2);
108rd += R_rd_0.read(ba) << 0;
109etiss_uint8 uimm = 0;
110static BitArrayRange R_uimm_6(5, 5);
111uimm += R_uimm_6.read(ba) << 6;
112static BitArrayRange R_uimm_2(6, 6);
113uimm += R_uimm_2.read(ba) << 2;
114etiss_uint8 rs1 = 0;
115static BitArrayRange R_rs1_0(9, 7);
116rs1 += R_rs1_0.read(ba) << 0;
117static BitArrayRange R_uimm_3(12, 10);
118uimm += R_uimm_3.read(ba) << 3;
119
120// -----------------------------------------------------------------------------
121
122 std::stringstream ss;
123// -----------------------------------------------------------------------------
124ss << "cflw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | uimm=" + std::to_string(uimm) + " | rs1=" + std::to_string(rs1) + "]");
125// -----------------------------------------------------------------------------
126 return ss.str();
127 }
128);
129
130// CFSW ------------------------------------------------------------------------
131static InstructionDefinition cfsw_rs2_uimm_rs1 (
132 ISA16_RV32IMACFD,
133 "cfsw",
134 (uint16_t) 0xe000,
135 (uint16_t) 0xe003,
136 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
137 {
138
139// -----------------------------------------------------------------------------
140
141// -----------------------------------------------------------------------------
142
143// -----------------------------------------------------------------------------
144etiss_uint8 rs2 = 0;
145static BitArrayRange R_rs2_0(4, 2);
146rs2 += R_rs2_0.read(ba) << 0;
147etiss_uint8 uimm = 0;
148static BitArrayRange R_uimm_6(5, 5);
149uimm += R_uimm_6.read(ba) << 6;
150static BitArrayRange R_uimm_2(6, 6);
151uimm += R_uimm_2.read(ba) << 2;
152etiss_uint8 rs1 = 0;
153static BitArrayRange R_rs1_0(9, 7);
154rs1 += R_rs1_0.read(ba) << 0;
155static BitArrayRange R_uimm_3(12, 10);
156uimm += R_uimm_3.read(ba) << 3;
157
158// -----------------------------------------------------------------------------
159
160 {
161 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
162
163 cp.code() = std::string("//CFSW\n");
164
165// -----------------------------------------------------------------------------
166cp.code() += "etiss_coverage_count(1, 115);\n";
167{ // block
168cp.code() += "etiss_coverage_count(1, 1169);\n";
169cp.code() += "{ // block\n";
170cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
171cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
172cp.code() += "} // block\n";
173} // block
174{ // block
175cp.code() += "etiss_coverage_count(1, 4972);\n";
176cp.code() += "{ // block\n";
177cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
178cp.code() += "etiss_coverage_count(7, 4960, 4959, 4957, 4956, 4954, 4955, 4958);\n";
179cp.code() += "etiss_uint32 mem_val_0;\n";
180cp.code() += "mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2 + 8ULL) + "ULL]);\n";
181cp.code() += "etiss_coverage_count(8, 4971, 4963, 4962, 4970, 4968, 4967, 4965, 4966);\n";
182cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
183cp.code() += "if (cpu->exception) { // conditional\n";
184{ // procedure
185cp.code() += "{ // procedure\n";
186cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
187cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
188cp.code() += "} // procedure\n";
189} // procedure
190cp.code() += "} // conditional\n";
191cp.code() += "} // block\n";
192} // block
193cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
194cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
195// -----------------------------------------------------------------------------
196 cp.getAffectedRegisters().add("instructionPointer", 32);
197 }
198 {
199 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
200
201 cp.code() = std::string("//CFSW\n");
202
203// -----------------------------------------------------------------------------
204cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
205// -----------------------------------------------------------------------------
206 }
207
208 return true;
209 },
210 0,
211 [] (BitArray & ba, Instruction & instr)
212 {
213// -----------------------------------------------------------------------------
214etiss_uint8 rs2 = 0;
215static BitArrayRange R_rs2_0(4, 2);
216rs2 += R_rs2_0.read(ba) << 0;
217etiss_uint8 uimm = 0;
218static BitArrayRange R_uimm_6(5, 5);
219uimm += R_uimm_6.read(ba) << 6;
220static BitArrayRange R_uimm_2(6, 6);
221uimm += R_uimm_2.read(ba) << 2;
222etiss_uint8 rs1 = 0;
223static BitArrayRange R_rs1_0(9, 7);
224rs1 += R_rs1_0.read(ba) << 0;
225static BitArrayRange R_uimm_3(12, 10);
226uimm += R_uimm_3.read(ba) << 3;
227
228// -----------------------------------------------------------------------------
229
230 std::stringstream ss;
231// -----------------------------------------------------------------------------
232ss << "cfsw" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | uimm=" + std::to_string(uimm) + " | rs1=" + std::to_string(rs1) + "]");
233// -----------------------------------------------------------------------------
234 return ss.str();
235 }
236);
237
238// CFLWSP ----------------------------------------------------------------------
239static InstructionDefinition cflwsp_uimm_rd (
240 ISA16_RV32IMACFD,
241 "cflwsp",
242 (uint16_t) 0x6002,
243 (uint16_t) 0xe003,
244 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
245 {
246
247// -----------------------------------------------------------------------------
248
249// -----------------------------------------------------------------------------
250
251// -----------------------------------------------------------------------------
252etiss_uint8 uimm = 0;
253static BitArrayRange R_uimm_6(3, 2);
254uimm += R_uimm_6.read(ba) << 6;
255static BitArrayRange R_uimm_2(6, 4);
256uimm += R_uimm_2.read(ba) << 2;
257etiss_uint8 rd = 0;
258static BitArrayRange R_rd_0(11, 7);
259rd += R_rd_0.read(ba) << 0;
260static BitArrayRange R_uimm_5(12, 12);
261uimm += R_uimm_5.read(ba) << 5;
262
263// -----------------------------------------------------------------------------
264
265 {
266 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
267
268 cp.code() = std::string("//CFLWSP\n");
269
270// -----------------------------------------------------------------------------
271cp.code() += "etiss_coverage_count(1, 116);\n";
272{ // block
273cp.code() += "etiss_coverage_count(1, 1169);\n";
274cp.code() += "{ // block\n";
275cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
276cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
277cp.code() += "} // block\n";
278} // block
279{ // block
280cp.code() += "etiss_coverage_count(1, 5010);\n";
281cp.code() += "{ // block\n";
282cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
283cp.code() += "etiss_coverage_count(5, 4979, 4978, 4976, 4975, 4977);\n";
284cp.code() += "etiss_uint32 mem_val_0;\n";
285cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
286cp.code() += "if (cpu->exception) { // conditional\n";
287{ // procedure
288cp.code() += "{ // procedure\n";
289cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
290cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
291cp.code() += "} // procedure\n";
292} // procedure
293cp.code() += "} // conditional\n";
294cp.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
295cp.code() += "etiss_coverage_count(4, 4986, 4985, 4983, 4982);\n";
296{ // block
297cp.code() += "etiss_coverage_count(1, 5009);\n";
298cp.code() += "{ // block\n";
299cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | res;\n";
300cp.code() += "etiss_coverage_count(5, 5008, 4998, 4997, 5007, 5006);\n";
301cp.code() += "} // block\n";
302} // block
303cp.code() += "} // block\n";
304} // block
305cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
306cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
307// -----------------------------------------------------------------------------
308 cp.getAffectedRegisters().add("instructionPointer", 32);
309 }
310 {
311 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
312
313 cp.code() = std::string("//CFLWSP\n");
314
315// -----------------------------------------------------------------------------
316cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
317// -----------------------------------------------------------------------------
318 }
319
320 return true;
321 },
322 0,
323 [] (BitArray & ba, Instruction & instr)
324 {
325// -----------------------------------------------------------------------------
326etiss_uint8 uimm = 0;
327static BitArrayRange R_uimm_6(3, 2);
328uimm += R_uimm_6.read(ba) << 6;
329static BitArrayRange R_uimm_2(6, 4);
330uimm += R_uimm_2.read(ba) << 2;
331etiss_uint8 rd = 0;
332static BitArrayRange R_rd_0(11, 7);
333rd += R_rd_0.read(ba) << 0;
334static BitArrayRange R_uimm_5(12, 12);
335uimm += R_uimm_5.read(ba) << 5;
336
337// -----------------------------------------------------------------------------
338
339 std::stringstream ss;
340// -----------------------------------------------------------------------------
341ss << "cflwsp" << " # " << ba << (" [uimm=" + std::to_string(uimm) + " | rd=" + std::to_string(rd) + "]");
342// -----------------------------------------------------------------------------
343 return ss.str();
344 }
345);
346
347// CFSWSP ----------------------------------------------------------------------
348static InstructionDefinition cfswsp_rs2_uimm (
349 ISA16_RV32IMACFD,
350 "cfswsp",
351 (uint16_t) 0xe002,
352 (uint16_t) 0xe003,
353 [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
354 {
355
356// -----------------------------------------------------------------------------
357
358// -----------------------------------------------------------------------------
359
360// -----------------------------------------------------------------------------
361etiss_uint8 rs2 = 0;
362static BitArrayRange R_rs2_0(6, 2);
363rs2 += R_rs2_0.read(ba) << 0;
364etiss_uint8 uimm = 0;
365static BitArrayRange R_uimm_6(8, 7);
366uimm += R_uimm_6.read(ba) << 6;
367static BitArrayRange R_uimm_2(12, 9);
368uimm += R_uimm_2.read(ba) << 2;
369
370// -----------------------------------------------------------------------------
371
372 {
373 CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
374
375 cp.code() = std::string("//CFSWSP\n");
376
377// -----------------------------------------------------------------------------
378cp.code() += "etiss_coverage_count(1, 117);\n";
379{ // block
380cp.code() += "etiss_coverage_count(1, 1169);\n";
381cp.code() += "{ // block\n";
382cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
383cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
384cp.code() += "} // block\n";
385} // block
386{ // block
387cp.code() += "etiss_coverage_count(1, 5027);\n";
388cp.code() += "{ // block\n";
389cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
390cp.code() += "etiss_coverage_count(5, 5017, 5016, 5014, 5013, 5015);\n";
391cp.code() += "etiss_uint32 mem_val_0;\n";
392cp.code() += "mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
393cp.code() += "etiss_coverage_count(6, 5026, 5020, 5019, 5025, 5023, 5022);\n";
394cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
395cp.code() += "if (cpu->exception) { // conditional\n";
396{ // procedure
397cp.code() += "{ // procedure\n";
398cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
399cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
400cp.code() += "} // procedure\n";
401} // procedure
402cp.code() += "} // conditional\n";
403cp.code() += "} // block\n";
404} // block
405cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
406cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
407// -----------------------------------------------------------------------------
408 cp.getAffectedRegisters().add("instructionPointer", 32);
409 }
410 {
411 CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
412
413 cp.code() = std::string("//CFSWSP\n");
414
415// -----------------------------------------------------------------------------
416cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
417// -----------------------------------------------------------------------------
418 }
419
420 return true;
421 },
422 0,
423 [] (BitArray & ba, Instruction & instr)
424 {
425// -----------------------------------------------------------------------------
426etiss_uint8 rs2 = 0;
427static BitArrayRange R_rs2_0(6, 2);
428rs2 += R_rs2_0.read(ba) << 0;
429etiss_uint8 uimm = 0;
430static BitArrayRange R_uimm_6(8, 7);
431uimm += R_uimm_6.read(ba) << 6;
432static BitArrayRange R_uimm_2(12, 9);
433uimm += R_uimm_2.read(ba) << 2;
434
435// -----------------------------------------------------------------------------
436
437 std::stringstream ss;
438// -----------------------------------------------------------------------------
439ss << "cfswsp" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | uimm=" + std::to_string(uimm) + "]");
440// -----------------------------------------------------------------------------
441 return ss.str();
442 }
443);
ISA16_RV32IMACFD
etiss::instr::InstructionGroup ISA16_RV32IMACFD("ISA16_RV32IMACFD", 16)
cfswsp_rs2_uimm
static InstructionDefinition cfswsp_rs2_uimm(ISA16_RV32IMACFD, "cfswsp",(uint16_t) 0xe002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(8, 7);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(12, 9);uimm+=R_uimm_2.read(ba)<< 2;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CFSWSP\n");cp.code()+="etiss_coverage_count(1, 117);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5027);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 5017, 5016, 5014, 5013, 5015);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(6, 5026, 5020, 5019, 5025, 5023, 5022);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CFSWSP\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(8, 7);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(12, 9);uimm+=R_uimm_2.read(ba)<< 2;std::stringstream ss;ss<< "cfswsp"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | uimm="+std::to_string(uimm)+"]");return ss.str();})
cfsw_rs2_uimm_rs1
static InstructionDefinition cfsw_rs2_uimm_rs1(ISA16_RV32IMACFD, "cfsw",(uint16_t) 0xe000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(5, 5);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 6);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CFSW\n");cp.code()+="etiss_coverage_count(1, 115);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4972);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 offs = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(7, 4960, 4959, 4957, 4956, 4954, 4955, 4958);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F["+std::to_string(rs2+8ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(8, 4971, 4963, 4962, 4970, 4968, 4967, 4965, 4966);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CFSW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(5, 5);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 6);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;std::stringstream ss;ss<< "cfsw"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | uimm="+std::to_string(uimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
cflw_rd_uimm_rs1
static InstructionDefinition cflw_rd_uimm_rs1(ISA16_RV32IMACFD, "cflw",(uint16_t) 0x6000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(5, 5);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 6);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CFLW\n");cp.code()+="etiss_coverage_count(1, 114);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4951);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 offs = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(7, 4916, 4915, 4913, 4912, 4910, 4911, 4914);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 4923, 4922, 4920, 4919);\n";{ cp.code()+="etiss_coverage_count(1, 4950);\n";cp.code()+="{ // block\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd+8ULL)+"ULL] = -4294967296LL | res;\n";cp.code()+="etiss_coverage_count(7, 4949, 4939, 4938, 4936, 4937, 4948, 4947);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CFLW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(5, 5);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 6);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;std::stringstream ss;ss<< "cflw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | uimm="+std::to_string(uimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
cflwsp_uimm_rd
static InstructionDefinition cflwsp_uimm_rd(ISA16_RV32IMACFD, "cflwsp",(uint16_t) 0x6002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(3, 2);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 4);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_uimm_5(12, 12);uimm+=R_uimm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CFLWSP\n");cp.code()+="etiss_coverage_count(1, 116);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5010);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 4979, 4978, 4976, 4975, 4977);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 4986, 4985, 4983, 4982);\n";{ cp.code()+="etiss_coverage_count(1, 5009);\n";cp.code()+="{ // block\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | res;\n";cp.code()+="etiss_coverage_count(5, 5008, 4998, 4997, 5007, 5006);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CFLWSP\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(3, 2);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 4);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_uimm_5(12, 12);uimm+=R_uimm_5.read(ba)<< 5;std::stringstream ss;ss<< "cflwsp"<< " # "<< ba<<(" [uimm="+std::to_string(uimm)+" | rd="+std::to_string(rd)+"]");return ss.str();})
etiss_uint8
uint8_t etiss_uint8
Definition types.h:87
etiss::CodePart
Contains a small code snipped.
Definition CodePart.h:386
etiss::CodePart::APPENDEDRETURNINGREQUIRED
@ APPENDEDRETURNINGREQUIRED
Definition CodePart.h:402
etiss::CodePart::code
std::string & code()
Definition CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition Benchmark.h:53
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