ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV32IMACFD_RV32FCInstr.cpp
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1 
8 #include "RV32IMACFDArch.h"
9 #include "RV32IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // CFLW ------------------------------------------------------------------------
16 static InstructionDefinition cflw_rd_uimm_rs1 (
17  ISA16_RV32IMACFD,
18  "cflw",
19  (uint16_t) 0x6000,
20  (uint16_t) 0xe003,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 etiss_uint8 rd = 0;
30 static BitArrayRange R_rd_0(4, 2);
31 rd += R_rd_0.read(ba) << 0;
32 etiss_uint8 uimm = 0;
33 static BitArrayRange R_uimm_6(5, 5);
34 uimm += R_uimm_6.read(ba) << 6;
35 static BitArrayRange R_uimm_2(6, 6);
36 uimm += R_uimm_2.read(ba) << 2;
37 etiss_uint8 rs1 = 0;
38 static BitArrayRange R_rs1_0(9, 7);
39 rs1 += R_rs1_0.read(ba) << 0;
40 static BitArrayRange R_uimm_3(12, 10);
41 uimm += R_uimm_3.read(ba) << 3;
42 
43 // -----------------------------------------------------------------------------
44 
45  {
46  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
47 
48  cp.code() = std::string("//CFLW\n");
49 
50 // -----------------------------------------------------------------------------
51 cp.code() += "etiss_coverage_count(1, 114);\n";
52 { // block
53 cp.code() += "etiss_coverage_count(1, 1169);\n";
54 cp.code() += "{ // block\n";
55 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
56 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
57 cp.code() += "} // block\n";
58 } // block
59 { // block
60 cp.code() += "etiss_coverage_count(1, 4951);\n";
61 cp.code() += "{ // block\n";
62 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
63 cp.code() += "etiss_coverage_count(7, 4916, 4915, 4913, 4912, 4910, 4911, 4914);\n";
64 cp.code() += "etiss_uint32 mem_val_0;\n";
65 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
66 cp.code() += "if (cpu->exception) { // conditional\n";
67 { // procedure
68 cp.code() += "{ // procedure\n";
69 cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
70 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
71 cp.code() += "} // procedure\n";
72 } // procedure
73 cp.code() += "} // conditional\n";
74 cp.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
75 cp.code() += "etiss_coverage_count(4, 4923, 4922, 4920, 4919);\n";
76 { // block
77 cp.code() += "etiss_coverage_count(1, 4950);\n";
78 cp.code() += "{ // block\n";
79 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd + 8ULL) + "ULL] = -4294967296LL | res;\n";
80 cp.code() += "etiss_coverage_count(7, 4949, 4939, 4938, 4936, 4937, 4948, 4947);\n";
81 cp.code() += "} // block\n";
82 } // block
83 cp.code() += "} // block\n";
84 } // block
85 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
86 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
87 // -----------------------------------------------------------------------------
88  cp.getAffectedRegisters().add("instructionPointer", 32);
89  }
90  {
91  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
92 
93  cp.code() = std::string("//CFLW\n");
94 
95 // -----------------------------------------------------------------------------
96 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
97 // -----------------------------------------------------------------------------
98  }
99 
100  return true;
101  },
102  0,
103  [] (BitArray & ba, Instruction & instr)
104  {
105 // -----------------------------------------------------------------------------
106 etiss_uint8 rd = 0;
107 static BitArrayRange R_rd_0(4, 2);
108 rd += R_rd_0.read(ba) << 0;
109 etiss_uint8 uimm = 0;
110 static BitArrayRange R_uimm_6(5, 5);
111 uimm += R_uimm_6.read(ba) << 6;
112 static BitArrayRange R_uimm_2(6, 6);
113 uimm += R_uimm_2.read(ba) << 2;
114 etiss_uint8 rs1 = 0;
115 static BitArrayRange R_rs1_0(9, 7);
116 rs1 += R_rs1_0.read(ba) << 0;
117 static BitArrayRange R_uimm_3(12, 10);
118 uimm += R_uimm_3.read(ba) << 3;
119 
120 // -----------------------------------------------------------------------------
121 
122  std::stringstream ss;
123 // -----------------------------------------------------------------------------
124 ss << "cflw" << " # " << ba << (" [rd=" + std::to_string(rd) + " | uimm=" + std::to_string(uimm) + " | rs1=" + std::to_string(rs1) + "]");
125 // -----------------------------------------------------------------------------
126  return ss.str();
127  }
128 );
129 
130 // CFSW ------------------------------------------------------------------------
131 static InstructionDefinition cfsw_rs2_uimm_rs1 (
132  ISA16_RV32IMACFD,
133  "cfsw",
134  (uint16_t) 0xe000,
135  (uint16_t) 0xe003,
136  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
137  {
138 
139 // -----------------------------------------------------------------------------
140 
141 // -----------------------------------------------------------------------------
142 
143 // -----------------------------------------------------------------------------
144 etiss_uint8 rs2 = 0;
145 static BitArrayRange R_rs2_0(4, 2);
146 rs2 += R_rs2_0.read(ba) << 0;
147 etiss_uint8 uimm = 0;
148 static BitArrayRange R_uimm_6(5, 5);
149 uimm += R_uimm_6.read(ba) << 6;
150 static BitArrayRange R_uimm_2(6, 6);
151 uimm += R_uimm_2.read(ba) << 2;
152 etiss_uint8 rs1 = 0;
153 static BitArrayRange R_rs1_0(9, 7);
154 rs1 += R_rs1_0.read(ba) << 0;
155 static BitArrayRange R_uimm_3(12, 10);
156 uimm += R_uimm_3.read(ba) << 3;
157 
158 // -----------------------------------------------------------------------------
159 
160  {
161  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
162 
163  cp.code() = std::string("//CFSW\n");
164 
165 // -----------------------------------------------------------------------------
166 cp.code() += "etiss_coverage_count(1, 115);\n";
167 { // block
168 cp.code() += "etiss_coverage_count(1, 1169);\n";
169 cp.code() += "{ // block\n";
170 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
171 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
172 cp.code() += "} // block\n";
173 } // block
174 { // block
175 cp.code() += "etiss_coverage_count(1, 4972);\n";
176 cp.code() += "{ // block\n";
177 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
178 cp.code() += "etiss_coverage_count(7, 4960, 4959, 4957, 4956, 4954, 4955, 4958);\n";
179 cp.code() += "etiss_uint32 mem_val_0;\n";
180 cp.code() += "mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2 + 8ULL) + "ULL]);\n";
181 cp.code() += "etiss_coverage_count(8, 4971, 4963, 4962, 4970, 4968, 4967, 4965, 4966);\n";
182 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
183 cp.code() += "if (cpu->exception) { // conditional\n";
184 { // procedure
185 cp.code() += "{ // procedure\n";
186 cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
187 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
188 cp.code() += "} // procedure\n";
189 } // procedure
190 cp.code() += "} // conditional\n";
191 cp.code() += "} // block\n";
192 } // block
193 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
194 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
195 // -----------------------------------------------------------------------------
196  cp.getAffectedRegisters().add("instructionPointer", 32);
197  }
198  {
199  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
200 
201  cp.code() = std::string("//CFSW\n");
202 
203 // -----------------------------------------------------------------------------
204 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
205 // -----------------------------------------------------------------------------
206  }
207 
208  return true;
209  },
210  0,
211  [] (BitArray & ba, Instruction & instr)
212  {
213 // -----------------------------------------------------------------------------
214 etiss_uint8 rs2 = 0;
215 static BitArrayRange R_rs2_0(4, 2);
216 rs2 += R_rs2_0.read(ba) << 0;
217 etiss_uint8 uimm = 0;
218 static BitArrayRange R_uimm_6(5, 5);
219 uimm += R_uimm_6.read(ba) << 6;
220 static BitArrayRange R_uimm_2(6, 6);
221 uimm += R_uimm_2.read(ba) << 2;
222 etiss_uint8 rs1 = 0;
223 static BitArrayRange R_rs1_0(9, 7);
224 rs1 += R_rs1_0.read(ba) << 0;
225 static BitArrayRange R_uimm_3(12, 10);
226 uimm += R_uimm_3.read(ba) << 3;
227 
228 // -----------------------------------------------------------------------------
229 
230  std::stringstream ss;
231 // -----------------------------------------------------------------------------
232 ss << "cfsw" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | uimm=" + std::to_string(uimm) + " | rs1=" + std::to_string(rs1) + "]");
233 // -----------------------------------------------------------------------------
234  return ss.str();
235  }
236 );
237 
238 // CFLWSP ----------------------------------------------------------------------
239 static InstructionDefinition cflwsp_uimm_rd (
240  ISA16_RV32IMACFD,
241  "cflwsp",
242  (uint16_t) 0x6002,
243  (uint16_t) 0xe003,
244  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
245  {
246 
247 // -----------------------------------------------------------------------------
248 
249 // -----------------------------------------------------------------------------
250 
251 // -----------------------------------------------------------------------------
252 etiss_uint8 uimm = 0;
253 static BitArrayRange R_uimm_6(3, 2);
254 uimm += R_uimm_6.read(ba) << 6;
255 static BitArrayRange R_uimm_2(6, 4);
256 uimm += R_uimm_2.read(ba) << 2;
257 etiss_uint8 rd = 0;
258 static BitArrayRange R_rd_0(11, 7);
259 rd += R_rd_0.read(ba) << 0;
260 static BitArrayRange R_uimm_5(12, 12);
261 uimm += R_uimm_5.read(ba) << 5;
262 
263 // -----------------------------------------------------------------------------
264 
265  {
266  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
267 
268  cp.code() = std::string("//CFLWSP\n");
269 
270 // -----------------------------------------------------------------------------
271 cp.code() += "etiss_coverage_count(1, 116);\n";
272 { // block
273 cp.code() += "etiss_coverage_count(1, 1169);\n";
274 cp.code() += "{ // block\n";
275 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
276 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
277 cp.code() += "} // block\n";
278 } // block
279 { // block
280 cp.code() += "etiss_coverage_count(1, 5010);\n";
281 cp.code() += "{ // block\n";
282 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
283 cp.code() += "etiss_coverage_count(5, 4979, 4978, 4976, 4975, 4977);\n";
284 cp.code() += "etiss_uint32 mem_val_0;\n";
285 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
286 cp.code() += "if (cpu->exception) { // conditional\n";
287 { // procedure
288 cp.code() += "{ // procedure\n";
289 cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
290 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
291 cp.code() += "} // procedure\n";
292 } // procedure
293 cp.code() += "} // conditional\n";
294 cp.code() += "etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
295 cp.code() += "etiss_coverage_count(4, 4986, 4985, 4983, 4982);\n";
296 { // block
297 cp.code() += "etiss_coverage_count(1, 5009);\n";
298 cp.code() += "{ // block\n";
299 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = -4294967296LL | res;\n";
300 cp.code() += "etiss_coverage_count(5, 5008, 4998, 4997, 5007, 5006);\n";
301 cp.code() += "} // block\n";
302 } // block
303 cp.code() += "} // block\n";
304 } // block
305 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
306 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
307 // -----------------------------------------------------------------------------
308  cp.getAffectedRegisters().add("instructionPointer", 32);
309  }
310  {
311  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
312 
313  cp.code() = std::string("//CFLWSP\n");
314 
315 // -----------------------------------------------------------------------------
316 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
317 // -----------------------------------------------------------------------------
318  }
319 
320  return true;
321  },
322  0,
323  [] (BitArray & ba, Instruction & instr)
324  {
325 // -----------------------------------------------------------------------------
326 etiss_uint8 uimm = 0;
327 static BitArrayRange R_uimm_6(3, 2);
328 uimm += R_uimm_6.read(ba) << 6;
329 static BitArrayRange R_uimm_2(6, 4);
330 uimm += R_uimm_2.read(ba) << 2;
331 etiss_uint8 rd = 0;
332 static BitArrayRange R_rd_0(11, 7);
333 rd += R_rd_0.read(ba) << 0;
334 static BitArrayRange R_uimm_5(12, 12);
335 uimm += R_uimm_5.read(ba) << 5;
336 
337 // -----------------------------------------------------------------------------
338 
339  std::stringstream ss;
340 // -----------------------------------------------------------------------------
341 ss << "cflwsp" << " # " << ba << (" [uimm=" + std::to_string(uimm) + " | rd=" + std::to_string(rd) + "]");
342 // -----------------------------------------------------------------------------
343  return ss.str();
344  }
345 );
346 
347 // CFSWSP ----------------------------------------------------------------------
348 static InstructionDefinition cfswsp_rs2_uimm (
349  ISA16_RV32IMACFD,
350  "cfswsp",
351  (uint16_t) 0xe002,
352  (uint16_t) 0xe003,
353  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
354  {
355 
356 // -----------------------------------------------------------------------------
357 
358 // -----------------------------------------------------------------------------
359 
360 // -----------------------------------------------------------------------------
361 etiss_uint8 rs2 = 0;
362 static BitArrayRange R_rs2_0(6, 2);
363 rs2 += R_rs2_0.read(ba) << 0;
364 etiss_uint8 uimm = 0;
365 static BitArrayRange R_uimm_6(8, 7);
366 uimm += R_uimm_6.read(ba) << 6;
367 static BitArrayRange R_uimm_2(12, 9);
368 uimm += R_uimm_2.read(ba) << 2;
369 
370 // -----------------------------------------------------------------------------
371 
372  {
373  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
374 
375  cp.code() = std::string("//CFSWSP\n");
376 
377 // -----------------------------------------------------------------------------
378 cp.code() += "etiss_coverage_count(1, 117);\n";
379 { // block
380 cp.code() += "etiss_coverage_count(1, 1169);\n";
381 cp.code() += "{ // block\n";
382 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
383 cp.code() += "etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
384 cp.code() += "} // block\n";
385 } // block
386 { // block
387 cp.code() += "etiss_coverage_count(1, 5027);\n";
388 cp.code() += "{ // block\n";
389 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
390 cp.code() += "etiss_coverage_count(5, 5017, 5016, 5014, 5013, 5015);\n";
391 cp.code() += "etiss_uint32 mem_val_0;\n";
392 cp.code() += "mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
393 cp.code() += "etiss_coverage_count(6, 5026, 5020, 5019, 5025, 5023, 5022);\n";
394 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
395 cp.code() += "if (cpu->exception) { // conditional\n";
396 { // procedure
397 cp.code() += "{ // procedure\n";
398 cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
399 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
400 cp.code() += "} // procedure\n";
401 } // procedure
402 cp.code() += "} // conditional\n";
403 cp.code() += "} // block\n";
404 } // block
405 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
406 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
407 // -----------------------------------------------------------------------------
408  cp.getAffectedRegisters().add("instructionPointer", 32);
409  }
410  {
411  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
412 
413  cp.code() = std::string("//CFSWSP\n");
414 
415 // -----------------------------------------------------------------------------
416 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
417 // -----------------------------------------------------------------------------
418  }
419 
420  return true;
421  },
422  0,
423  [] (BitArray & ba, Instruction & instr)
424  {
425 // -----------------------------------------------------------------------------
426 etiss_uint8 rs2 = 0;
427 static BitArrayRange R_rs2_0(6, 2);
428 rs2 += R_rs2_0.read(ba) << 0;
429 etiss_uint8 uimm = 0;
430 static BitArrayRange R_uimm_6(8, 7);
431 uimm += R_uimm_6.read(ba) << 6;
432 static BitArrayRange R_uimm_2(12, 9);
433 uimm += R_uimm_2.read(ba) << 2;
434 
435 // -----------------------------------------------------------------------------
436 
437  std::stringstream ss;
438 // -----------------------------------------------------------------------------
439 ss << "cfswsp" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | uimm=" + std::to_string(uimm) + "]");
440 // -----------------------------------------------------------------------------
441  return ss.str();
442  }
443 );
ISA16_RV32IMACFD
etiss::instr::InstructionGroup ISA16_RV32IMACFD("ISA16_RV32IMACFD", 16)
cfswsp_rs2_uimm
static InstructionDefinition cfswsp_rs2_uimm(ISA16_RV32IMACFD, "cfswsp",(uint16_t) 0xe002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(8, 7);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(12, 9);uimm+=R_uimm_2.read(ba)<< 2;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CFSWSP\n");cp.code()+="etiss_coverage_count(1, 117);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5027);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 5017, 5016, 5014, 5013, 5015);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(6, 5026, 5020, 5019, 5025, 5023, 5022);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CFSWSP\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(8, 7);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(12, 9);uimm+=R_uimm_2.read(ba)<< 2;std::stringstream ss;ss<< "cfswsp"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | uimm="+std::to_string(uimm)+"]");return ss.str();})
cfsw_rs2_uimm_rs1
static InstructionDefinition cfsw_rs2_uimm_rs1(ISA16_RV32IMACFD, "cfsw",(uint16_t) 0xe000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(5, 5);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 6);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CFSW\n");cp.code()+="etiss_coverage_count(1, 115);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4972);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 offs = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(7, 4960, 4959, 4957, 4956, 4954, 4955, 4958);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F["+std::to_string(rs2+8ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(8, 4971, 4963, 4962, 4970, 4968, 4967, 4965, 4966);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CFSW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(5, 5);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 6);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;std::stringstream ss;ss<< "cfsw"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | uimm="+std::to_string(uimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
cflw_rd_uimm_rs1
static InstructionDefinition cflw_rd_uimm_rs1(ISA16_RV32IMACFD, "cflw",(uint16_t) 0x6000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(5, 5);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 6);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CFLW\n");cp.code()+="etiss_coverage_count(1, 114);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4951);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 offs = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(7, 4916, 4915, 4913, 4912, 4910, 4911, 4914);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 4923, 4922, 4920, 4919);\n";{ cp.code()+="etiss_coverage_count(1, 4950);\n";cp.code()+="{ // block\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd+8ULL)+"ULL] = -4294967296LL | res;\n";cp.code()+="etiss_coverage_count(7, 4949, 4939, 4938, 4936, 4937, 4948, 4947);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CFLW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(5, 5);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 6);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;std::stringstream ss;ss<< "cflw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | uimm="+std::to_string(uimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
cflwsp_uimm_rd
static InstructionDefinition cflwsp_uimm_rd(ISA16_RV32IMACFD, "cflwsp",(uint16_t) 0x6002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(3, 2);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 4);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_uimm_5(12, 12);uimm+=R_uimm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CFLWSP\n");cp.code()+="etiss_coverage_count(1, 116);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5010);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 4979, 4978, 4976, 4975, 4977);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 4986, 4985, 4983, 4982);\n";{ cp.code()+="etiss_coverage_count(1, 5009);\n";cp.code()+="{ // block\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | res;\n";cp.code()+="etiss_coverage_count(5, 5008, 4998, 4997, 5007, 5006);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CFLWSP\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(3, 2);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 4);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_uimm_5(12, 12);uimm+=R_uimm_5.read(ba)<< 5;std::stringstream ss;ss<< "cflwsp"<< " # "<< ba<<(" [uimm="+std::to_string(uimm)+" | rd="+std::to_string(rd)+"]");return ss.str();})
uint16_t
static __inline__ uint16_t
Definition: arm_mve.h:315
etiss_uint8
uint8_t etiss_uint8
Definition: types.h:87
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:386
etiss::CodePart::APPENDEDRETURNINGREQUIRED
@ APPENDEDRETURNINGREQUIRED
Definition: CodePart.h:402
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition: Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition: Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
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