32rd += R_rd_0.
read(ba) << 0;
35uimm += R_uimm_6.
read(ba) << 6;
37uimm += R_uimm_2.
read(ba) << 2;
40rs1 += R_rs1_0.
read(ba) << 0;
42uimm += R_uimm_3.
read(ba) << 3;
50 cp.
code() = std::string(
"//CFLW\n");
53cp.
code() +=
"etiss_coverage_count(1, 114);\n";
55cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
56cp.
code() +=
"{ // block\n";
58cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
59cp.
code() +=
"} // block\n";
62cp.
code() +=
"etiss_coverage_count(1, 4951);\n";
63cp.
code() +=
"{ // block\n";
64cp.
code() +=
"etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) +
"ULL] + " + std::to_string(uimm) +
"ULL;\n";
65cp.
code() +=
"etiss_coverage_count(7, 4916, 4915, 4913, 4912, 4910, 4911, 4914);\n";
66cp.
code() +=
"etiss_uint32 mem_val_0;\n";
67cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
68cp.
code() +=
"if (cpu->exception) { // conditional\n";
70cp.
code() +=
"{ // procedure\n";
71cp.
code() +=
"RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
73cp.
code() +=
"} // procedure\n";
75cp.
code() +=
"} // conditional\n";
76cp.
code() +=
"etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
77cp.
code() +=
"etiss_coverage_count(4, 4923, 4922, 4920, 4919);\n";
79cp.
code() +=
"etiss_coverage_count(1, 4950);\n";
80cp.
code() +=
"{ // block\n";
81cp.
code() +=
"((RV32IMACFD*)cpu)->F[" + std::to_string(rd + 8ULL) +
"ULL] = -4294967296LL | res;\n";
82cp.
code() +=
"etiss_coverage_count(7, 4949, 4939, 4938, 4936, 4937, 4948, 4947);\n";
83cp.
code() +=
"} // block\n";
85cp.
code() +=
"} // block\n";
88cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
95 cp.
code() = std::string(
"//CFLW\n");
98cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
110rd += R_rd_0.read(ba) << 0;
113uimm += R_uimm_6.read(ba) << 6;
115uimm += R_uimm_2.read(ba) << 2;
118rs1 += R_rs1_0.read(ba) << 0;
120uimm += R_uimm_3.read(ba) << 3;
124 std::stringstream ss;
126ss <<
"cflw" <<
" # " << ba << (
" [rd=" + std::to_string(rd) +
" | uimm=" + std::to_string(uimm) +
" | rs1=" + std::to_string(rs1) +
"]");
149rs2 += R_rs2_0.
read(ba) << 0;
152uimm += R_uimm_6.
read(ba) << 6;
154uimm += R_uimm_2.
read(ba) << 2;
157rs1 += R_rs1_0.
read(ba) << 0;
159uimm += R_uimm_3.
read(ba) << 3;
167 cp.
code() = std::string(
"//CFSW\n");
170cp.
code() +=
"etiss_coverage_count(1, 115);\n";
172cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
173cp.
code() +=
"{ // block\n";
175cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
176cp.
code() +=
"} // block\n";
179cp.
code() +=
"etiss_coverage_count(1, 4972);\n";
180cp.
code() +=
"{ // block\n";
181cp.
code() +=
"etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) +
"ULL] + " + std::to_string(uimm) +
"ULL;\n";
182cp.
code() +=
"etiss_coverage_count(7, 4960, 4959, 4957, 4956, 4954, 4955, 4958);\n";
183cp.
code() +=
"etiss_uint32 mem_val_0;\n";
184cp.
code() +=
"mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2 + 8ULL) +
"ULL]);\n";
185cp.
code() +=
"etiss_coverage_count(8, 4971, 4963, 4962, 4970, 4968, 4967, 4965, 4966);\n";
186cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
187cp.
code() +=
"if (cpu->exception) { // conditional\n";
189cp.
code() +=
"{ // procedure\n";
190cp.
code() +=
"RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
192cp.
code() +=
"} // procedure\n";
194cp.
code() +=
"} // conditional\n";
195cp.
code() +=
"} // block\n";
198cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
205 cp.
code() = std::string(
"//CFSW\n");
208cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
220rs2 += R_rs2_0.read(ba) << 0;
223uimm += R_uimm_6.read(ba) << 6;
225uimm += R_uimm_2.read(ba) << 2;
228rs1 += R_rs1_0.read(ba) << 0;
230uimm += R_uimm_3.read(ba) << 3;
234 std::stringstream ss;
236ss <<
"cfsw" <<
" # " << ba << (
" [rs2=" + std::to_string(rs2) +
" | uimm=" + std::to_string(uimm) +
" | rs1=" + std::to_string(rs1) +
"]");
259uimm += R_uimm_6.
read(ba) << 6;
261uimm += R_uimm_2.
read(ba) << 2;
264rd += R_rd_0.
read(ba) << 0;
266uimm += R_uimm_5.
read(ba) << 5;
274 cp.
code() = std::string(
"//CFLWSP\n");
277cp.
code() +=
"etiss_coverage_count(1, 116);\n";
279cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
280cp.
code() +=
"{ // block\n";
282cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
283cp.
code() +=
"} // block\n";
286cp.
code() +=
"etiss_coverage_count(1, 5010);\n";
287cp.
code() +=
"{ // block\n";
288cp.
code() +=
"etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) +
"ULL;\n";
289cp.
code() +=
"etiss_coverage_count(5, 4979, 4978, 4976, 4975, 4977);\n";
290cp.
code() +=
"etiss_uint32 mem_val_0;\n";
291cp.
code() +=
"cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
292cp.
code() +=
"if (cpu->exception) { // conditional\n";
294cp.
code() +=
"{ // procedure\n";
295cp.
code() +=
"RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
297cp.
code() +=
"} // procedure\n";
299cp.
code() +=
"} // conditional\n";
300cp.
code() +=
"etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";
301cp.
code() +=
"etiss_coverage_count(4, 4986, 4985, 4983, 4982);\n";
303cp.
code() +=
"etiss_coverage_count(1, 5009);\n";
304cp.
code() +=
"{ // block\n";
305cp.
code() +=
"((RV32IMACFD*)cpu)->F[" + std::to_string(rd) +
"ULL] = -4294967296LL | res;\n";
306cp.
code() +=
"etiss_coverage_count(5, 5008, 4998, 4997, 5007, 5006);\n";
307cp.
code() +=
"} // block\n";
309cp.
code() +=
"} // block\n";
312cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
319 cp.
code() = std::string(
"//CFLWSP\n");
322cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
334uimm += R_uimm_6.read(ba) << 6;
336uimm += R_uimm_2.read(ba) << 2;
339rd += R_rd_0.read(ba) << 0;
341uimm += R_uimm_5.read(ba) << 5;
345 std::stringstream ss;
347ss <<
"cflwsp" <<
" # " << ba << (
" [uimm=" + std::to_string(uimm) +
" | rd=" + std::to_string(rd) +
"]");
370rs2 += R_rs2_0.
read(ba) << 0;
373uimm += R_uimm_6.
read(ba) << 6;
375uimm += R_uimm_2.
read(ba) << 2;
383 cp.
code() = std::string(
"//CFSWSP\n");
386cp.
code() +=
"etiss_coverage_count(1, 117);\n";
388cp.
code() +=
"etiss_coverage_count(1, 1169);\n";
389cp.
code() +=
"{ // block\n";
391cp.
code() +=
"etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";
392cp.
code() +=
"} // block\n";
395cp.
code() +=
"etiss_coverage_count(1, 5027);\n";
396cp.
code() +=
"{ // block\n";
397cp.
code() +=
"etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) +
"ULL;\n";
398cp.
code() +=
"etiss_coverage_count(5, 5017, 5016, 5014, 5013, 5015);\n";
399cp.
code() +=
"etiss_uint32 mem_val_0;\n";
400cp.
code() +=
"mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) +
"ULL]);\n";
401cp.
code() +=
"etiss_coverage_count(6, 5026, 5020, 5019, 5025, 5023, 5022);\n";
402cp.
code() +=
"cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";
403cp.
code() +=
"if (cpu->exception) { // conditional\n";
405cp.
code() +=
"{ // procedure\n";
406cp.
code() +=
"RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
408cp.
code() +=
"} // procedure\n";
410cp.
code() +=
"} // conditional\n";
411cp.
code() +=
"} // block\n";
414cp.
code() +=
"cpu->instructionPointer = cpu->nextPc;\n";
421 cp.
code() = std::string(
"//CFSWSP\n");
424cp.
code() +=
"if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
436rs2 += R_rs2_0.read(ba) << 0;
439uimm += R_uimm_6.read(ba) << 6;
441uimm += R_uimm_2.read(ba) << 2;
445 std::stringstream ss;
447ss <<
"cfswsp" <<
" # " << ba << (
" [rs2=" + std::to_string(rs2) +
" | uimm=" + std::to_string(uimm) +
"]");
etiss::instr::InstructionGroup ISA16_RV32IMACFD("ISA16_RV32IMACFD", 16)
static InstructionDefinition cfswsp_rs2_uimm(ISA16_RV32IMACFD, "cfswsp",(uint16_t) 0xe002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(8, 7);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(12, 9);uimm+=R_uimm_2.read(ba)<< 2;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CFSWSP\n");cp.code()+="etiss_coverage_count(1, 117);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5027);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 5017, 5016, 5014, 5013, 5015);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="etiss_coverage_count(6, 5026, 5020, 5019, 5025, 5023, 5022);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CFSWSP\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(8, 7);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(12, 9);uimm+=R_uimm_2.read(ba)<< 2;std::stringstream ss;ss<< "cfswsp"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | uimm="+std::to_string(uimm)+"]");return ss.str();})
static InstructionDefinition cfsw_rs2_uimm_rs1(ISA16_RV32IMACFD, "cfsw",(uint16_t) 0xe000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(5, 5);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 6);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CFSW\n");cp.code()+="etiss_coverage_count(1, 115);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4972);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 offs = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(7, 4960, 4959, 4957, 4956, 4954, 4955, 4958);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_uint32)(((RV32IMACFD*)cpu)->F["+std::to_string(rs2+8ULL)+"ULL]);\n";cp.code()+="etiss_coverage_count(8, 4971, 4963, 4962, 4970, 4968, 4967, 4965, 4966);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CFSW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(5, 5);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 6);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;std::stringstream ss;ss<< "cfsw"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | uimm="+std::to_string(uimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
static InstructionDefinition cflw_rd_uimm_rs1(ISA16_RV32IMACFD, "cflw",(uint16_t) 0x6000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(5, 5);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 6);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CFLW\n");cp.code()+="etiss_coverage_count(1, 114);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 4951);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 offs = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(7, 4916, 4915, 4913, 4912, 4910, 4911, 4914);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 4923, 4922, 4920, 4919);\n";{ cp.code()+="etiss_coverage_count(1, 4950);\n";cp.code()+="{ // block\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd+8ULL)+"ULL] = -4294967296LL | res;\n";cp.code()+="etiss_coverage_count(7, 4949, 4939, 4938, 4936, 4937, 4948, 4947);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CFLW\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(5, 5);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 6);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;std::stringstream ss;ss<< "cflw"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | uimm="+std::to_string(uimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
static InstructionDefinition cflwsp_uimm_rd(ISA16_RV32IMACFD, "cflwsp",(uint16_t) 0x6002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(3, 2);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 4);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_uimm_5(12, 12);uimm+=R_uimm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CFLWSP\n");cp.code()+="etiss_coverage_count(1, 116);\n";{ cp.code()+="etiss_coverage_count(1, 1169);\n";cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 1168, 1164, 1167, 1165, 1166);\n";cp.code()+="} // block\n";} { cp.code()+="etiss_coverage_count(1, 5010);\n";cp.code()+="{ // block\n";cp.code()+="etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_coverage_count(5, 4979, 4978, 4976, 4975, 4977);\n";cp.code()+="etiss_uint32 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 4);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint32 res = (etiss_uint32)(mem_val_0);\n";cp.code()+="etiss_coverage_count(4, 4986, 4985, 4983, 4982);\n";{ cp.code()+="etiss_coverage_count(1, 5009);\n";cp.code()+="{ // block\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = -4294967296LL | res;\n";cp.code()+="etiss_coverage_count(5, 5008, 4998, 4997, 5007, 5006);\n";cp.code()+="} // block\n";} cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CFLWSP\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(3, 2);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_2(6, 4);uimm+=R_uimm_2.read(ba)<< 2;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_uimm_5(12, 12);uimm+=R_uimm_5.read(ba)<< 5;std::stringstream ss;ss<< "cflwsp"<< " # "<< ba<<(" [uimm="+std::to_string(uimm)+" | rd="+std::to_string(rd)+"]");return ss.str();})
Contains a small code snipped.
@ APPENDEDRETURNINGREQUIRED
RegisterSet & getAffectedRegisters()
void append(const CodePart &part, CodePart::TYPE type)
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Reading through it will only return bits within the range.
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
this class contains parameters that persist in between instruction lookpus/translation within a trans...
uint64_t current_address_
start address of current instruction
holds information and translation callbacks for an instruction.