ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
RV32IMACFD_RV32DCInstr.cpp
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1 
8 #include "RV32IMACFDArch.h"
9 #include "RV32IMACFDFuncs.h"
10 
11 using namespace etiss;
12 using namespace etiss::instr;
13 
14 
15 // CFLD ------------------------------------------------------------------------
16 static InstructionDefinition cfld_rd_uimm_rs1 (
17  ISA16_RV32IMACFD,
18  "cfld",
19  (uint16_t) 0x2000,
20  (uint16_t) 0xe003,
21  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
22  {
23 
24 // -----------------------------------------------------------------------------
25 
26 // -----------------------------------------------------------------------------
27 
28 // -----------------------------------------------------------------------------
29 etiss_uint8 rd = 0;
30 static BitArrayRange R_rd_0(4, 2);
31 rd += R_rd_0.read(ba) << 0;
32 etiss_uint8 uimm = 0;
33 static BitArrayRange R_uimm_6(6, 5);
34 uimm += R_uimm_6.read(ba) << 6;
35 etiss_uint8 rs1 = 0;
36 static BitArrayRange R_rs1_0(9, 7);
37 rs1 += R_rs1_0.read(ba) << 0;
38 static BitArrayRange R_uimm_3(12, 10);
39 uimm += R_uimm_3.read(ba) << 3;
40 
41 // -----------------------------------------------------------------------------
42 
43  {
44  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
45 
46  cp.code() = std::string("//CFLD\n");
47 
48 // -----------------------------------------------------------------------------
49 { // block
50 cp.code() += "{ // block\n";
51 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
52 cp.code() += "} // block\n";
53 } // block
54 { // block
55 cp.code() += "{ // block\n";
56 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
57 cp.code() += "etiss_uint64 mem_val_0;\n";
58 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
59 cp.code() += "if (cpu->exception) { // conditional\n";
60 { // procedure
61 cp.code() += "{ // procedure\n";
62 cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
63 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
64 cp.code() += "} // procedure\n";
65 } // procedure
66 cp.code() += "} // conditional\n";
67 cp.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
68 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd + 8ULL) + "ULL] = res;\n";
69 cp.code() += "} // block\n";
70 } // block
71 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
72 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
73 // -----------------------------------------------------------------------------
74  cp.getAffectedRegisters().add("instructionPointer", 32);
75  }
76  {
77  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
78 
79  cp.code() = std::string("//CFLD\n");
80 
81 // -----------------------------------------------------------------------------
82 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
83 // -----------------------------------------------------------------------------
84  }
85 
86  return true;
87  },
88  0,
89  [] (BitArray & ba, Instruction & instr)
90  {
91 // -----------------------------------------------------------------------------
92 etiss_uint8 rd = 0;
93 static BitArrayRange R_rd_0(4, 2);
94 rd += R_rd_0.read(ba) << 0;
95 etiss_uint8 uimm = 0;
96 static BitArrayRange R_uimm_6(6, 5);
97 uimm += R_uimm_6.read(ba) << 6;
98 etiss_uint8 rs1 = 0;
99 static BitArrayRange R_rs1_0(9, 7);
100 rs1 += R_rs1_0.read(ba) << 0;
101 static BitArrayRange R_uimm_3(12, 10);
102 uimm += R_uimm_3.read(ba) << 3;
103 
104 // -----------------------------------------------------------------------------
105 
106  std::stringstream ss;
107 // -----------------------------------------------------------------------------
108 ss << "cfld" << " # " << ba << (" [rd=" + std::to_string(rd) + " | uimm=" + std::to_string(uimm) + " | rs1=" + std::to_string(rs1) + "]");
109 // -----------------------------------------------------------------------------
110  return ss.str();
111  }
112 );
113 
114 // CFSD ------------------------------------------------------------------------
115 static InstructionDefinition cfsd_rs2_uimm_rs1 (
116  ISA16_RV32IMACFD,
117  "cfsd",
118  (uint16_t) 0xa000,
119  (uint16_t) 0xe003,
120  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
121  {
122 
123 // -----------------------------------------------------------------------------
124 
125 // -----------------------------------------------------------------------------
126 
127 // -----------------------------------------------------------------------------
128 etiss_uint8 rs2 = 0;
129 static BitArrayRange R_rs2_0(4, 2);
130 rs2 += R_rs2_0.read(ba) << 0;
131 etiss_uint8 uimm = 0;
132 static BitArrayRange R_uimm_6(6, 5);
133 uimm += R_uimm_6.read(ba) << 6;
134 etiss_uint8 rs1 = 0;
135 static BitArrayRange R_rs1_0(9, 7);
136 rs1 += R_rs1_0.read(ba) << 0;
137 static BitArrayRange R_uimm_3(12, 10);
138 uimm += R_uimm_3.read(ba) << 3;
139 
140 // -----------------------------------------------------------------------------
141 
142  {
143  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
144 
145  cp.code() = std::string("//CFSD\n");
146 
147 // -----------------------------------------------------------------------------
148 { // block
149 cp.code() += "{ // block\n";
150 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
151 cp.code() += "} // block\n";
152 } // block
153 { // block
154 cp.code() += "{ // block\n";
155 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[" + std::to_string(rs1 + 8ULL) + "ULL] + " + std::to_string(uimm) + "ULL;\n";
156 cp.code() += "etiss_uint64 mem_val_0;\n";
157 cp.code() += "mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2 + 8ULL) + "ULL]);\n";
158 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
159 cp.code() += "if (cpu->exception) { // conditional\n";
160 { // procedure
161 cp.code() += "{ // procedure\n";
162 cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
163 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
164 cp.code() += "} // procedure\n";
165 } // procedure
166 cp.code() += "} // conditional\n";
167 cp.code() += "} // block\n";
168 } // block
169 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
170 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
171 // -----------------------------------------------------------------------------
172  cp.getAffectedRegisters().add("instructionPointer", 32);
173  }
174  {
175  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
176 
177  cp.code() = std::string("//CFSD\n");
178 
179 // -----------------------------------------------------------------------------
180 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
181 // -----------------------------------------------------------------------------
182  }
183 
184  return true;
185  },
186  0,
187  [] (BitArray & ba, Instruction & instr)
188  {
189 // -----------------------------------------------------------------------------
190 etiss_uint8 rs2 = 0;
191 static BitArrayRange R_rs2_0(4, 2);
192 rs2 += R_rs2_0.read(ba) << 0;
193 etiss_uint8 uimm = 0;
194 static BitArrayRange R_uimm_6(6, 5);
195 uimm += R_uimm_6.read(ba) << 6;
196 etiss_uint8 rs1 = 0;
197 static BitArrayRange R_rs1_0(9, 7);
198 rs1 += R_rs1_0.read(ba) << 0;
199 static BitArrayRange R_uimm_3(12, 10);
200 uimm += R_uimm_3.read(ba) << 3;
201 
202 // -----------------------------------------------------------------------------
203 
204  std::stringstream ss;
205 // -----------------------------------------------------------------------------
206 ss << "cfsd" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | uimm=" + std::to_string(uimm) + " | rs1=" + std::to_string(rs1) + "]");
207 // -----------------------------------------------------------------------------
208  return ss.str();
209  }
210 );
211 
212 // CFLDSP ----------------------------------------------------------------------
213 static InstructionDefinition cfldsp_uimm_rd (
214  ISA16_RV32IMACFD,
215  "cfldsp",
216  (uint16_t) 0x2002,
217  (uint16_t) 0xe003,
218  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
219  {
220 
221 // -----------------------------------------------------------------------------
222 
223 // -----------------------------------------------------------------------------
224 
225 // -----------------------------------------------------------------------------
226 etiss_uint16 uimm = 0;
227 static BitArrayRange R_uimm_6(4, 2);
228 uimm += R_uimm_6.read(ba) << 6;
229 static BitArrayRange R_uimm_3(6, 5);
230 uimm += R_uimm_3.read(ba) << 3;
231 etiss_uint8 rd = 0;
232 static BitArrayRange R_rd_0(11, 7);
233 rd += R_rd_0.read(ba) << 0;
234 static BitArrayRange R_uimm_5(12, 12);
235 uimm += R_uimm_5.read(ba) << 5;
236 
237 // -----------------------------------------------------------------------------
238 
239  {
240  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
241 
242  cp.code() = std::string("//CFLDSP\n");
243 
244 // -----------------------------------------------------------------------------
245 { // block
246 cp.code() += "{ // block\n";
247 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
248 cp.code() += "} // block\n";
249 } // block
250 { // block
251 cp.code() += "{ // block\n";
252 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
253 cp.code() += "etiss_uint64 mem_val_0;\n";
254 cp.code() += "cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
255 cp.code() += "if (cpu->exception) { // conditional\n";
256 { // procedure
257 cp.code() += "{ // procedure\n";
258 cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
259 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
260 cp.code() += "} // procedure\n";
261 } // procedure
262 cp.code() += "} // conditional\n";
263 cp.code() += "etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";
264 cp.code() += "((RV32IMACFD*)cpu)->F[" + std::to_string(rd) + "ULL] = res;\n";
265 cp.code() += "} // block\n";
266 } // block
267 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
268 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
269 // -----------------------------------------------------------------------------
270  cp.getAffectedRegisters().add("instructionPointer", 32);
271  }
272  {
273  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
274 
275  cp.code() = std::string("//CFLDSP\n");
276 
277 // -----------------------------------------------------------------------------
278 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
279 // -----------------------------------------------------------------------------
280  }
281 
282  return true;
283  },
284  0,
285  [] (BitArray & ba, Instruction & instr)
286  {
287 // -----------------------------------------------------------------------------
288 etiss_uint16 uimm = 0;
289 static BitArrayRange R_uimm_6(4, 2);
290 uimm += R_uimm_6.read(ba) << 6;
291 static BitArrayRange R_uimm_3(6, 5);
292 uimm += R_uimm_3.read(ba) << 3;
293 etiss_uint8 rd = 0;
294 static BitArrayRange R_rd_0(11, 7);
295 rd += R_rd_0.read(ba) << 0;
296 static BitArrayRange R_uimm_5(12, 12);
297 uimm += R_uimm_5.read(ba) << 5;
298 
299 // -----------------------------------------------------------------------------
300 
301  std::stringstream ss;
302 // -----------------------------------------------------------------------------
303 ss << "cfldsp" << " # " << ba << (" [uimm=" + std::to_string(uimm) + " | rd=" + std::to_string(rd) + "]");
304 // -----------------------------------------------------------------------------
305  return ss.str();
306  }
307 );
308 
309 // CFSDSP ----------------------------------------------------------------------
310 static InstructionDefinition cfsdsp_rs2_uimm (
311  ISA16_RV32IMACFD,
312  "cfsdsp",
313  (uint16_t) 0xa002,
314  (uint16_t) 0xe003,
315  [] (BitArray & ba,etiss::CodeSet & cs,InstructionContext & ic)
316  {
317 
318 // -----------------------------------------------------------------------------
319 
320 // -----------------------------------------------------------------------------
321 
322 // -----------------------------------------------------------------------------
323 etiss_uint8 rs2 = 0;
324 static BitArrayRange R_rs2_0(6, 2);
325 rs2 += R_rs2_0.read(ba) << 0;
326 etiss_uint16 uimm = 0;
327 static BitArrayRange R_uimm_6(9, 7);
328 uimm += R_uimm_6.read(ba) << 6;
329 static BitArrayRange R_uimm_3(12, 10);
330 uimm += R_uimm_3.read(ba) << 3;
331 
332 // -----------------------------------------------------------------------------
333 
334  {
335  CodePart & cp = cs.append(CodePart::INITIALREQUIRED);
336 
337  cp.code() = std::string("//CFSDSP\n");
338 
339 // -----------------------------------------------------------------------------
340 { // block
341 cp.code() += "{ // block\n";
342 cp.code() += "cpu->nextPc = " + std::to_string(ic.current_address_ + 2) + "ULL;\n";
343 cp.code() += "} // block\n";
344 } // block
345 { // block
346 cp.code() += "{ // block\n";
347 cp.code() += "etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + " + std::to_string(uimm) + "ULL;\n";
348 cp.code() += "etiss_uint64 mem_val_0;\n";
349 cp.code() += "mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F[" + std::to_string(rs2) + "ULL]);\n";
350 cp.code() += "cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";
351 cp.code() += "if (cpu->exception) { // conditional\n";
352 { // procedure
353 cp.code() += "{ // procedure\n";
354 cp.code() += "RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";
355 cp.code() += "goto instr_exit_" + std::to_string(ic.current_address_) + ";\n";
356 cp.code() += "} // procedure\n";
357 } // procedure
358 cp.code() += "} // conditional\n";
359 cp.code() += "} // block\n";
360 } // block
361 cp.code() += "instr_exit_" + std::to_string(ic.current_address_) + ":\n";
362 cp.code() += "cpu->instructionPointer = cpu->nextPc;\n";
363 // -----------------------------------------------------------------------------
364  cp.getAffectedRegisters().add("instructionPointer", 32);
365  }
366  {
367  CodePart & cp = cs.append(CodePart::APPENDEDRETURNINGREQUIRED);
368 
369  cp.code() = std::string("//CFSDSP\n");
370 
371 // -----------------------------------------------------------------------------
372 cp.code() += "if (cpu->return_pending || cpu->exception) return cpu->exception;\n";
373 // -----------------------------------------------------------------------------
374  }
375 
376  return true;
377  },
378  0,
379  [] (BitArray & ba, Instruction & instr)
380  {
381 // -----------------------------------------------------------------------------
382 etiss_uint8 rs2 = 0;
383 static BitArrayRange R_rs2_0(6, 2);
384 rs2 += R_rs2_0.read(ba) << 0;
385 etiss_uint16 uimm = 0;
386 static BitArrayRange R_uimm_6(9, 7);
387 uimm += R_uimm_6.read(ba) << 6;
388 static BitArrayRange R_uimm_3(12, 10);
389 uimm += R_uimm_3.read(ba) << 3;
390 
391 // -----------------------------------------------------------------------------
392 
393  std::stringstream ss;
394 // -----------------------------------------------------------------------------
395 ss << "cfsdsp" << " # " << ba << (" [rs2=" + std::to_string(rs2) + " | uimm=" + std::to_string(uimm) + "]");
396 // -----------------------------------------------------------------------------
397  return ss.str();
398  }
399 );
ISA16_RV32IMACFD
etiss::instr::InstructionGroup ISA16_RV32IMACFD("ISA16_RV32IMACFD", 16)
cfldsp_uimm_rd
static InstructionDefinition cfldsp_uimm_rd(ISA16_RV32IMACFD, "cfldsp",(uint16_t) 0x2002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint16 uimm=0;static BitArrayRange R_uimm_6(4, 2);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_3(6, 5);uimm+=R_uimm_3.read(ba)<< 3;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_uimm_5(12, 12);uimm+=R_uimm_5.read(ba)<< 5;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CFLDSP\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd)+"ULL] = res;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CFLDSP\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint16 uimm=0;static BitArrayRange R_uimm_6(4, 2);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_3(6, 5);uimm+=R_uimm_3.read(ba)<< 3;etiss_uint8 rd=0;static BitArrayRange R_rd_0(11, 7);rd+=R_rd_0.read(ba)<< 0;static BitArrayRange R_uimm_5(12, 12);uimm+=R_uimm_5.read(ba)<< 5;std::stringstream ss;ss<< "cfldsp"<< " # "<< ba<<(" [uimm="+std::to_string(uimm)+" | rd="+std::to_string(rd)+"]");return ss.str();})
cfld_rd_uimm_rs1
static InstructionDefinition cfld_rd_uimm_rs1(ISA16_RV32IMACFD, "cfld",(uint16_t) 0x2000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(6, 5);uimm+=R_uimm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CFLD\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint32 offs = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="cpu->exception |= (*(system->dread))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="etiss_uint64 res = (etiss_uint64)(mem_val_0);\n";cp.code()+="((RV32IMACFD*)cpu)->F["+std::to_string(rd+8ULL)+"ULL] = res;\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CFLD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rd=0;static BitArrayRange R_rd_0(4, 2);rd+=R_rd_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(6, 5);uimm+=R_uimm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;std::stringstream ss;ss<< "cfld"<< " # "<< ba<<(" [rd="+std::to_string(rd)+" | uimm="+std::to_string(uimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
cfsdsp_rs2_uimm
static InstructionDefinition cfsdsp_rs2_uimm(ISA16_RV32IMACFD, "cfsdsp",(uint16_t) 0xa002,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint16 uimm=0;static BitArrayRange R_uimm_6(9, 7);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CFSDSP\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint32 offs = *((RV32IMACFD*)cpu)->X[2ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F["+std::to_string(rs2)+"ULL]);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CFSDSP\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(6, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint16 uimm=0;static BitArrayRange R_uimm_6(9, 7);uimm+=R_uimm_6.read(ba)<< 6;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;std::stringstream ss;ss<< "cfsdsp"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | uimm="+std::to_string(uimm)+"]");return ss.str();})
cfsd_rs2_uimm_rs1
static InstructionDefinition cfsd_rs2_uimm_rs1(ISA16_RV32IMACFD, "cfsd",(uint16_t) 0xa000,(uint16_t) 0xe003, [](BitArray &ba, etiss::CodeSet &cs, InstructionContext &ic) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(6, 5);uimm+=R_uimm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;{ CodePart &cp=cs.append(CodePart::INITIALREQUIRED);cp.code()=std::string("//CFSD\n");{ cp.code()+="{ // block\n";cp.code()+="cpu->nextPc = "+std::to_string(ic.current_address_+2)+"ULL;\n";cp.code()+="} // block\n";} { cp.code()+="{ // block\n";cp.code()+="etiss_uint32 offs = *((RV32IMACFD*)cpu)->X["+std::to_string(rs1+8ULL)+"ULL] + "+std::to_string(uimm)+"ULL;\n";cp.code()+="etiss_uint64 mem_val_0;\n";cp.code()+="mem_val_0 = (etiss_uint64)(((RV32IMACFD*)cpu)->F["+std::to_string(rs2+8ULL)+"ULL]);\n";cp.code()+="cpu->exception |= (*(system->dwrite))(system->handle, cpu, offs, (etiss_uint8*)&mem_val_0, 8);\n";cp.code()+="if (cpu->exception) { // conditional\n";{ cp.code()+="{ // procedure\n";cp.code()+="RV32IMACFD_translate_exc_code(cpu, system, plugin_pointers, cpu->exception);\n";cp.code()+="goto instr_exit_"+std::to_string(ic.current_address_)+";\n";cp.code()+="} // procedure\n";} cp.code()+="} // conditional\n";cp.code()+="} // block\n";} cp.code()+="instr_exit_"+std::to_string(ic.current_address_)+":\n";cp.code()+="cpu->instructionPointer = cpu->nextPc;\n";cp.getAffectedRegisters().add("instructionPointer", 32);} { CodePart &cp=cs.append(CodePart::APPENDEDRETURNINGREQUIRED);cp.code()=std::string("//CFSD\n");cp.code()+="if (cpu->return_pending || cpu->exception) return cpu->exception;\n";} return true;}, 0, [](BitArray &ba, Instruction &instr) { etiss_uint8 rs2=0;static BitArrayRange R_rs2_0(4, 2);rs2+=R_rs2_0.read(ba)<< 0;etiss_uint8 uimm=0;static BitArrayRange R_uimm_6(6, 5);uimm+=R_uimm_6.read(ba)<< 6;etiss_uint8 rs1=0;static BitArrayRange R_rs1_0(9, 7);rs1+=R_rs1_0.read(ba)<< 0;static BitArrayRange R_uimm_3(12, 10);uimm+=R_uimm_3.read(ba)<< 3;std::stringstream ss;ss<< "cfsd"<< " # "<< ba<<(" [rs2="+std::to_string(rs2)+" | uimm="+std::to_string(uimm)+" | rs1="+std::to_string(rs1)+"]");return ss.str();})
uint16_t
static __inline__ uint16_t
Definition: arm_mve.h:315
etiss_uint8
uint8_t etiss_uint8
Definition: types.h:87
etiss_uint16
uint16_t etiss_uint16
Definition: types.h:90
etiss::CodePart
Contains a small code snipped.
Definition: CodePart.h:386
etiss::CodePart::APPENDEDRETURNINGREQUIRED
@ APPENDEDRETURNINGREQUIRED
Definition: CodePart.h:402
etiss::CodePart::code
std::string & code()
Definition: CodePart.h:416
etiss::CodePart::getAffectedRegisters
RegisterSet & getAffectedRegisters()
Definition: CodePart.h:414
etiss::CodeSet
A set of CodeParts.
Definition: CodePart.h:437
etiss::CodeSet::append
void append(const CodePart &part, CodePart::TYPE type)
Definition: CodePart.h:450
etiss::RegisterSet::add
void add(const RegisterPart &rp)
add a registerPart to the set or just its relevant bits if a register with the same name is already p...
Definition: CodePart.h:222
etiss::instr::BitArrayRange
Reading through it will only return bits within the range.
Definition: Instruction.h:208
etiss::instr::BitArrayRange::read
I read(const BitArray &ba)
reads bits from the range to the return value starting at the lsb.
Definition: Instruction.cpp:198
etiss::instr::BitArray
stores a bit vector
Definition: Instruction.h:161
etiss::instr::InstructionContext
this class contains parameters that persist in between instruction lookpus/translation within a trans...
Definition: Instruction.h:337
etiss::instr::InstructionContext::current_address_
uint64_t current_address_
start address of current instruction
Definition: Instruction.h:366
etiss::instr::Instruction
holds information and translation callbacks for an instruction.
Definition: Instruction.h:393
etiss
Page Table Entry (PTE) defines the composition of Page Frame Number (PFN) and relavant flags.
Definition: Benchmark.h:53
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