mlonmcu.target.riscv package

Submodules

mlonmcu.target.riscv.ara module

MLonMCU ARA Target definitions

class mlonmcu.target.riscv.ara.AraTarget(name='ara', features=None, config=None)

Bases: RVVTarget

Target using a Pulpino-like VP running in the GVSOC simulator

DEFAULTS = {'abi': None, 'arch': None, 'atomic': True, 'attr': '', 'compressed': True, 'cpu': None, 'elen': 64, 'embedded': False, 'embedded_vext': False, 'enable_vext': False, 'extensions': [], 'extra_args': '', 'fpu': 'double', 'limit_cycles': 10000000, 'multiply': True, 'nr_lanes': 4, 'num_threads': 4, 'print_outputs': False, 'repeat': None, 'timeout_sec': 0, 'vext_spec': 1.0, 'vlen': 4096, 'xlen': 64}

FEATURES = {'benchmark', 'log_instrs', 'vext'}

OPTIONAL = {'ara.verilator_tb', 'llvm.install_dir', 'mlif.toolchain'}

REQUIRED = {'ara.src_dir', 'riscv_gcc.install_dir', 'riscv_gcc.name', 'riscv_gcc.variant', 'verilator.install_dir'}

property ara_apps_dir

property ara_hardware_dir

property ara_verilator_tb

property elen

property embedded_vext

property enable_vext

exec(program, *args, cwd='/home/runner/work/mlonmcu/mlonmcu/docs', **kwargs)

Use target to execute an executable with given arguments

property extensions

get_backend_config(backend, optimized_layouts=False, optimized_schedules=False)

get_metrics(elf, directory, *args, handle_exit=None)

get_platform_defs(platform)

get_target_system()

property limit_cycles

property nr_lanes

property num_threads

parse_exit(out)

parse_stdout(out, metrics, exit_code=0)

prepare_simulator(program, *_, cwd='/home/runner/work/mlonmcu/mlonmcu/docs', **kwargs)

property verilator_install_dir

property vext_spec

property vlen

mlonmcu.target.riscv.ara_rtl module

MLonMCU ARA Target definitions

class mlonmcu.target.riscv.ara_rtl.AraRtlTarget(name='ara_rtl', features=None, config=None)

Bases: RVVTarget

TODO

DEFAULTS = {'abi': None, 'arch': None, 'atomic': True, 'attr': '', 'compressed': True, 'cpu': None, 'elen': 64, 'embedded': False, 'embedded_vext': False, 'enable_vext': False, 'extensions': [], 'extra_args': '', 'fpu': 'double', 'limit_cycles': 10000000, 'multiply': True, 'nr_lanes': 4, 'num_threads': 4, 'print_outputs': False, 'repeat': None, 'timeout_sec': 0, 'vext_spec': 1.0, 'vlen': 4096, 'xlen': 64}

FEATURES = {'benchmark', 'log_instrs', 'vext'}

OPTIONAL = {'llvm.install_dir', 'mlif.toolchain', 'questasim.install_dir'}

REQUIRED = {'ara.src_dir', 'riscv_gcc.install_dir', 'riscv_gcc.name', 'riscv_gcc.variant', 'spike.install_dir', 'verilator.install_dir'}

property ara_apps_dir

property ara_hardware_dir

property elen

property embedded_vext

property enable_vext

exec(program, *args, cwd='/home/runner/work/mlonmcu/mlonmcu/docs', **kwargs)

Use target to execute an executable with given arguments

property extensions

get_backend_config(backend, optimized_layouts=False, optimized_schedules=False)

get_metrics(elf, directory, *args, handle_exit=None)

get_platform_defs(platform)

get_target_system()

property limit_cycles

property nr_lanes

property num_threads

parse_exit(out)

parse_stdout(out, metrics, exit_code=0)

prepare_simulator(program, *_, cwd='/home/runner/work/mlonmcu/mlonmcu/docs', **kwargs)

property questasim_install_dir

property spike_install_dir

property verilator_install_dir

property vext_spec

property vlen

mlonmcu.target.riscv.corev_ovpsim module

MLonMCU OVPSimCOREV Target definitions

class mlonmcu.target.riscv.corev_ovpsim.COREVOVPSimTarget(name='corev_ovpsim', features=None, config=None)

Bases: RISCVTarget

TODO

DEFAULTS = {'abi': None, 'arch': None, 'atomic': False, 'attr': '', 'compressed': True, 'cpu': None, 'embedded': False, 'enable_xcorevalu': False, 'enable_xcorevbi': False, 'enable_xcorevbitmanip': False, 'enable_xcorevhwlp': False, 'enable_xcorevmac': False, 'enable_xcorevmem': False, 'enable_xcorevsimd': False, 'end_to_end_cycles': False, 'extensions': [], 'extra_args': '', 'fpu': 'none', 'gdbserver_attach': False, 'gdbserver_enable': False, 'gdbserver_port': 2222, 'multiply': True, 'print_outputs': False, 'processor': None, 'repeat': None, 'timeout_sec': 0, 'variant': None, 'xlen': 32}

FEATURES = {'benchmark', 'gdbserver', 'log_instrs', 'trace', 'xcorev'}

REQUIRED = {'corev_ovpsim.exe', 'riscv_gcc.install_dir', 'riscv_gcc.name', 'riscv_gcc.variant'}

property attr

property enable_xcorevalu

property enable_xcorevbi

property enable_xcorevbitmanip

property enable_xcorevhwlp

property enable_xcorevmac

property enable_xcorevmem

property enable_xcorevsimd

property end_to_end_cycles

exec(program, *args, cwd='/home/runner/work/mlonmcu/mlonmcu/docs', **kwargs)

Use target to execute a executable with given arguments

property extensions

property gdbserver_attach

property gdbserver_enable

property gdbserver_port

get_backend_config(backend, optimized_layouts=False, optimized_schedules=False)

get_default_ovpsim_args()

get_metrics(elf, directory, *args, handle_exit=None)

get_platform_defs(platform)

property ovpsim_exe

parse_exit(out)

parse_stdout(out, metrics, exit_code=0)

property processor

property variant

mlonmcu.target.riscv.corev_ovpsim.replace_unsupported(exts)

mlonmcu.target.riscv.cv32e40p module

MLonMCU ETISS/Pulpino Target definitions

class mlonmcu.target.riscv.cv32e40p.CV32E40PTarget(name='cv32e40p', features=None, config=None)

Bases: RISCVTarget

Target for running CV32E40P programs in verilated RTL core.

DEFAULTS = {'abi': None, 'arch': None, 'atomic': False, 'attr': '', 'compressed': True, 'cpu': None, 'embedded': False, 'enable_xcorevalu': False, 'enable_xcorevbi': False, 'enable_xcorevbitmanip': False, 'enable_xcorevhwlp': False, 'enable_xcorevmac': False, 'enable_xcorevmem': False, 'enable_xcorevsimd': False, 'extensions': [], 'extra_args': '', 'fpu': 'none', 'multiply': True, 'print_outputs': False, 'repeat': None, 'timeout_sec': 0, 'xlen': 32}

FEATURES = {'benchmark', 'xcorev'}

REQUIRED = {'cv32e40p.verilator_executable', 'riscv_gcc.install_dir', 'riscv_gcc.name', 'riscv_gcc.variant'}

property attr

property enable_xcorevalu

property enable_xcorevbi

property enable_xcorevbitmanip

property enable_xcorevhwlp

property enable_xcorevmac

property enable_xcorevmem

property enable_xcorevsimd

exec(program, *args, cwd='/home/runner/work/mlonmcu/mlonmcu/docs', **kwargs)

Use target to execute a executable with given arguments

property extensions

get_backend_config(backend, optimized_layouts=False, optimized_schedules=False)

get_metrics(elf, directory, *args, handle_exit=None)

get_platform_defs(platform)

get_target_system()

parse_exit(out)

parse_stdout(out, metrics, exit_code=0)

property verilator_executable

mlonmcu.target.riscv.etiss module

MLonMCU ETISS/Pulpino Target definitions

class mlonmcu.target.riscv.etiss.EtissTarget(name='etiss', features=None, config=None)

Bases: RISCVTarget

Target using a simple RISC-V VP running in the ETISS simulator

DEFAULTS = {'abi': None, 'allow_error': False, 'arch': None, 'atomic': True, 'attr': '', 'compressed': True, 'cpu': None, 'cpu_arch': None, 'cycle_time_ps': 31250, 'debug_etiss': False, 'elen': 32, 'embedded': False, 'embedded_vext': False, 'enable_pext': False, 'enable_vext': False, 'enable_xcorevalu': False, 'enable_xcorevbi': False, 'enable_xcorevbitmanip': False, 'enable_xcorevhwlp': False, 'enable_xcorevmac': False, 'enable_xcorevmem': False, 'enable_xcorevsimd': False, 'extensions': [], 'extra_args': '', 'extra_bool_config': {}, 'extra_int_config': {}, 'extra_plugin_config': {}, 'extra_string_config': {}, 'fpu': 'double', 'gdbserver_attach': False, 'gdbserver_enable': False, 'gdbserver_port': 2222, 'jit': None, 'max_block_size': None, 'multiply': True, 'pext_spec': 0.96, 'plugins': [], 'print_outputs': False, 'ram_size': 67108864, 'ram_start': 8388608, 'repeat': None, 'rom_size': 8388608, 'rom_start': 0, 'timeout_sec': 0, 'trace_memory': False, 'verbose': False, 'vext_spec': 1.0, 'vlen': 0, 'xlen': 32}

FEATURES = {'benchmark', 'etissdbg', 'gdbserver', 'log_instrs', 'pext', 'trace', 'vanilla_accelerator', 'vext', 'xcorev'}

REQUIRED = {'etiss.install_dir', 'etiss.src_dir', 'etissvp.script', 'riscv_gcc.install_dir', 'riscv_gcc.name', 'riscv_gcc.variant'}

property allow_error

property attr

property cpu_arch

property cycle_time_ps

property debug_etiss

property elen

property embedded_vext

property enable_pext

property enable_vext

property enable_xcorevalu

property enable_xcorevbi

property enable_xcorevbitmanip

property enable_xcorevhwlp

property enable_xcorevmac

property enable_xcorevmem

property enable_xcorevsimd

property etiss_dir

property etiss_script

property etiss_src_dir

exec(program, *args, cwd='/home/runner/work/mlonmcu/mlonmcu/docs', **kwargs)

Use target to execute a executable with given arguments

property extensions

property extra_bool_config

property extra_int_config

property extra_plugin_config

property extra_string_config

property gdbserver_attach

property gdbserver_enable

property gdbserver_port

get_backend_config(backend, optimized_layouts=False, optimized_schedules=False)

get_ini_bool_config()

get_ini_int_config()

get_ini_plugin_config()

get_ini_string_config()

get_metrics(elf, directory, *args, handle_exit=None)

get_platform_defs(platform)

get_target_system()

property jit

property max_block_size

parse_exit(out)

parse_stdout(out, metrics, exit_code=0)

property pext_spec

property plugins

property ram_size

property ram_start

property rom_size

property rom_start

property trace_memory

property verbose

property vext_spec

property vlen

write_ini(path)

mlonmcu.target.riscv.etiss_pulpino module

MLonMCU ETISS/Pulpino Target definitions

class mlonmcu.target.riscv.etiss_pulpino.EtissPulpinoTarget(name='etiss_pulpino', features=None, config=None)

Bases: EtissTarget

Target using a Pulpino-like VP running in the ETISS simulator

REQUIRED = {'etiss.install_dir', 'etiss.src_dir', 'etissvp.script', 'riscv_gcc.install_dir', 'riscv_gcc.name', 'riscv_gcc.variant'}

get_ini_bool_config()

get_platform_defs(platform)

mlonmcu.target.riscv.gvsoc_pulp module

MLonMCU GVSOC/Pulp or Pulpissimo Target definitions

class mlonmcu.target.riscv.gvsoc_pulp.GvsocPulpTarget(name='gvsoc_pulp', features=None, config=None)

Bases: RISCVTarget

Target using a Pulpino-like VP running in the GVSOC simulator

DEFAULTS = {'abi': 'ilp32', 'arch': None, 'atomic': True, 'attr': '', 'compressed': True, 'cpu': None, 'embedded': False, 'extensions': ['i', 'm', 'c'], 'extra_args': '', 'fpu': None, 'model': 'pulp', 'multiply': True, 'print_outputs': False, 'repeat': None, 'timeout_sec': 0, 'xlen': 32, 'xpulp_version': None}

FEATURES = {'benchmark', 'log_instrs', 'xpulp'}

REQUIRED = {'gvsoc.exe', 'pulp_freertos.config_dir', 'pulp_freertos.install_dir', 'pulp_freertos.support_dir', 'pulp_gcc.install_dir', 'pulp_gcc.name'}

property abi

exec(program, *args, cwd='/home/runner/work/mlonmcu/mlonmcu/docs', **kwargs)

Use target to execute an executable with given arguments

property extensions

get_backend_config(backend, optimized_layouts=False, optimized_schedules=False)

get_basic_gvsoc_simulating_arg(program)

get_metrics(elf, directory, *args, handle_exit=None)

get_platform_defs(platform)

get_target_system()

property gvsoc_folder

gvsoc_preparation_env()

property gvsoc_script

property model

parse_stdout(out)

property pulp_freertos_config_dir

property pulp_freertos_install_dir

property pulp_freertos_support_dir

property xpulp_version

mlonmcu.target.riscv.ovpsim module

MLonMCU OVPSim Target definitions

class mlonmcu.target.riscv.ovpsim.OVPSimTarget(name='ovpsim', features=None, config=None)

Bases: RVPTarget, RVVTarget

Target using an ARM FVP (fixed virtual platform) based on a Cortex M55 with EthosU support

DEFAULTS = {'abi': None, 'arch': None, 'atomic': True, 'attr': '', 'bitmanip_spec': 0.94, 'compressed': True, 'cpu': None, 'elen': 64, 'embedded': False, 'embedded_vext': False, 'enable_pext': False, 'enable_vext': False, 'end_to_end_cycles': True, 'extensions': [], 'extra_args': '', 'fpu': 'double', 'gdbserver_attach': False, 'gdbserver_enable': False, 'gdbserver_port': 2222, 'multiply': True, 'pext_spec': 0.92, 'print_outputs': False, 'repeat': None, 'timeout_sec': 0, 'variant': None, 'vext_spec': 1.0, 'vlen': 128, 'xlen': 32}

FEATURES = {'benchmark', 'gdbserver', 'log_instrs', 'pext', 'trace', 'vext'}

REQUIRED = {'ovpsim.exe', 'riscv_gcc.install_dir', 'riscv_gcc.name', 'riscv_gcc.variant'}

property end_to_end_cycles

exec(program, *args, cwd='/home/runner/work/mlonmcu/mlonmcu/docs', **kwargs)

Use target to execute a executable with given arguments

property extensions

property gdbserver_attach

property gdbserver_enable

property gdbserver_port

get_backend_config(backend, optimized_layouts=False, optimized_schedules=False)

get_default_ovpsim_args()

get_metrics(elf, directory, *args, handle_exit=None)

get_platform_defs(platform)

property ovpsim_exe

parse_stdout(out)

property variant

mlonmcu.target.riscv.ovpsim.replace_unsupported(exts)

mlonmcu.target.riscv.riscv module

MLonMCU RISC-V Target definitions

class mlonmcu.target.riscv.riscv.RISCVTarget(name: str, features: List[Feature] | None = None, config: dict | None = None)

Bases: Target

Common base class for RISCV-like targets. Please do not use this as a target itself!

DEFAULTS = {'abi': None, 'arch': None, 'atomic': True, 'attr': '', 'compressed': True, 'cpu': None, 'embedded': False, 'extensions': [], 'extra_args': '', 'fpu': 'double', 'multiply': True, 'print_outputs': False, 'repeat': None, 'timeout_sec': 0, 'xlen': 32}

FEATURES = {'benchmark'}

OPTIONAL = {'llvm.install_dir', 'mlif.toolchain'}

PUPL_GCC_TOOLCHAIN_REQUIRED = {'pulp_gcc.install_dir', 'pulp_gcc.name'}

REQUIRED = {'riscv_gcc.install_dir', 'riscv_gcc.name', 'riscv_gcc.variant'}

property abi

property arch

property atomic

property attr

property attrs

property compressed

property cpu

property embedded

property extensions

property extra_args

property fpu

property gcc_arch

property gcc_extensions

property gcc_variant

get_arch()

get_backend_config(backend, optimized_layouts=False, optimized_schedules=False)

get_platform_defs(platform)

get_target_system()

property has_fpu

property llvm_arch

property llvm_extensions

property multiply

property pulp_gcc_basename

property pulp_gcc_prefix

reconfigure()

property riscv_gcc_basename

property riscv_gcc_prefix

property timeout_sec

property toolchain

property xlen

mlonmcu.target.riscv.riscv_bext_target module

MLonMCU Spike Target definitions

class mlonmcu.target.riscv.riscv_bext_target.RVBTarget(name, features=None, config=None)

Bases: RISCVTarget

TODO

DEFAULTS = {'abi': None, 'arch': None, 'atomic': True, 'attr': '', 'bext_spec': 0.92, 'bext_zba': False, 'bext_zbb': False, 'bext_zbc': False, 'bext_zbs': False, 'compressed': True, 'cpu': None, 'embedded': False, 'enable_bext': False, 'extensions': [], 'extra_args': '', 'fpu': 'double', 'multiply': True, 'print_outputs': False, 'repeat': None, 'timeout_sec': 0, 'xlen': 32}

FEATURES = {'benchmark', 'bext'}

REQUIRED = {'riscv_gcc.install_dir', 'riscv_gcc.name', 'riscv_gcc.variant'}

property bext_spec

property bext_zba

property bext_zbb

property bext_zbc

property bext_zbs

property enable_bext

property extensions

get_platform_defs(platform)

mlonmcu.target.riscv.riscv_pext_target module

MLonMCU Spike Target definitions

class mlonmcu.target.riscv.riscv_pext_target.RVPTarget(name, features=None, config=None)

Bases: RISCVTarget

TODO

DEFAULTS = {'abi': None, 'arch': None, 'atomic': True, 'attr': '', 'compressed': True, 'cpu': None, 'embedded': False, 'enable_pext': False, 'extensions': [], 'extra_args': '', 'fpu': 'double', 'multiply': True, 'pext_spec': 0.92, 'print_outputs': False, 'repeat': None, 'timeout_sec': 0, 'xlen': 32}

FEATURES = {'benchmark', 'pext'}

REQUIRED = {'riscv_gcc.install_dir', 'riscv_gcc.name', 'riscv_gcc.variant'}

property enable_pext

property extensions

get_platform_defs(platform)

property pext_spec

mlonmcu.target.riscv.riscv_qemu module

MLonMCU RISC-V QEMU Target definitions

class mlonmcu.target.riscv.riscv_qemu.RiscvQemuTarget(name='riscv_qemu', features=None, config=None)

Bases: RISCVTarget

Target using a spike machine in the QEMU simulator

DEFAULTS = {'abi': None, 'arch': None, 'atomic': True, 'attr': '', 'compressed': True, 'cpu': None, 'elen': 32, 'embedded': False, 'embedded_vext': False, 'enable_vext': False, 'extensions': [], 'extra_args': '', 'fpu': 'double', 'multiply': True, 'print_outputs': False, 'repeat': None, 'timeout_sec': 0, 'vext_spec': 1.0, 'vlen': 0, 'xlen': 32}

FEATURES = {'benchmark', 'vext'}

REQUIRED = {'riscv32_qemu.exe', 'riscv_gcc.install_dir', 'riscv_gcc.name', 'riscv_gcc.variant'}

property attr

property elen

property embedded_vext

property enable_vext

exec(program, *args, cwd='/home/runner/work/mlonmcu/mlonmcu/docs', **kwargs)

Use target to execute a executable with given arguments

property extensions

get_cpu_str()

get_metrics(elf, directory, *args, handle_exit=None)

get_platform_defs(platform)

get_qemu_args(program)

get_target_system()

parse_stdout(out, handle_exit=None)

property riscv32_qemu_exe

property vext_spec

property vlen

mlonmcu.target.riscv.riscv_vext_target module

MLonMCU Spike Target definitions

class mlonmcu.target.riscv.riscv_vext_target.RVVTarget(name, features=None, config=None)

Bases: RISCVTarget

TODO

DEFAULTS = {'abi': None, 'arch': None, 'atomic': True, 'attr': '', 'compressed': True, 'cpu': None, 'elen': 64, 'embedded': False, 'embedded_vext': False, 'enable_vext': False, 'extensions': [], 'extra_args': '', 'fpu': 'double', 'multiply': True, 'print_outputs': False, 'repeat': None, 'timeout_sec': 0, 'vext_spec': 1.0, 'vlen': 128, 'xlen': 32}

FEATURES = {'benchmark', 'vext'}

REQUIRED = {'riscv_gcc.install_dir', 'riscv_gcc.name', 'riscv_gcc.variant'}

property attrs

property elen

property embedded_vext

property enable_vext

property extensions

get_backend_config(backend, optimized_layouts=False, optimized_schedules=False)

get_platform_defs(platform)

property vext_spec

property vlen

mlonmcu.target.riscv.spike module

MLonMCU Spike Target definitions

class mlonmcu.target.riscv.spike.SpikeTarget(name='spike', features=None, config=None)

Bases: RVPTarget, RVVTarget, RVBTarget

Target using the riscv-isa-sim (Spike) RISC-V simulator.

DEFAULTS = {'abi': None, 'arch': None, 'atomic': True, 'attr': '', 'bext_spec': 0.92, 'bext_zba': False, 'bext_zbb': False, 'bext_zbc': False, 'bext_zbs': False, 'compressed': True, 'cpu': None, 'elen': 64, 'embedded': False, 'embedded_vext': False, 'enable_bext': False, 'enable_pext': False, 'enable_vext': False, 'extensions': [], 'extra_args': '', 'fpu': 'double', 'multiply': True, 'pext_spec': 0.92, 'print_outputs': False, 'repeat': None, 'spikepk_extra_args': [], 'timeout_sec': 0, 'vext_spec': 1.0, 'vlen': 128, 'xlen': 32}

FEATURES = {'benchmark', 'bext', 'cachesim', 'log_instrs', 'pext', 'vext'}

REQUIRED = {'riscv_gcc.install_dir', 'riscv_gcc.name', 'riscv_gcc.variant', 'spike.exe', 'spike.pk'}

exec(program, *args, cwd='/home/runner/work/mlonmcu/mlonmcu/docs', **kwargs)

Use target to execute a executable with given arguments

property extensions

get_backend_config(backend, optimized_layouts=False, optimized_schedules=False)

get_metrics(elf, directory, *args, handle_exit=None)

get_platform_defs(platform)

property isa

parse_stdout(out, metrics, exit_code=0)

property spike_exe

property spike_pk

property spikepk_extra_args

mlonmcu.target.riscv.spike.filter_unsupported_extensions(exts)

mlonmcu.target.riscv.util module

MLonMCU RISC-V utilities

mlonmcu.target.riscv.util.join_extensions(exts, merge=True)

mlonmcu.target.riscv.util.sort_extensions_canonical(extensions, lower=False, unpack=False)

Utility to get the canonical architecture name string.

mlonmcu.target.riscv.util.split_extensions(inp)

mlonmcu.target.riscv.util.update_extensions(exts, embedded=None, compressed=None, atomic=None, multiply=None, pext=None, pext_spec=None, vext=None, elen=None, embedded_vext=None, vlen=None, fpu=None, minimal=True, bext=None, bext_spec=None, bext_zba=None, bext_zbb=None, bext_zbc=None, bext_zbs=None)

mlonmcu.target.riscv.util.update_extensions_pulp(exts, xpulp_version)

mlonmcu.target.riscv.vicuna module

MLonMCU Vicuna Target definitions

class mlonmcu.target.riscv.vicuna.VicunaTarget(name='vicuna', features=None, config=None)

Bases: RVVTarget

Target using a Pulpino-like VP running in the GVSOC simulator

DEFAULTS = {'abi': None, 'abort_cycles': 10000000, 'arch': None, 'atomic': False, 'attr': '', 'compressed': False, 'core': 'cv32e40x', 'cpu': None, 'dc_line_width': None, 'dc_size': 0, 'elen': 32, 'embedded': False, 'embedded_vext': True, 'enable_vext': False, 'extensions': [], 'extra_args': '', 'extra_cycles': 4096, 'fpu': None, 'ic_line_width': 128, 'ic_size': 0, 'mem_latency': 1, 'mem_size': 524288, 'mem_width': 32, 'multiply': True, 'print_outputs': False, 'repeat': None, 'timeout_sec': 0, 'vext_spec': 1.0, 'vlen': 128, 'vmem_width': None, 'vport_policy': None, 'vproc_config': 'compact', 'vproc_pipelines': None, 'xlen': 32}

FEATURES = {'benchmark', 'log_instrs', 'vext'}

REQUIRED = {'riscv_gcc.install_dir', 'riscv_gcc.name', 'riscv_gcc.variant', 'verilator.install_dir', 'vicuna.src_dir'}

property abort_cycles

property core

property dc_line_width

property dc_size

exec(program, *args, cwd='/home/runner/work/mlonmcu/mlonmcu/docs', **kwargs)

Use target to execute an executable with given arguments

property extra_cycles

get_backend_config(backend, optimized_layouts=False, optimized_schedules=False)

get_config_args()

get_metrics(elf, directory, *args, handle_exit=None)

get_platform_defs(platform)

get_target_system()

property ic_line_width

property ic_size

property mem_latency

property mem_size

property mem_width

parse_exit(out)

parse_stdout(out, metrics, exit_code=0)

prepare_simulator(cwd='/home/runner/work/mlonmcu/mlonmcu/docs', **kwargs)

property verilator_install_dir

property vicuna_src_dir

property vmem_width

property vport_policy

property vproc_config

property vproc_pipelines

mlonmcu.target.riscv.vicuna.logger = <Logger mlonmcu (INFO)>

NOTES

# select the core to use as main processor (defaults to Ibex) CORE ?= ibex CORE_DIR := $(SIM_DIR)/../$(CORE)/

# memory initialization files PROG_PATHS ?= progs.txt

# trace file TRACE_FILE ?= sim_trace.csv TRACE_SIGS ?= ‘*’

Module contents

class mlonmcu.target.riscv.AraRtlTarget(name='ara_rtl', features=None, config=None)

Bases: RVVTarget

TODO

DEFAULTS = {'abi': None, 'arch': None, 'atomic': True, 'attr': '', 'compressed': True, 'cpu': None, 'elen': 64, 'embedded': False, 'embedded_vext': False, 'enable_vext': False, 'extensions': [], 'extra_args': '', 'fpu': 'double', 'limit_cycles': 10000000, 'multiply': True, 'nr_lanes': 4, 'num_threads': 4, 'print_outputs': False, 'repeat': None, 'timeout_sec': 0, 'vext_spec': 1.0, 'vlen': 4096, 'xlen': 64}

FEATURES = {'benchmark', 'log_instrs', 'vext'}

OPTIONAL = {'llvm.install_dir', 'mlif.toolchain', 'questasim.install_dir'}

REQUIRED = {'ara.src_dir', 'riscv_gcc.install_dir', 'riscv_gcc.name', 'riscv_gcc.variant', 'spike.install_dir', 'verilator.install_dir'}

property ara_apps_dir

property ara_hardware_dir

property elen

property embedded_vext

property enable_vext

exec(program, *args, cwd='/home/runner/work/mlonmcu/mlonmcu/docs', **kwargs)

Use target to execute an executable with given arguments

property extensions

get_backend_config(backend, optimized_layouts=False, optimized_schedules=False)

get_metrics(elf, directory, *args, handle_exit=None)

get_platform_defs(platform)

get_target_system()

property limit_cycles

property nr_lanes

property num_threads

parse_exit(out)

parse_stdout(out, metrics, exit_code=0)

prepare_simulator(program, *_, cwd='/home/runner/work/mlonmcu/mlonmcu/docs', **kwargs)

property questasim_install_dir

property spike_install_dir

property verilator_install_dir

property vext_spec

property vlen

class mlonmcu.target.riscv.AraTarget(name='ara', features=None, config=None)

Bases: RVVTarget

Target using a Pulpino-like VP running in the GVSOC simulator

DEFAULTS = {'abi': None, 'arch': None, 'atomic': True, 'attr': '', 'compressed': True, 'cpu': None, 'elen': 64, 'embedded': False, 'embedded_vext': False, 'enable_vext': False, 'extensions': [], 'extra_args': '', 'fpu': 'double', 'limit_cycles': 10000000, 'multiply': True, 'nr_lanes': 4, 'num_threads': 4, 'print_outputs': False, 'repeat': None, 'timeout_sec': 0, 'vext_spec': 1.0, 'vlen': 4096, 'xlen': 64}

FEATURES = {'benchmark', 'log_instrs', 'vext'}

OPTIONAL = {'ara.verilator_tb', 'llvm.install_dir', 'mlif.toolchain'}

REQUIRED = {'ara.src_dir', 'riscv_gcc.install_dir', 'riscv_gcc.name', 'riscv_gcc.variant', 'verilator.install_dir'}

property ara_apps_dir

property ara_hardware_dir

property ara_verilator_tb

property elen

property embedded_vext

property enable_vext

exec(program, *args, cwd='/home/runner/work/mlonmcu/mlonmcu/docs', **kwargs)

Use target to execute an executable with given arguments

property extensions

get_backend_config(backend, optimized_layouts=False, optimized_schedules=False)

get_metrics(elf, directory, *args, handle_exit=None)

get_platform_defs(platform)

get_target_system()

property limit_cycles

property nr_lanes

property num_threads

parse_exit(out)

parse_stdout(out, metrics, exit_code=0)

prepare_simulator(program, *_, cwd='/home/runner/work/mlonmcu/mlonmcu/docs', **kwargs)

property verilator_install_dir

property vext_spec

property vlen

class mlonmcu.target.riscv.COREVOVPSimTarget(name='corev_ovpsim', features=None, config=None)

Bases: RISCVTarget

TODO

DEFAULTS = {'abi': None, 'arch': None, 'atomic': False, 'attr': '', 'compressed': True, 'cpu': None, 'embedded': False, 'enable_xcorevalu': False, 'enable_xcorevbi': False, 'enable_xcorevbitmanip': False, 'enable_xcorevhwlp': False, 'enable_xcorevmac': False, 'enable_xcorevmem': False, 'enable_xcorevsimd': False, 'end_to_end_cycles': False, 'extensions': [], 'extra_args': '', 'fpu': 'none', 'gdbserver_attach': False, 'gdbserver_enable': False, 'gdbserver_port': 2222, 'multiply': True, 'print_outputs': False, 'processor': None, 'repeat': None, 'timeout_sec': 0, 'variant': None, 'xlen': 32}

FEATURES = {'benchmark', 'gdbserver', 'log_instrs', 'trace', 'xcorev'}

REQUIRED = {'corev_ovpsim.exe', 'riscv_gcc.install_dir', 'riscv_gcc.name', 'riscv_gcc.variant'}

property attr

property enable_xcorevalu

property enable_xcorevbi

property enable_xcorevbitmanip

property enable_xcorevhwlp

property enable_xcorevmac

property enable_xcorevmem

property enable_xcorevsimd

property end_to_end_cycles

exec(program, *args, cwd='/home/runner/work/mlonmcu/mlonmcu/docs', **kwargs)

Use target to execute a executable with given arguments

property extensions

property gdbserver_attach

property gdbserver_enable

property gdbserver_port

get_backend_config(backend, optimized_layouts=False, optimized_schedules=False)

get_default_ovpsim_args()

get_metrics(elf, directory, *args, handle_exit=None)

get_platform_defs(platform)

property ovpsim_exe

parse_exit(out)

parse_stdout(out, metrics, exit_code=0)

property processor

property variant

class mlonmcu.target.riscv.CV32E40PTarget(name='cv32e40p', features=None, config=None)

Bases: RISCVTarget

Target for running CV32E40P programs in verilated RTL core.

DEFAULTS = {'abi': None, 'arch': None, 'atomic': False, 'attr': '', 'compressed': True, 'cpu': None, 'embedded': False, 'enable_xcorevalu': False, 'enable_xcorevbi': False, 'enable_xcorevbitmanip': False, 'enable_xcorevhwlp': False, 'enable_xcorevmac': False, 'enable_xcorevmem': False, 'enable_xcorevsimd': False, 'extensions': [], 'extra_args': '', 'fpu': 'none', 'multiply': True, 'print_outputs': False, 'repeat': None, 'timeout_sec': 0, 'xlen': 32}

FEATURES = {'benchmark', 'xcorev'}

REQUIRED = {'cv32e40p.verilator_executable', 'riscv_gcc.install_dir', 'riscv_gcc.name', 'riscv_gcc.variant'}

property attr

property enable_xcorevalu

property enable_xcorevbi

property enable_xcorevbitmanip

property enable_xcorevhwlp

property enable_xcorevmac

property enable_xcorevmem

property enable_xcorevsimd

exec(program, *args, cwd='/home/runner/work/mlonmcu/mlonmcu/docs', **kwargs)

Use target to execute a executable with given arguments

property extensions

get_backend_config(backend, optimized_layouts=False, optimized_schedules=False)

get_metrics(elf, directory, *args, handle_exit=None)

get_platform_defs(platform)

get_target_system()

parse_exit(out)

parse_stdout(out, metrics, exit_code=0)

property verilator_executable

class mlonmcu.target.riscv.EtissPulpinoTarget(name='etiss_pulpino', features=None, config=None)

Bases: EtissTarget

Target using a Pulpino-like VP running in the ETISS simulator

REQUIRED = {'etiss.install_dir', 'etiss.src_dir', 'etissvp.script', 'riscv_gcc.install_dir', 'riscv_gcc.name', 'riscv_gcc.variant'}

get_ini_bool_config()

get_platform_defs(platform)

class mlonmcu.target.riscv.EtissTarget(name='etiss', features=None, config=None)

Bases: RISCVTarget

Target using a simple RISC-V VP running in the ETISS simulator

DEFAULTS = {'abi': None, 'allow_error': False, 'arch': None, 'atomic': True, 'attr': '', 'compressed': True, 'cpu': None, 'cpu_arch': None, 'cycle_time_ps': 31250, 'debug_etiss': False, 'elen': 32, 'embedded': False, 'embedded_vext': False, 'enable_pext': False, 'enable_vext': False, 'enable_xcorevalu': False, 'enable_xcorevbi': False, 'enable_xcorevbitmanip': False, 'enable_xcorevhwlp': False, 'enable_xcorevmac': False, 'enable_xcorevmem': False, 'enable_xcorevsimd': False, 'extensions': [], 'extra_args': '', 'extra_bool_config': {}, 'extra_int_config': {}, 'extra_plugin_config': {}, 'extra_string_config': {}, 'fpu': 'double', 'gdbserver_attach': False, 'gdbserver_enable': False, 'gdbserver_port': 2222, 'jit': None, 'max_block_size': None, 'multiply': True, 'pext_spec': 0.96, 'plugins': [], 'print_outputs': False, 'ram_size': 67108864, 'ram_start': 8388608, 'repeat': None, 'rom_size': 8388608, 'rom_start': 0, 'timeout_sec': 0, 'trace_memory': False, 'verbose': False, 'vext_spec': 1.0, 'vlen': 0, 'xlen': 32}

FEATURES = {'benchmark', 'etissdbg', 'gdbserver', 'log_instrs', 'pext', 'trace', 'vanilla_accelerator', 'vext', 'xcorev'}

REQUIRED = {'etiss.install_dir', 'etiss.src_dir', 'etissvp.script', 'riscv_gcc.install_dir', 'riscv_gcc.name', 'riscv_gcc.variant'}

property allow_error

property attr

property cpu_arch

property cycle_time_ps

property debug_etiss

property elen

property embedded_vext

property enable_pext

property enable_vext

property enable_xcorevalu

property enable_xcorevbi

property enable_xcorevbitmanip

property enable_xcorevhwlp

property enable_xcorevmac

property enable_xcorevmem

property enable_xcorevsimd

property etiss_dir

property etiss_script

property etiss_src_dir

exec(program, *args, cwd='/home/runner/work/mlonmcu/mlonmcu/docs', **kwargs)

Use target to execute a executable with given arguments

property extensions

property extra_bool_config

property extra_int_config

property extra_plugin_config

property extra_string_config

property gdbserver_attach

property gdbserver_enable

property gdbserver_port

get_backend_config(backend, optimized_layouts=False, optimized_schedules=False)

get_ini_bool_config()

get_ini_int_config()

get_ini_plugin_config()

get_ini_string_config()

get_metrics(elf, directory, *args, handle_exit=None)

get_platform_defs(platform)

get_target_system()

property jit

property max_block_size

parse_exit(out)

parse_stdout(out, metrics, exit_code=0)

property pext_spec

property plugins

property ram_size

property ram_start

property rom_size

property rom_start

property trace_memory

property verbose

property vext_spec

property vlen

write_ini(path)

class mlonmcu.target.riscv.GvsocPulpTarget(name='gvsoc_pulp', features=None, config=None)

Bases: RISCVTarget

Target using a Pulpino-like VP running in the GVSOC simulator

DEFAULTS = {'abi': 'ilp32', 'arch': None, 'atomic': True, 'attr': '', 'compressed': True, 'cpu': None, 'embedded': False, 'extensions': ['i', 'm', 'c'], 'extra_args': '', 'fpu': None, 'model': 'pulp', 'multiply': True, 'print_outputs': False, 'repeat': None, 'timeout_sec': 0, 'xlen': 32, 'xpulp_version': None}

FEATURES = {'benchmark', 'log_instrs', 'xpulp'}

REQUIRED = {'gvsoc.exe', 'pulp_freertos.config_dir', 'pulp_freertos.install_dir', 'pulp_freertos.support_dir', 'pulp_gcc.install_dir', 'pulp_gcc.name'}

property abi

exec(program, *args, cwd='/home/runner/work/mlonmcu/mlonmcu/docs', **kwargs)

Use target to execute an executable with given arguments

property extensions

get_backend_config(backend, optimized_layouts=False, optimized_schedules=False)

get_basic_gvsoc_simulating_arg(program)

get_metrics(elf, directory, *args, handle_exit=None)

get_platform_defs(platform)

get_target_system()

property gvsoc_folder

gvsoc_preparation_env()

property gvsoc_script

property model

parse_stdout(out)

property pulp_freertos_config_dir

property pulp_freertos_install_dir

property pulp_freertos_support_dir

property xpulp_version

class mlonmcu.target.riscv.OVPSimTarget(name='ovpsim', features=None, config=None)

Bases: RVPTarget, RVVTarget

Target using an ARM FVP (fixed virtual platform) based on a Cortex M55 with EthosU support

DEFAULTS = {'abi': None, 'arch': None, 'atomic': True, 'attr': '', 'bitmanip_spec': 0.94, 'compressed': True, 'cpu': None, 'elen': 64, 'embedded': False, 'embedded_vext': False, 'enable_pext': False, 'enable_vext': False, 'end_to_end_cycles': True, 'extensions': [], 'extra_args': '', 'fpu': 'double', 'gdbserver_attach': False, 'gdbserver_enable': False, 'gdbserver_port': 2222, 'multiply': True, 'pext_spec': 0.92, 'print_outputs': False, 'repeat': None, 'timeout_sec': 0, 'variant': None, 'vext_spec': 1.0, 'vlen': 128, 'xlen': 32}

FEATURES = {'benchmark', 'gdbserver', 'log_instrs', 'pext', 'trace', 'vext'}

REQUIRED = {'ovpsim.exe', 'riscv_gcc.install_dir', 'riscv_gcc.name', 'riscv_gcc.variant'}

property end_to_end_cycles

exec(program, *args, cwd='/home/runner/work/mlonmcu/mlonmcu/docs', **kwargs)

Use target to execute a executable with given arguments

property extensions

property gdbserver_attach

property gdbserver_enable

property gdbserver_port

get_backend_config(backend, optimized_layouts=False, optimized_schedules=False)

get_default_ovpsim_args()

get_metrics(elf, directory, *args, handle_exit=None)

get_platform_defs(platform)

property ovpsim_exe

parse_stdout(out)

property variant

class mlonmcu.target.riscv.RiscvQemuTarget(name='riscv_qemu', features=None, config=None)

Bases: RISCVTarget

Target using a spike machine in the QEMU simulator

DEFAULTS = {'abi': None, 'arch': None, 'atomic': True, 'attr': '', 'compressed': True, 'cpu': None, 'elen': 32, 'embedded': False, 'embedded_vext': False, 'enable_vext': False, 'extensions': [], 'extra_args': '', 'fpu': 'double', 'multiply': True, 'print_outputs': False, 'repeat': None, 'timeout_sec': 0, 'vext_spec': 1.0, 'vlen': 0, 'xlen': 32}

FEATURES = {'benchmark', 'vext'}

REQUIRED = {'riscv32_qemu.exe', 'riscv_gcc.install_dir', 'riscv_gcc.name', 'riscv_gcc.variant'}

property attr

property elen

property embedded_vext

property enable_vext

exec(program, *args, cwd='/home/runner/work/mlonmcu/mlonmcu/docs', **kwargs)

Use target to execute a executable with given arguments

property extensions

get_cpu_str()

get_metrics(elf, directory, *args, handle_exit=None)

get_platform_defs(platform)

get_qemu_args(program)

get_target_system()

parse_stdout(out, handle_exit=None)

property riscv32_qemu_exe

property vext_spec

property vlen

class mlonmcu.target.riscv.SpikeTarget(name='spike', features=None, config=None)

Bases: RVPTarget, RVVTarget, RVBTarget

Target using the riscv-isa-sim (Spike) RISC-V simulator.

DEFAULTS = {'abi': None, 'arch': None, 'atomic': True, 'attr': '', 'bext_spec': 0.92, 'bext_zba': False, 'bext_zbb': False, 'bext_zbc': False, 'bext_zbs': False, 'compressed': True, 'cpu': None, 'elen': 64, 'embedded': False, 'embedded_vext': False, 'enable_bext': False, 'enable_pext': False, 'enable_vext': False, 'extensions': [], 'extra_args': '', 'fpu': 'double', 'multiply': True, 'pext_spec': 0.92, 'print_outputs': False, 'repeat': None, 'spikepk_extra_args': [], 'timeout_sec': 0, 'vext_spec': 1.0, 'vlen': 128, 'xlen': 32}

FEATURES = {'benchmark', 'bext', 'cachesim', 'log_instrs', 'pext', 'vext'}

REQUIRED = {'riscv_gcc.install_dir', 'riscv_gcc.name', 'riscv_gcc.variant', 'spike.exe', 'spike.pk'}

exec(program, *args, cwd='/home/runner/work/mlonmcu/mlonmcu/docs', **kwargs)

Use target to execute a executable with given arguments

property extensions

get_backend_config(backend, optimized_layouts=False, optimized_schedules=False)

get_metrics(elf, directory, *args, handle_exit=None)

get_platform_defs(platform)

property isa

parse_stdout(out, metrics, exit_code=0)

property spike_exe

property spike_pk

property spikepk_extra_args

class mlonmcu.target.riscv.VicunaTarget(name='vicuna', features=None, config=None)

Bases: RVVTarget

Target using a Pulpino-like VP running in the GVSOC simulator

DEFAULTS = {'abi': None, 'abort_cycles': 10000000, 'arch': None, 'atomic': False, 'attr': '', 'compressed': False, 'core': 'cv32e40x', 'cpu': None, 'dc_line_width': None, 'dc_size': 0, 'elen': 32, 'embedded': False, 'embedded_vext': True, 'enable_vext': False, 'extensions': [], 'extra_args': '', 'extra_cycles': 4096, 'fpu': None, 'ic_line_width': 128, 'ic_size': 0, 'mem_latency': 1, 'mem_size': 524288, 'mem_width': 32, 'multiply': True, 'print_outputs': False, 'repeat': None, 'timeout_sec': 0, 'vext_spec': 1.0, 'vlen': 128, 'vmem_width': None, 'vport_policy': None, 'vproc_config': 'compact', 'vproc_pipelines': None, 'xlen': 32}

FEATURES = {'benchmark', 'log_instrs', 'vext'}

REQUIRED = {'riscv_gcc.install_dir', 'riscv_gcc.name', 'riscv_gcc.variant', 'verilator.install_dir', 'vicuna.src_dir'}

property abort_cycles

property core

property dc_line_width

property dc_size

exec(program, *args, cwd='/home/runner/work/mlonmcu/mlonmcu/docs', **kwargs)

Use target to execute an executable with given arguments

property extra_cycles

get_backend_config(backend, optimized_layouts=False, optimized_schedules=False)

get_config_args()

get_metrics(elf, directory, *args, handle_exit=None)

get_platform_defs(platform)

get_target_system()

property ic_line_width

property ic_size

property mem_latency

property mem_size

property mem_width

parse_exit(out)

parse_stdout(out, metrics, exit_code=0)

prepare_simulator(cwd='/home/runner/work/mlonmcu/mlonmcu/docs', **kwargs)

property verilator_install_dir

property vicuna_src_dir

property vmem_width

property vport_policy

property vproc_config

property vproc_pipelines