ETISS 0.8.0
Extendable Translating Instruction Set Simulator (version 0.8.0)
htmintrin.h
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1 /*===---- htmintrin.h - Standard header for PowerPC HTM ---------------===*\
2  *
3  * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4  * See https://llvm.org/LICENSE.txt for license information.
5  * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6  *
7 \*===----------------------------------------------------------------------===*/
8 
9 #ifndef __HTMINTRIN_H
10 #define __HTMINTRIN_H
11 
12 #ifndef __HTM__
13 #error "HTM instruction set not enabled"
14 #endif
15 
16 #ifdef __powerpc__
17 
18 #include <stdint.h>
19 
20 typedef uint64_t texasr_t;
21 typedef uint32_t texasru_t;
22 typedef uint32_t texasrl_t;
23 typedef uintptr_t tfiar_t;
24 typedef uintptr_t tfhar_t;
25 
26 #define _HTM_STATE(CR0) ((CR0 >> 1) & 0x3)
27 #define _HTM_NONTRANSACTIONAL 0x0
28 #define _HTM_SUSPENDED 0x1
29 #define _HTM_TRANSACTIONAL 0x2
30 
31 #define _TEXASR_EXTRACT_BITS(TEXASR,BITNUM,SIZE) \
32  (((TEXASR) >> (63-(BITNUM))) & ((1<<(SIZE))-1))
33 #define _TEXASRU_EXTRACT_BITS(TEXASR,BITNUM,SIZE) \
34  (((TEXASR) >> (31-(BITNUM))) & ((1<<(SIZE))-1))
35 
36 #define _TEXASR_FAILURE_CODE(TEXASR) \
37  _TEXASR_EXTRACT_BITS(TEXASR, 7, 8)
38 #define _TEXASRU_FAILURE_CODE(TEXASRU) \
39  _TEXASRU_EXTRACT_BITS(TEXASRU, 7, 8)
40 
41 #define _TEXASR_FAILURE_PERSISTENT(TEXASR) \
42  _TEXASR_EXTRACT_BITS(TEXASR, 7, 1)
43 #define _TEXASRU_FAILURE_PERSISTENT(TEXASRU) \
44  _TEXASRU_EXTRACT_BITS(TEXASRU, 7, 1)
45 
46 #define _TEXASR_DISALLOWED(TEXASR) \
47  _TEXASR_EXTRACT_BITS(TEXASR, 8, 1)
48 #define _TEXASRU_DISALLOWED(TEXASRU) \
49  _TEXASRU_EXTRACT_BITS(TEXASRU, 8, 1)
50 
51 #define _TEXASR_NESTING_OVERFLOW(TEXASR) \
52  _TEXASR_EXTRACT_BITS(TEXASR, 9, 1)
53 #define _TEXASRU_NESTING_OVERFLOW(TEXASRU) \
54  _TEXASRU_EXTRACT_BITS(TEXASRU, 9, 1)
55 
56 #define _TEXASR_FOOTPRINT_OVERFLOW(TEXASR) \
57  _TEXASR_EXTRACT_BITS(TEXASR, 10, 1)
58 #define _TEXASRU_FOOTPRINT_OVERFLOW(TEXASRU) \
59  _TEXASRU_EXTRACT_BITS(TEXASRU, 10, 1)
60 
61 #define _TEXASR_SELF_INDUCED_CONFLICT(TEXASR) \
62  _TEXASR_EXTRACT_BITS(TEXASR, 11, 1)
63 #define _TEXASRU_SELF_INDUCED_CONFLICT(TEXASRU) \
64  _TEXASRU_EXTRACT_BITS(TEXASRU, 11, 1)
65 
66 #define _TEXASR_NON_TRANSACTIONAL_CONFLICT(TEXASR) \
67  _TEXASR_EXTRACT_BITS(TEXASR, 12, 1)
68 #define _TEXASRU_NON_TRANSACTIONAL_CONFLICT(TEXASRU) \
69  _TEXASRU_EXTRACT_BITS(TEXASRU, 12, 1)
70 
71 #define _TEXASR_TRANSACTION_CONFLICT(TEXASR) \
72  _TEXASR_EXTRACT_BITS(TEXASR, 13, 1)
73 #define _TEXASRU_TRANSACTION_CONFLICT(TEXASRU) \
74  _TEXASRU_EXTRACT_BITS(TEXASRU, 13, 1)
75 
76 #define _TEXASR_TRANSLATION_INVALIDATION_CONFLICT(TEXASR) \
77  _TEXASR_EXTRACT_BITS(TEXASR, 14, 1)
78 #define _TEXASRU_TRANSLATION_INVALIDATION_CONFLICT(TEXASRU) \
79  _TEXASRU_EXTRACT_BITS(TEXASRU, 14, 1)
80 
81 #define _TEXASR_IMPLEMENTAION_SPECIFIC(TEXASR) \
82  _TEXASR_EXTRACT_BITS(TEXASR, 15, 1)
83 #define _TEXASRU_IMPLEMENTAION_SPECIFIC(TEXASRU) \
84  _TEXASRU_EXTRACT_BITS(TEXASRU, 15, 1)
85 
86 #define _TEXASR_INSTRUCTION_FETCH_CONFLICT(TEXASR) \
87  _TEXASR_EXTRACT_BITS(TEXASR, 16, 1)
88 #define _TEXASRU_INSTRUCTION_FETCH_CONFLICT(TEXASRU) \
89  _TEXASRU_EXTRACT_BITS(TEXASRU, 16, 1)
90 
91 #define _TEXASR_ABORT(TEXASR) \
92  _TEXASR_EXTRACT_BITS(TEXASR, 31, 1)
93 #define _TEXASRU_ABORT(TEXASRU) \
94  _TEXASRU_EXTRACT_BITS(TEXASRU, 31, 1)
95 
96 
97 #define _TEXASR_SUSPENDED(TEXASR) \
98  _TEXASR_EXTRACT_BITS(TEXASR, 32, 1)
99 
100 #define _TEXASR_PRIVILEGE(TEXASR) \
101  _TEXASR_EXTRACT_BITS(TEXASR, 35, 2)
102 
103 #define _TEXASR_FAILURE_SUMMARY(TEXASR) \
104  _TEXASR_EXTRACT_BITS(TEXASR, 36, 1)
105 
106 #define _TEXASR_TFIAR_EXACT(TEXASR) \
107  _TEXASR_EXTRACT_BITS(TEXASR, 37, 1)
108 
109 #define _TEXASR_ROT(TEXASR) \
110  _TEXASR_EXTRACT_BITS(TEXASR, 38, 1)
111 
112 #define _TEXASR_TRANSACTION_LEVEL(TEXASR) \
113  _TEXASR_EXTRACT_BITS(TEXASR, 63, 12)
114 
115 #endif /* __powerpc */
116 
117 #ifdef __s390__
118 
119 /* Condition codes generated by tbegin */
120 #define _HTM_TBEGIN_STARTED 0
121 #define _HTM_TBEGIN_INDETERMINATE 1
122 #define _HTM_TBEGIN_TRANSIENT 2
123 #define _HTM_TBEGIN_PERSISTENT 3
124 
125 /* The abort codes below this threshold are reserved for machine use. */
126 #define _HTM_FIRST_USER_ABORT_CODE 256
127 
128 /* The transaction diagnostic block is it is defined in the Principles
129  of Operation chapter 5-91. */
130 
131 struct __htm_tdb {
132  unsigned char format; /* 0 */
133  unsigned char flags;
134  unsigned char reserved1[4];
135  unsigned short nesting_depth;
136  unsigned long long abort_code; /* 8 */
137  unsigned long long conflict_token; /* 16 */
138  unsigned long long atia; /* 24 */
139  unsigned char eaid; /* 32 */
140  unsigned char dxc;
141  unsigned char reserved2[2];
142  unsigned int program_int_id;
143  unsigned long long exception_id; /* 40 */
144  unsigned long long bea; /* 48 */
145  unsigned char reserved3[72]; /* 56 */
146  unsigned long long gprs[16]; /* 128 */
147 } __attribute__((__packed__, __aligned__ (8)));
148 
149 
150 /* Helper intrinsics to retry tbegin in case of transient failure. */
151 
152 static __inline int __attribute__((__always_inline__, __nodebug__))
153 __builtin_tbegin_retry_null (int __retry)
154 {
155  int cc, i = 0;
156 
157  while ((cc = __builtin_tbegin(0)) == _HTM_TBEGIN_TRANSIENT
158  && i++ < __retry)
159  __builtin_tx_assist(i);
160 
161  return cc;
162 }
163 
164 static __inline int __attribute__((__always_inline__, __nodebug__))
165 __builtin_tbegin_retry_tdb (void *__tdb, int __retry)
166 {
167  int cc, i = 0;
168 
169  while ((cc = __builtin_tbegin(__tdb)) == _HTM_TBEGIN_TRANSIENT
170  && i++ < __retry)
171  __builtin_tx_assist(i);
172 
173  return cc;
174 }
175 
176 #define __builtin_tbegin_retry(tdb, retry) \
177  (__builtin_constant_p(tdb == 0) && tdb == 0 ? \
178  __builtin_tbegin_retry_null(retry) : \
179  __builtin_tbegin_retry_tdb(tdb, retry))
180 
181 static __inline int __attribute__((__always_inline__, __nodebug__))
182 __builtin_tbegin_retry_nofloat_null (int __retry)
183 {
184  int cc, i = 0;
185 
186  while ((cc = __builtin_tbegin_nofloat(0)) == _HTM_TBEGIN_TRANSIENT
187  && i++ < __retry)
188  __builtin_tx_assist(i);
189 
190  return cc;
191 }
192 
193 static __inline int __attribute__((__always_inline__, __nodebug__))
194 __builtin_tbegin_retry_nofloat_tdb (void *__tdb, int __retry)
195 {
196  int cc, i = 0;
197 
198  while ((cc = __builtin_tbegin_nofloat(__tdb)) == _HTM_TBEGIN_TRANSIENT
199  && i++ < __retry)
200  __builtin_tx_assist(i);
201 
202  return cc;
203 }
204 
205 #define __builtin_tbegin_retry_nofloat(tdb, retry) \
206  (__builtin_constant_p(tdb == 0) && tdb == 0 ? \
207  __builtin_tbegin_retry_nofloat_null(retry) : \
208  __builtin_tbegin_retry_nofloat_tdb(tdb, retry))
209 
210 #endif /* __s390__ */
211 
212 #endif /* __HTMINTRIN_H */
_Float16 __2f16 __attribute__((ext_vector_type(2)))
Zeroes the upper 128 bits (bits 255:128) of all YMM registers.
static __inline__ uint32_t
Definition: arm_cde.h:25
static __inline__ uint64_t
Definition: arm_cde.h:31
__UINTPTR_TYPE__ uintptr_t
An unsigned integer type with the property that any valid pointer to void can be converted to this ty...
Definition: opencl-c-base.h:62